include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  28 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  29 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  52 /* Set 1M boot space */
  53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  55                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #ifdef CONFIG_DDR_ECC
  67 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  68 #endif
  69
  70 /*
  71  * Config the L3 Cache as L3 SRAM
  72  */
  73 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  74 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  75 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  76
  77 #define CONFIG_SYS_DCSRBAR      0xf0000000
  78 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  79
  80 /* EEPROM */
  81 #define CONFIG_SYS_I2C_EEPROM_NXID
  82 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  83
  84 /*
  85  * DDR Setup
  86  */
  87 #define CONFIG_VERY_BIG_RAM
  88 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  91 #define SPD_EEPROM_ADDRESS1     0x51
  92 #define SPD_EEPROM_ADDRESS2     0x52
  93 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  94 #define CTRL_INTLV_PREFERED     cacheline
  95
  96 /*
  97  * IFC Definitions
  98  */
  99 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 100 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 101 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 102 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 103                                 CSPR_PORT_SIZE_16 | \
 104                                 CSPR_MSEL_NOR | \
 105                                 CSPR_V)
 106 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 107
 108 /* NOR Flash Timing Params */
 109 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 110
 111 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 112                                 FTIM0_NOR_TEADC(0x5) | \
 113                                 FTIM0_NOR_TEAHC(0x5))
 114 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 115                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 116                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 117 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 118                                 FTIM2_NOR_TCH(0x4) | \
 119                                 FTIM2_NOR_TWPH(0x0E) | \
 120                                 FTIM2_NOR_TWP(0x1c))
 121 #define CONFIG_SYS_NOR_FTIM3    0x0
 122
 123 #define CONFIG_SYS_FLASH_QUIET_TEST
 124 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 125
 126 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 129 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 130
 131 /* CPLD on IFC */
 132 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 133 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 134 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 135 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 136                                 | CSPR_PORT_SIZE_8 \
 137                                 | CSPR_MSEL_GPCM \
 138                                 | CSPR_V)
 139 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 140 #define CONFIG_SYS_CSOR2        0x0
 141
 142 /* CPLD Timing parameters for IFC CS2 */
 143 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 144                                         FTIM0_GPCM_TEADC(0x0e) | \
 145                                         FTIM0_GPCM_TEAHC(0x0e))
 146 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 147                                         FTIM1_GPCM_TRAD(0x1f))
 148 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 149                                         FTIM2_GPCM_TCH(0x8) | \
 150                                         FTIM2_GPCM_TWP(0x1f))
 151 #define CONFIG_SYS_CS2_FTIM3            0x0
 152
 153 /* NAND Flash on IFC */
 154 #define CONFIG_SYS_NAND_BASE            0xff800000
 155 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 156
 157 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 158 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 159                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 160                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 161                                 | CSPR_V)
 162 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 163
 164 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 165                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 166                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 167                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 168                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 169                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 170                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 171
 172 /* ONFI NAND Flash mode0 Timing Params */
 173 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 174                                         FTIM0_NAND_TWP(0x18)    | \
 175                                         FTIM0_NAND_TWCHT(0x07)  | \
 176                                         FTIM0_NAND_TWH(0x0a))
 177 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 178                                         FTIM1_NAND_TWBE(0x39)   | \
 179                                         FTIM1_NAND_TRR(0x0e)    | \
 180                                         FTIM1_NAND_TRP(0x18))
 181 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 182                                         FTIM2_NAND_TREH(0x0a)   | \
 183                                         FTIM2_NAND_TWHRE(0x1e))
 184 #define CONFIG_SYS_NAND_FTIM3           0x0
 185
 186 #define CONFIG_SYS_NAND_DDR_LAW         11
 187 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 188 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 189
 190 #if defined(CONFIG_MTD_RAW_NAND)
 191 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 192 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 193 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 194 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 195 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 196 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 197 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 198 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 199 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 200 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 201 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 202 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 203 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 204 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 205 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 206 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 207 #else
 208 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 209 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 210 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 211 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 212 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 213 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 214 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 215 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 216 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 217 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 218 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 219 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 220 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 221 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 222 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 223 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 224 #endif
 225
 226 #define CONFIG_HWCONFIG
 227
 228 /* define to use L1 as initial stack */
 229 #define CONFIG_L1_INIT_RAM
 230 #define CONFIG_SYS_INIT_RAM_LOCK
 231 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 234 /* The assembler doesn't like typecast */
 235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 236                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 237                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 238 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 239 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 241
 242 /*
 243  * Serial Port
 244  */
 245 #define CONFIG_SYS_NS16550_SERIAL
 246 #define CONFIG_SYS_NS16550_REG_SIZE     1
 247 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 248 #define CONFIG_SYS_BAUDRATE_TABLE       \
 249         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 252 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 253 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 254
 255 /*
 256  * I2C
 257  */
 258
 259 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 260 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 261 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 262 #define I2C_MUX_CH_DEFAULT      0x8
 263
 264 #define I2C_MUX_CH_VOL_MONITOR  0xa
 265
 266 /* The lowest and highest voltage allowed for T208xRDB */
 267 #define VDD_MV_MIN                      819
 268 #define VDD_MV_MAX                      1212
 269
 270 /*
 271  * RapidIO
 272  */
 273 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 274 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 275 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 276 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 277 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 278 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 279 /*
 280  * for slave u-boot IMAGE instored in master memory space,
 281  * PHYS must be aligned based on the SIZE
 282  */
 283 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 284 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 285 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 286 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 287 /*
 288  * for slave UCODE and ENV instored in master memory space,
 289  * PHYS must be aligned based on the SIZE
 290  */
 291 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 292 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 293 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 294
 295 /* slave core release by master*/
 296 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 297 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 298
 299 /*
 300  * SRIO_PCIE_BOOT - SLAVE
 301  */
 302 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 303 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 304 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 305                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 306 #endif
 307
 308 /*
 309  * eSPI - Enhanced SPI
 310  */
 311
 312 /*
 313  * General PCI
 314  * Memory space is mapped 1-1, but I/O space must start from 0.
 315  */
 316 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 317 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 318 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 319 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 320 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 321
 322 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 323 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 324 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 325 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 326 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 327
 328 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 329 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 330 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 331 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 332 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 333
 334 /* controller 4, Base address 203000 */
 335 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 336 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 337 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 338
 339 /* Qman/Bman */
 340 #ifndef CONFIG_NOBQFMAN
 341 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 342 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 343 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 344 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 345 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 346 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 347 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 348 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 349 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 350                                         CONFIG_SYS_BMAN_CENA_SIZE)
 351 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 352 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 353 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 354 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 355 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 356 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 357 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 358 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 359 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 360 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 361 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 362                                         CONFIG_SYS_QMAN_CENA_SIZE)
 363 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 364 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 365
 366 #define CONFIG_SYS_DPAA_FMAN
 367 #define CONFIG_SYS_DPAA_PME
 368 #define CONFIG_SYS_PMAN
 369 #define CONFIG_SYS_DPAA_DCE
 370 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 371 #define CONFIG_SYS_INTERLAKEN
 372
 373 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 374 #endif /* CONFIG_NOBQFMAN */
 375
 376 #ifdef CONFIG_SYS_DPAA_FMAN
 377 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 378 #define RGMII_PHY2_ADDR         0x02
 379 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 380 #define CORTINA_PHY_ADDR2       0x0d
 381 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 382 #define FM1_10GEC3_PHY_ADDR     0x00
 383 #define FM1_10GEC4_PHY_ADDR     0x01
 384 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 385 #define AQR113C_PHY_ADDR1       0x00
 386 #define AQR113C_PHY_ADDR2       0x08
 387 #endif
 388
 389 /*
 390  * USB
 391  */
 392
 393 /*
 394  * SDHC
 395  */
 396 #ifdef CONFIG_MMC
 397 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 398 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 399 #endif
 400
 401 /*
 402  * Dynamic MTD Partition support with mtdparts
 403  */
 404
 405 /*
 406  * Environment
 407  */
 408
 409 /*
 410  * Miscellaneous configurable options
 411  */
 412
 413 /*
 414  * For booting Linux, the board info and command line data
 415  * have to be in the first 64 MB of memory, since this is
 416  * the maximum mapped by the Linux kernel during initialization.
 417  */
 418 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 419
 420 /*
 421  * Environment Configuration
 422  */
 423 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 424 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 425
 426 #define __USB_PHY_TYPE          utmi
 427
 428 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 429         "hwconfig=fsl_ddr:"                                     \
 430         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 431         "bank_intlv=auto;"                                      \
 432         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 433         "netdev=eth0\0"                                         \
 434         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 435         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 436         "tftpflash=tftpboot $loadaddr $uboot && "               \
 437         "protect off $ubootaddr +$filesize && "                 \
 438         "erase $ubootaddr +$filesize && "                       \
 439         "cp.b $loadaddr $ubootaddr $filesize && "               \
 440         "protect on $ubootaddr +$filesize && "                  \
 441         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 442         "consoledev=ttyS0\0"                                    \
 443         "ramdiskaddr=2000000\0"                                 \
 444         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 445         "fdtaddr=1e00000\0"                                     \
 446         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 447         "bdev=sda3\0"
 448
 449 /*
 450  * For emulation this causes u-boot to jump to the start of the
 451  * proof point app code automatically
 452  */
 453 #define PROOF_POINTS                            \
 454         "setenv bootargs root=/dev/$bdev rw "           \
 455         "console=$consoledev,$baudrate $othbootargs;"   \
 456         "cpu 1 release 0x29000000 - - -;"               \
 457         "cpu 2 release 0x29000000 - - -;"               \
 458         "cpu 3 release 0x29000000 - - -;"               \
 459         "cpu 4 release 0x29000000 - - -;"               \
 460         "cpu 5 release 0x29000000 - - -;"               \
 461         "cpu 6 release 0x29000000 - - -;"               \
 462         "cpu 7 release 0x29000000 - - -;"               \
 463         "go 0x29000000"
 464
 465 #define HVBOOT                          \
 466         "setenv bootargs config-addr=0x60000000; "      \
 467         "bootm 0x01000000 - 0x00f00000"
 468
 469 #define ALU                             \
 470         "setenv bootargs root=/dev/$bdev rw "           \
 471         "console=$consoledev,$baudrate $othbootargs;"   \
 472         "cpu 1 release 0x01000000 - - -;"               \
 473         "cpu 2 release 0x01000000 - - -;"               \
 474         "cpu 3 release 0x01000000 - - -;"               \
 475         "cpu 4 release 0x01000000 - - -;"               \
 476         "cpu 5 release 0x01000000 - - -;"               \
 477         "cpu 6 release 0x01000000 - - -;"               \
 478         "cpu 7 release 0x01000000 - - -;"               \
 479         "go 0x01000000"
 480
 481 #include <asm/fsl_secure_boot.h>
 482
 483 #endif  /* __T2080RDB_H */