include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2023 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CFG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CFG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CFG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CFG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CFG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CFG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CFG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CFG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CFG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CFG_RESET_VECTOR_ADDRESS
  59 #define CFG_RESET_VECTOR_ADDRESS        0xeffffffc
  60 #endif
  61
  62 /*
  63  * Config the L3 Cache as L3 SRAM
  64  */
  65 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  66 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  67
  68 #define CFG_SYS_DCSRBAR 0xf0000000
  69 #define CFG_SYS_DCSRBAR_PHYS    0xf00000000ull
  70
  71 /*
  72  * DDR Setup
  73  */
  74 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  75 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  76 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  77 #define SPD_EEPROM_ADDRESS1     0x51
  78 #define SPD_EEPROM_ADDRESS2     0x52
  79 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  80 #define CTRL_INTLV_PREFERED     cacheline
  81
  82 /*
  83  * IFC Definitions
  84  */
  85 #define CFG_SYS_FLASH_BASE              0xe8000000
  86 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  87 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
  88 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  89                                 CSPR_PORT_SIZE_16 | \
  90                                 CSPR_MSEL_NOR | \
  91                                 CSPR_V)
  92 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
  93
  94 /* NOR Flash Timing Params */
  95 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
  96
  97 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
  98                                 FTIM0_NOR_TEADC(0x5) | \
  99                                 FTIM0_NOR_TEAHC(0x5))
 100 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 101                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 102                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 103 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 104                                 FTIM2_NOR_TCH(0x4) | \
 105                                 FTIM2_NOR_TWPH(0x0E) | \
 106                                 FTIM2_NOR_TWP(0x1c))
 107 #define CFG_SYS_NOR_FTIM3       0x0
 108
 109 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS }
 110
 111 /* CPLD on IFC */
 112 #define CFG_SYS_CPLD_BASE       0xffdf0000
 113 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 114 #define CFG_SYS_CSPR2_EXT       (0xf)
 115 #define CFG_SYS_CSPR2   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 116                                 | CSPR_PORT_SIZE_8 \
 117                                 | CSPR_MSEL_GPCM \
 118                                 | CSPR_V)
 119 #define CFG_SYS_AMASK2  IFC_AMASK(64*1024)
 120 #define CFG_SYS_CSOR2   0x0
 121
 122 /* CPLD Timing parameters for IFC CS2 */
 123 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 124                                         FTIM0_GPCM_TEADC(0x0e) | \
 125                                         FTIM0_GPCM_TEAHC(0x0e))
 126 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 127                                         FTIM1_GPCM_TRAD(0x1f))
 128 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 129                                         FTIM2_GPCM_TCH(0x8) | \
 130                                         FTIM2_GPCM_TWP(0x1f))
 131 #define CFG_SYS_CS2_FTIM3               0x0
 132
 133 /* NAND Flash on IFC */
 134 #define CFG_SYS_NAND_BASE               0xff800000
 135 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 136
 137 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 138 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 139                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 140                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 141                                 | CSPR_V)
 142 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 143
 144 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 145                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 146                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 147                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 148                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 149                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 150                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 151
 152 /* ONFI NAND Flash mode0 Timing Params */
 153 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 154                                         FTIM0_NAND_TWP(0x18)    | \
 155                                         FTIM0_NAND_TWCHT(0x07)  | \
 156                                         FTIM0_NAND_TWH(0x0a))
 157 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 158                                         FTIM1_NAND_TWBE(0x39)   | \
 159                                         FTIM1_NAND_TRR(0x0e)    | \
 160                                         FTIM1_NAND_TRP(0x18))
 161 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 162                                         FTIM2_NAND_TREH(0x0a)   | \
 163                                         FTIM2_NAND_TWHRE(0x1e))
 164 #define CFG_SYS_NAND_FTIM3              0x0
 165
 166 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 167
 168 #if defined(CONFIG_MTD_RAW_NAND)
 169 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 170 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 171 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 172 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 173 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 174 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 175 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 176 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 177 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 178 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 179 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 180 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 181 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 182 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 183 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 184 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 185 #else
 186 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 187 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 188 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 189 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 190 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 191 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 192 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 193 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 194 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 195 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 196 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 197 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 198 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 199 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 200 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 201 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 202 #endif
 203
 204 /* define to use L1 as initial stack */
 205 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000 /* Initial L1 address */
 206 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 207 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 208 /* The assembler doesn't like typecast */
 209 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 210                         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 211                         CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 212 #define CFG_SYS_INIT_RAM_SIZE   0x00004000
 213 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 214
 215 /*
 216  * Serial Port
 217  */
 218 #if !CONFIG_IS_ENABLED(DM_SERIAL)
 219 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 220 #endif
 221 #define CFG_SYS_BAUDRATE_TABLE  \
 222         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 223 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
 224 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
 225 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
 226 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 227
 228 /*
 229  * I2C
 230  */
 231
 232 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 233 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 234 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 235 #define I2C_MUX_CH_DEFAULT      0x8
 236
 237 #define I2C_MUX_CH_VOL_MONITOR  0xa
 238
 239 /* The lowest and highest voltage allowed for T208xRDB */
 240 #define VDD_MV_MIN                      819
 241 #define VDD_MV_MAX                      1212
 242
 243 /*
 244  * RapidIO
 245  */
 246 #define CFG_SYS_SRIO1_MEM_VIRT  0xa0000000
 247 #define CFG_SYS_SRIO1_MEM_PHYS  0xc20000000ull
 248 #define CFG_SYS_SRIO1_MEM_SIZE  0x10000000 /* 256M */
 249 #define CFG_SYS_SRIO2_MEM_VIRT  0xb0000000
 250 #define CFG_SYS_SRIO2_MEM_PHYS  0xc30000000ull
 251 #define CFG_SYS_SRIO2_MEM_SIZE  0x10000000 /* 256M */
 252 /*
 253  * for slave u-boot IMAGE instored in master memory space,
 254  * PHYS must be aligned based on the SIZE
 255  */
 256 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 257 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 258 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 259 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 260 /*
 261  * for slave UCODE and ENV instored in master memory space,
 262  * PHYS must be aligned based on the SIZE
 263  */
 264 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 265 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 266 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000    /* 256K */
 267
 268 /* slave core release by master*/
 269 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 270 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 271
 272 /*
 273  * SRIO_PCIE_BOOT - SLAVE
 274  */
 275 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 276 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 277 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 278                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 279 #endif
 280
 281 /*
 282  * eSPI - Enhanced SPI
 283  */
 284
 285 /*
 286  * General PCI
 287  * Memory space is mapped 1-1, but I/O space must start from 0.
 288  */
 289 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 290 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 291 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 292 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 293 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 294
 295 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 296 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 297 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 298 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 299 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 300
 301 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 302 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 303 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 304
 305 /* controller 4, Base address 203000 */
 306 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 307 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 308
 309 /* Qman/Bman */
 310 #ifndef CONFIG_NOBQFMAN
 311 #define CFG_SYS_BMAN_NUM_PORTALS        18
 312 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 313 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 314 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 315 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 316 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 317 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 318 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 319 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 320                                         CFG_SYS_BMAN_CENA_SIZE)
 321 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 322 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 323 #define CFG_SYS_QMAN_NUM_PORTALS        18
 324 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 325 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 326 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 327 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 328 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 329 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 330                                         CFG_SYS_QMAN_CENA_SIZE)
 331 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 332 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 333 #endif /* CONFIG_NOBQFMAN */
 334
 335 #ifdef CONFIG_SYS_DPAA_FMAN
 336 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 337 #define RGMII_PHY2_ADDR         0x02
 338 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 339 #define CORTINA_PHY_ADDR2       0x0d
 340 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 341 #define FM1_10GEC3_PHY_ADDR     0x00
 342 #define FM1_10GEC4_PHY_ADDR     0x01
 343 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 344 #define AQR113C_PHY_ADDR1       0x00
 345 #define AQR113C_PHY_ADDR2       0x08
 346 #endif
 347
 348 /*
 349  * USB
 350  */
 351
 352 /*
 353  * SDHC
 354  */
 355 #ifdef CONFIG_MMC
 356 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 357 #endif
 358
 359 /*
 360  * Dynamic MTD Partition support with mtdparts
 361  */
 362
 363 /*
 364  * Environment
 365  */
 366
 367 /*
 368  * Miscellaneous configurable options
 369  */
 370
 371 /*
 372  * For booting Linux, the board info and command line data
 373  * have to be in the first 64 MB of memory, since this is
 374  * the maximum mapped by the Linux kernel during initialization.
 375  */
 376 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 377
 378 /*
 379  * Environment Configuration
 380  */
 381
 382 #define __USB_PHY_TYPE          utmi
 383
 384 #define CFG_EXTRA_ENV_SETTINGS                          \
 385         "hwconfig=fsl_ddr:"                                     \
 386         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 387         "bank_intlv=auto;"                                      \
 388         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 389         "netdev=eth0\0"                                         \
 390         "uboot=" CONFIG_UBOOTPATH "\0"          \
 391         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 392         "tftpflash=tftpboot $loadaddr $uboot && "               \
 393         "protect off $ubootaddr +$filesize && "                 \
 394         "erase $ubootaddr +$filesize && "                       \
 395         "cp.b $loadaddr $ubootaddr $filesize && "               \
 396         "protect on $ubootaddr +$filesize && "                  \
 397         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 398         "consoledev=ttyS0\0"                                    \
 399         "ramdiskaddr=2000000\0"                                 \
 400         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 401         "fdtaddr=1e00000\0"                                     \
 402         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 403         "bdev=sda3\0"
 404
 405 /*
 406  * For emulation this causes u-boot to jump to the start of the
 407  * proof point app code automatically
 408  */
 409 #define PROOF_POINTS                            \
 410         "setenv bootargs root=/dev/$bdev rw "           \
 411         "console=$consoledev,$baudrate $othbootargs;"   \
 412         "cpu 1 release 0x29000000 - - -;"               \
 413         "cpu 2 release 0x29000000 - - -;"               \
 414         "cpu 3 release 0x29000000 - - -;"               \
 415         "cpu 4 release 0x29000000 - - -;"               \
 416         "cpu 5 release 0x29000000 - - -;"               \
 417         "cpu 6 release 0x29000000 - - -;"               \
 418         "cpu 7 release 0x29000000 - - -;"               \
 419         "go 0x29000000"
 420
 421 #define HVBOOT                          \
 422         "setenv bootargs config-addr=0x60000000; "      \
 423         "bootm 0x01000000 - 0x00f00000"
 424
 425 #define ALU                             \
 426         "setenv bootargs root=/dev/$bdev rw "           \
 427         "console=$consoledev,$baudrate $othbootargs;"   \
 428         "cpu 1 release 0x01000000 - - -;"               \
 429         "cpu 2 release 0x01000000 - - -;"               \
 430         "cpu 3 release 0x01000000 - - -;"               \
 431         "cpu 4 release 0x01000000 - - -;"               \
 432         "cpu 5 release 0x01000000 - - -;"               \
 433         "cpu 6 release 0x01000000 - - -;"               \
 434         "cpu 7 release 0x01000000 - - -;"               \
 435         "go 0x01000000"
 436
 437 #include <asm/fsl_secure_boot.h>
 438
 439 #endif  /* __T2080RDB_H */