include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #ifdef CONFIG_RAMBOOT_PBL
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef CONFIG_MTD_RAW_NAND
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  32 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  33 #endif
  34
  35 #ifdef CONFIG_SPIFLASH
  36 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  41 #endif
  42
  43 #ifdef CONFIG_SDCARD
  44 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  45 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  46 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  47 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  48 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  49 #endif
  50
  51 #endif /* CONFIG_RAMBOOT_PBL */
  52
  53 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  54 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  55 /* Set 1M boot space */
  56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  57 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  58                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  59 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  60 #endif
  61
  62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  63 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  64 #endif
  65
  66 /*
  67  * These can be toggled for performance analysis, otherwise use default.
  68  */
  69 #define CONFIG_SYS_CACHE_STASHING
  70 #ifdef CONFIG_DDR_ECC
  71 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  72 #endif
  73
  74 /*
  75  * Config the L3 Cache as L3 SRAM
  76  */
  77 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  78 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  79 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  80
  81 #define CONFIG_SYS_DCSRBAR      0xf0000000
  82 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  83
  84 /* EEPROM */
  85 #define CONFIG_SYS_I2C_EEPROM_NXID
  86 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CONFIG_VERY_BIG_RAM
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  94 #define CONFIG_SYS_SPD_BUS_NUM  0
  95 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  96 #define SPD_EEPROM_ADDRESS1     0x51
  97 #define SPD_EEPROM_ADDRESS2     0x52
  98 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  99 #define CTRL_INTLV_PREFERED     cacheline
 100
 101 /*
 102  * IFC Definitions
 103  */
 104 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 105 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 106 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 107 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 108                                 CSPR_PORT_SIZE_16 | \
 109                                 CSPR_MSEL_NOR | \
 110                                 CSPR_V)
 111 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 112
 113 /* NOR Flash Timing Params */
 114 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 115
 116 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 117                                 FTIM0_NOR_TEADC(0x5) | \
 118                                 FTIM0_NOR_TEAHC(0x5))
 119 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 120                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 121                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 122 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 123                                 FTIM2_NOR_TCH(0x4) | \
 124                                 FTIM2_NOR_TWPH(0x0E) | \
 125                                 FTIM2_NOR_TWP(0x1c))
 126 #define CONFIG_SYS_NOR_FTIM3    0x0
 127
 128 #define CONFIG_SYS_FLASH_QUIET_TEST
 129 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 130
 131 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 134 #define CONFIG_SYS_FLASH_EMPTY_INFO
 135 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 136
 137 /* CPLD on IFC */
 138 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 139 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 140 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 141 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 142                                 | CSPR_PORT_SIZE_8 \
 143                                 | CSPR_MSEL_GPCM \
 144                                 | CSPR_V)
 145 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 146 #define CONFIG_SYS_CSOR2        0x0
 147
 148 /* CPLD Timing parameters for IFC CS2 */
 149 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 150                                         FTIM0_GPCM_TEADC(0x0e) | \
 151                                         FTIM0_GPCM_TEAHC(0x0e))
 152 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 153                                         FTIM1_GPCM_TRAD(0x1f))
 154 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 155                                         FTIM2_GPCM_TCH(0x8) | \
 156                                         FTIM2_GPCM_TWP(0x1f))
 157 #define CONFIG_SYS_CS2_FTIM3            0x0
 158
 159 /* NAND Flash on IFC */
 160 #define CONFIG_SYS_NAND_BASE            0xff800000
 161 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 162
 163 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 164 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 165                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 166                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 167                                 | CSPR_V)
 168 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 169
 170 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 171                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 172                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 173                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 174                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 175                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 176                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 177
 178 /* ONFI NAND Flash mode0 Timing Params */
 179 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 180                                         FTIM0_NAND_TWP(0x18)    | \
 181                                         FTIM0_NAND_TWCHT(0x07)  | \
 182                                         FTIM0_NAND_TWH(0x0a))
 183 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 184                                         FTIM1_NAND_TWBE(0x39)   | \
 185                                         FTIM1_NAND_TRR(0x0e)    | \
 186                                         FTIM1_NAND_TRP(0x18))
 187 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 188                                         FTIM2_NAND_TREH(0x0a)   | \
 189                                         FTIM2_NAND_TWHRE(0x1e))
 190 #define CONFIG_SYS_NAND_FTIM3           0x0
 191
 192 #define CONFIG_SYS_NAND_DDR_LAW         11
 193 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 194 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 195
 196 #if defined(CONFIG_MTD_RAW_NAND)
 197 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 198 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 199 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 200 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 201 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 202 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 203 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 204 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 205 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 206 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 207 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 208 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 209 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 210 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 211 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 212 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 213 #else
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 216 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 217 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 218 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 219 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 220 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 221 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 222 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 223 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 224 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 225 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 226 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 227 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 228 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 229 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 230 #endif
 231
 232 #if defined(CONFIG_RAMBOOT_PBL)
 233 #define CONFIG_SYS_RAMBOOT
 234 #endif
 235
 236 #define CONFIG_HWCONFIG
 237
 238 /* define to use L1 as initial stack */
 239 #define CONFIG_L1_INIT_RAM
 240 #define CONFIG_SYS_INIT_RAM_LOCK
 241 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 244 /* The assembler doesn't like typecast */
 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 246                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 247                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 248 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 249 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 250 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 251
 252 /*
 253  * Serial Port
 254  */
 255 #define CONFIG_SYS_NS16550_SERIAL
 256 #define CONFIG_SYS_NS16550_REG_SIZE     1
 257 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 258 #define CONFIG_SYS_BAUDRATE_TABLE       \
 259         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 262 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 263 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 264
 265 /*
 266  * I2C
 267  */
 268
 269 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 270 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 271 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 272 #define I2C_MUX_CH_DEFAULT      0x8
 273
 274 #define I2C_MUX_CH_VOL_MONITOR  0xa
 275
 276 /* The lowest and highest voltage allowed for T208xRDB */
 277 #define VDD_MV_MIN                      819
 278 #define VDD_MV_MAX                      1212
 279
 280 /*
 281  * RapidIO
 282  */
 283 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 284 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 285 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 286 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 287 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 288 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 289 /*
 290  * for slave u-boot IMAGE instored in master memory space,
 291  * PHYS must be aligned based on the SIZE
 292  */
 293 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 294 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 295 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 296 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 297 /*
 298  * for slave UCODE and ENV instored in master memory space,
 299  * PHYS must be aligned based on the SIZE
 300  */
 301 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 302 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 303 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 304
 305 /* slave core release by master*/
 306 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 307 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 308
 309 /*
 310  * SRIO_PCIE_BOOT - SLAVE
 311  */
 312 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 313 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 314 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 315                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 316 #endif
 317
 318 /*
 319  * eSPI - Enhanced SPI
 320  */
 321
 322 /*
 323  * General PCI
 324  * Memory space is mapped 1-1, but I/O space must start from 0.
 325  */
 326 #define CONFIG_PCIE1            /* PCIE controller 1 */
 327 #define CONFIG_PCIE2            /* PCIE controller 2 */
 328 #define CONFIG_PCIE3            /* PCIE controller 3 */
 329 #define CONFIG_PCIE4            /* PCIE controller 4 */
 330 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 331 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 332 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 333 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 334 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 335
 336 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 337 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 338 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 339 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 340 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 341
 342 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 343 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 344 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 345 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 346 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 347
 348 /* controller 4, Base address 203000 */
 349 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 350 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 351 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 352
 353 #ifdef CONFIG_PCI
 354 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 355 #endif
 356
 357 /* Qman/Bman */
 358 #ifndef CONFIG_NOBQFMAN
 359 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 360 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 361 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 362 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 363 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 364 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 365 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 366 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 367 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 368                                         CONFIG_SYS_BMAN_CENA_SIZE)
 369 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 370 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 371 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 372 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 373 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 374 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 375 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 376 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 377 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 378 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 379 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 380                                         CONFIG_SYS_QMAN_CENA_SIZE)
 381 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 382 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 383
 384 #define CONFIG_SYS_DPAA_FMAN
 385 #define CONFIG_SYS_DPAA_PME
 386 #define CONFIG_SYS_PMAN
 387 #define CONFIG_SYS_DPAA_DCE
 388 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 389 #define CONFIG_SYS_INTERLAKEN
 390
 391 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 392 #endif /* CONFIG_NOBQFMAN */
 393
 394 #ifdef CONFIG_SYS_DPAA_FMAN
 395 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 396 #define RGMII_PHY2_ADDR         0x02
 397 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 398 #define CORTINA_PHY_ADDR2       0x0d
 399 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 400 #define FM1_10GEC3_PHY_ADDR     0x00
 401 #define FM1_10GEC4_PHY_ADDR     0x01
 402 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 403 #define AQR113C_PHY_ADDR1       0x00
 404 #define AQR113C_PHY_ADDR2       0x08
 405 #endif
 406
 407 /*
 408  * USB
 409  */
 410
 411 /*
 412  * SDHC
 413  */
 414 #ifdef CONFIG_MMC
 415 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 416 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 417 #endif
 418
 419 /*
 420  * Dynamic MTD Partition support with mtdparts
 421  */
 422
 423 /*
 424  * Environment
 425  */
 426
 427 /*
 428  * Miscellaneous configurable options
 429  */
 430
 431 /*
 432  * For booting Linux, the board info and command line data
 433  * have to be in the first 64 MB of memory, since this is
 434  * the maximum mapped by the Linux kernel during initialization.
 435  */
 436 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 437 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 438
 439 /*
 440  * Environment Configuration
 441  */
 442 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 443 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 444
 445 #define __USB_PHY_TYPE          utmi
 446
 447 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 448         "hwconfig=fsl_ddr:"                                     \
 449         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 450         "bank_intlv=auto;"                                      \
 451         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 452         "netdev=eth0\0"                                         \
 453         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 454         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 455         "tftpflash=tftpboot $loadaddr $uboot && "               \
 456         "protect off $ubootaddr +$filesize && "                 \
 457         "erase $ubootaddr +$filesize && "                       \
 458         "cp.b $loadaddr $ubootaddr $filesize && "               \
 459         "protect on $ubootaddr +$filesize && "                  \
 460         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 461         "consoledev=ttyS0\0"                                    \
 462         "ramdiskaddr=2000000\0"                                 \
 463         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 464         "fdtaddr=1e00000\0"                                     \
 465         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 466         "bdev=sda3\0"
 467
 468 /*
 469  * For emulation this causes u-boot to jump to the start of the
 470  * proof point app code automatically
 471  */
 472 #define PROOF_POINTS                            \
 473         "setenv bootargs root=/dev/$bdev rw "           \
 474         "console=$consoledev,$baudrate $othbootargs;"   \
 475         "cpu 1 release 0x29000000 - - -;"               \
 476         "cpu 2 release 0x29000000 - - -;"               \
 477         "cpu 3 release 0x29000000 - - -;"               \
 478         "cpu 4 release 0x29000000 - - -;"               \
 479         "cpu 5 release 0x29000000 - - -;"               \
 480         "cpu 6 release 0x29000000 - - -;"               \
 481         "cpu 7 release 0x29000000 - - -;"               \
 482         "go 0x29000000"
 483
 484 #define HVBOOT                          \
 485         "setenv bootargs config-addr=0x60000000; "      \
 486         "bootm 0x01000000 - 0x00f00000"
 487
 488 #define ALU                             \
 489         "setenv bootargs root=/dev/$bdev rw "           \
 490         "console=$consoledev,$baudrate $othbootargs;"   \
 491         "cpu 1 release 0x01000000 - - -;"               \
 492         "cpu 2 release 0x01000000 - - -;"               \
 493         "cpu 3 release 0x01000000 - - -;"               \
 494         "cpu 4 release 0x01000000 - - -;"               \
 495         "cpu 5 release 0x01000000 - - -;"               \
 496         "cpu 6 release 0x01000000 - - -;"               \
 497         "cpu 7 release 0x01000000 - - -;"               \
 498         "go 0x01000000"
 499
 500 #include <asm/fsl_secure_boot.h>
 501
 502 #endif  /* __T2080RDB_H */