include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_FSL_SATA_V2
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  19 #define CONFIG_MP               /* support multiple processors */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #ifdef CONFIG_PHYS_64BIT
  23 #define CONFIG_ADDR_MAP 1
  24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  25 #endif
  26
  27 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  29 #define CONFIG_ENV_OVERWRITE
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  36 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  37 #define CONFIG_SPL_PAD_TO               0x40000
  38 #define CONFIG_SPL_MAX_SIZE             0x28000
  39 #define RESET_VECTOR_OFFSET             0x27FFC
  40 #define BOOT_PAGE_OFFSET                0x27000
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_SKIP_RELOCATE
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  45 #endif
  46
  47 #ifdef CONFIG_NAND
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  51 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  52 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  54 #define CONFIG_SPL_NAND_BOOT
  55 #endif
  56
  57 #ifdef CONFIG_SPIFLASH
  58 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  64 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  69 #define CONFIG_SPL_SPI_BOOT
  70 #endif
  71
  72 #ifdef CONFIG_SDCARD
  73 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  74 #define CONFIG_SPL_MMC_MINIMAL
  75 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  76 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  77 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  78 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  79 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  80 #ifndef CONFIG_SPL_BUILD
  81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  82 #endif
  83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  84 #define CONFIG_SPL_MMC_BOOT
  85 #endif
  86
  87 #endif /* CONFIG_RAMBOOT_PBL */
  88
  89 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  90 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  91 /* Set 1M boot space */
  92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  94                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  95 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  96 #endif
  97
  98 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  99 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 100 #endif
 101
 102 /*
 103  * These can be toggled for performance analysis, otherwise use default.
 104  */
 105 #define CONFIG_SYS_CACHE_STASHING
 106 #define CONFIG_BTB              /* toggle branch predition */
 107 #define CONFIG_DDR_ECC
 108 #ifdef CONFIG_DDR_ECC
 109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 110 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 111 #endif
 112
 113 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 114 #define CONFIG_SYS_MEMTEST_END          0x00400000
 115 #define CONFIG_SYS_ALT_MEMTEST
 116
 117 #ifdef CONFIG_MTD_NOR_FLASH
 118 #define CONFIG_FLASH_CFI_DRIVER
 119 #define CONFIG_SYS_FLASH_CFI
 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 121 #endif
 122
 123 #if defined(CONFIG_SPIFLASH)
 124 #define CONFIG_SYS_EXTRA_ENV_RELOC
 125 #define CONFIG_ENV_SPI_BUS      0
 126 #define CONFIG_ENV_SPI_CS       0
 127 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 128 #define CONFIG_ENV_SPI_MODE     0
 129 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 130 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 131 #define CONFIG_ENV_SECT_SIZE    0x10000
 132 #elif defined(CONFIG_SDCARD)
 133 #define CONFIG_SYS_EXTRA_ENV_RELOC
 134 #define CONFIG_SYS_MMC_ENV_DEV  0
 135 #define CONFIG_ENV_SIZE         0x2000
 136 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 137 #elif defined(CONFIG_NAND)
 138 #define CONFIG_SYS_EXTRA_ENV_RELOC
 139 #define CONFIG_ENV_SIZE         0x2000
 140 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 141 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 142 #define CONFIG_ENV_ADDR         0xffe20000
 143 #define CONFIG_ENV_SIZE         0x2000
 144 #elif defined(CONFIG_ENV_IS_NOWHERE)
 145 #define CONFIG_ENV_SIZE         0x2000
 146 #else
 147 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 148 #define CONFIG_ENV_SIZE         0x2000
 149 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 150 #endif
 151
 152 #ifndef __ASSEMBLY__
 153 unsigned long get_board_sys_clk(void);
 154 unsigned long get_board_ddr_clk(void);
 155 #endif
 156
 157 #define CONFIG_SYS_CLK_FREQ     66660000
 158 #define CONFIG_DDR_CLK_FREQ     133330000
 159
 160 /*
 161  * Config the L3 Cache as L3 SRAM
 162  */
 163 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 164 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 165 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 166 #ifdef CONFIG_RAMBOOT_PBL
 167 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 168 #endif
 169 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 170 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 171 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 172 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 173
 174 #define CONFIG_SYS_DCSRBAR      0xf0000000
 175 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 176
 177 /* EEPROM */
 178 #define CONFIG_ID_EEPROM
 179 #define CONFIG_SYS_I2C_EEPROM_NXID
 180 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 183
 184 /*
 185  * DDR Setup
 186  */
 187 #define CONFIG_VERY_BIG_RAM
 188 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 189 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 190 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 191 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 192 #define CONFIG_DDR_SPD
 193 #undef CONFIG_FSL_DDR_INTERACTIVE
 194 #define CONFIG_SYS_SPD_BUS_NUM  0
 195 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 196 #define SPD_EEPROM_ADDRESS1     0x51
 197 #define SPD_EEPROM_ADDRESS2     0x52
 198 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 199 #define CTRL_INTLV_PREFERED     cacheline
 200
 201 /*
 202  * IFC Definitions
 203  */
 204 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 205 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 206 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 207 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 208                                 CSPR_PORT_SIZE_16 | \
 209                                 CSPR_MSEL_NOR | \
 210                                 CSPR_V)
 211 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 212
 213 /* NOR Flash Timing Params */
 214 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 215
 216 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 217                                 FTIM0_NOR_TEADC(0x5) | \
 218                                 FTIM0_NOR_TEAHC(0x5))
 219 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 220                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 221                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 222 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 223                                 FTIM2_NOR_TCH(0x4) | \
 224                                 FTIM2_NOR_TWPH(0x0E) | \
 225                                 FTIM2_NOR_TWP(0x1c))
 226 #define CONFIG_SYS_NOR_FTIM3    0x0
 227
 228 #define CONFIG_SYS_FLASH_QUIET_TEST
 229 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 230
 231 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 232 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 235 #define CONFIG_SYS_FLASH_EMPTY_INFO
 236 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 237
 238 /* CPLD on IFC */
 239 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 240 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 241 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 242 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 243                                 | CSPR_PORT_SIZE_8 \
 244                                 | CSPR_MSEL_GPCM \
 245                                 | CSPR_V)
 246 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 247 #define CONFIG_SYS_CSOR2        0x0
 248
 249 /* CPLD Timing parameters for IFC CS2 */
 250 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 251                                         FTIM0_GPCM_TEADC(0x0e) | \
 252                                         FTIM0_GPCM_TEAHC(0x0e))
 253 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 254                                         FTIM1_GPCM_TRAD(0x1f))
 255 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 256                                         FTIM2_GPCM_TCH(0x8) | \
 257                                         FTIM2_GPCM_TWP(0x1f))
 258 #define CONFIG_SYS_CS2_FTIM3            0x0
 259
 260 /* NAND Flash on IFC */
 261 #define CONFIG_NAND_FSL_IFC
 262 #define CONFIG_SYS_NAND_BASE            0xff800000
 263 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 264
 265 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 266 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 267                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 268                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 269                                 | CSPR_V)
 270 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 271
 272 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 273                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 274                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 275                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 276                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 277                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 278                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 279
 280 #define CONFIG_SYS_NAND_ONFI_DETECTION
 281
 282 /* ONFI NAND Flash mode0 Timing Params */
 283 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 284                                         FTIM0_NAND_TWP(0x18)    | \
 285                                         FTIM0_NAND_TWCHT(0x07)  | \
 286                                         FTIM0_NAND_TWH(0x0a))
 287 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 288                                         FTIM1_NAND_TWBE(0x39)   | \
 289                                         FTIM1_NAND_TRR(0x0e)    | \
 290                                         FTIM1_NAND_TRP(0x18))
 291 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 292                                         FTIM2_NAND_TREH(0x0a)   | \
 293                                         FTIM2_NAND_TWHRE(0x1e))
 294 #define CONFIG_SYS_NAND_FTIM3           0x0
 295
 296 #define CONFIG_SYS_NAND_DDR_LAW         11
 297 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 298 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 299 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 300
 301 #if defined(CONFIG_NAND)
 302 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 303 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 304 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 305 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 306 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 307 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 308 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 309 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 310 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 311 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 312 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #else
 319 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 335 #endif
 336
 337 #if defined(CONFIG_RAMBOOT_PBL)
 338 #define CONFIG_SYS_RAMBOOT
 339 #endif
 340
 341 #ifdef CONFIG_SPL_BUILD
 342 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 343 #else
 344 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 345 #endif
 346
 347 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 348 #define CONFIG_MISC_INIT_R
 349 #define CONFIG_HWCONFIG
 350
 351 /* define to use L1 as initial stack */
 352 #define CONFIG_L1_INIT_RAM
 353 #define CONFIG_SYS_INIT_RAM_LOCK
 354 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 357 /* The assembler doesn't like typecast */
 358 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 359                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 360                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 361 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 362 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 363                                                 GENERATED_GBL_DATA_SIZE)
 364 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 365 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 366 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 367
 368 /*
 369  * Serial Port
 370  */
 371 #define CONFIG_CONS_INDEX               1
 372 #define CONFIG_SYS_NS16550_SERIAL
 373 #define CONFIG_SYS_NS16550_REG_SIZE     1
 374 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 375 #define CONFIG_SYS_BAUDRATE_TABLE       \
 376         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 379 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 380 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 381
 382 /*
 383  * I2C
 384  */
 385 #define CONFIG_SYS_I2C
 386 #define CONFIG_SYS_I2C_FSL
 387 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 388 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 389 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 390 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 391 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 392 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 393 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 394 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 395 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 396 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 397 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 398 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 399 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 400 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 401 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 402 #define I2C_MUX_CH_DEFAULT      0x8
 403
 404 #define I2C_MUX_CH_VOL_MONITOR  0xa
 405
 406 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 407 #ifndef CONFIG_SPL_BUILD
 408 #define CONFIG_VID
 409 #endif
 410 #define CONFIG_VOL_MONITOR_IR36021_SET
 411 #define CONFIG_VOL_MONITOR_IR36021_READ
 412 /* The lowest and highest voltage allowed for T208xRDB */
 413 #define VDD_MV_MIN                      819
 414 #define VDD_MV_MAX                      1212
 415
 416 /*
 417  * RapidIO
 418  */
 419 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 420 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 421 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 422 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 423 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 424 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 425 /*
 426  * for slave u-boot IMAGE instored in master memory space,
 427  * PHYS must be aligned based on the SIZE
 428  */
 429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 430 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 431 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 432 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 433 /*
 434  * for slave UCODE and ENV instored in master memory space,
 435  * PHYS must be aligned based on the SIZE
 436  */
 437 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 438 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 439 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 440
 441 /* slave core release by master*/
 442 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 443 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 444
 445 /*
 446  * SRIO_PCIE_BOOT - SLAVE
 447  */
 448 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 449 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 450 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 451                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 452 #endif
 453
 454 /*
 455  * eSPI - Enhanced SPI
 456  */
 457 #ifdef CONFIG_SPI_FLASH
 458 #define CONFIG_SPI_FLASH_BAR
 459 #define CONFIG_SF_DEFAULT_SPEED  10000000
 460 #define CONFIG_SF_DEFAULT_MODE    0
 461 #endif
 462
 463 /*
 464  * General PCI
 465  * Memory space is mapped 1-1, but I/O space must start from 0.
 466  */
 467 #define CONFIG_PCIE1            /* PCIE controller 1 */
 468 #define CONFIG_PCIE2            /* PCIE controller 2 */
 469 #define CONFIG_PCIE3            /* PCIE controller 3 */
 470 #define CONFIG_PCIE4            /* PCIE controller 4 */
 471 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 472 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 473 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 474 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 475 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 476 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 477 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 478 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 479 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 480 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 481 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 482
 483 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 484 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 485 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 486 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 487 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 488 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 489 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 490 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 491 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 492
 493 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 494 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 495 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 496 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 497 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 498 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 499 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 500 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 501 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 502
 503 /* controller 4, Base address 203000 */
 504 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 505 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 506 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 507 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 508 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 509 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 510 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 511
 512 #ifdef CONFIG_PCI
 513 #define CONFIG_PCI_INDIRECT_BRIDGE
 514 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 515 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 516 #endif
 517
 518 /* Qman/Bman */
 519 #ifndef CONFIG_NOBQFMAN
 520 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 521 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 522 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 523 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 524 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 525 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 526 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 527 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 528 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 529                                         CONFIG_SYS_BMAN_CENA_SIZE)
 530 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 531 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 532 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 533 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 534 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 535 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 536 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 537 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 538 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 539 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 540 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 541                                         CONFIG_SYS_QMAN_CENA_SIZE)
 542 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 543 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 544
 545 #define CONFIG_SYS_DPAA_FMAN
 546 #define CONFIG_SYS_DPAA_PME
 547 #define CONFIG_SYS_PMAN
 548 #define CONFIG_SYS_DPAA_DCE
 549 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 550 #define CONFIG_SYS_INTERLAKEN
 551
 552 /* Default address of microcode for the Linux Fman driver */
 553 #if defined(CONFIG_SPIFLASH)
 554 /*
 555  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 556  * env, so we got 0x110000.
 557  */
 558 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 559 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 560 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 561 #define CONFIG_CORTINA_FW_ADDR          0x120000
 562
 563 #elif defined(CONFIG_SDCARD)
 564 /*
 565  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 566  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 567  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 568  */
 569 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 570 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 571 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 572 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 573
 574 #elif defined(CONFIG_NAND)
 575 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 576 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 577 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 578 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 579 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 580 /*
 581  * Slave has no ucode locally, it can fetch this from remote. When implementing
 582  * in two corenet boards, slave's ucode could be stored in master's memory
 583  * space, the address can be mapped from slave TLB->slave LAW->
 584  * slave SRIO or PCIE outbound window->master inbound window->
 585  * master LAW->the ucode address in master's memory space.
 586  */
 587 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 588 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 589 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 590 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 591 #else
 592 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 593 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 594 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 595 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 596 #endif
 597 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 598 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 599 #endif /* CONFIG_NOBQFMAN */
 600
 601 #ifdef CONFIG_SYS_DPAA_FMAN
 602 #define CONFIG_FMAN_ENET
 603 #define CONFIG_PHYLIB_10G
 604 #define CONFIG_PHY_AQUANTIA
 605 #define CONFIG_PHY_CORTINA
 606 #define CONFIG_PHY_REALTEK
 607 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 608 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 609 #define RGMII_PHY2_ADDR         0x02
 610 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 611 #define CORTINA_PHY_ADDR2       0x0d
 612 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 613 #define FM1_10GEC4_PHY_ADDR     0x01
 614 #endif
 615
 616 #ifdef CONFIG_FMAN_ENET
 617 #define CONFIG_MII              /* MII PHY management */
 618 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 619 #endif
 620
 621 /*
 622  * SATA
 623  */
 624 #ifdef CONFIG_FSL_SATA_V2
 625 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 626 #define CONFIG_SATA1
 627 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 628 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 629 #define CONFIG_SATA2
 630 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 631 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 632 #define CONFIG_LBA48
 633 #endif
 634
 635 /*
 636  * USB
 637  */
 638 #ifdef CONFIG_USB_EHCI_HCD
 639 #define CONFIG_USB_EHCI_FSL
 640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 641 #define CONFIG_HAS_FSL_DR_USB
 642 #endif
 643
 644 /*
 645  * SDHC
 646  */
 647 #ifdef CONFIG_MMC
 648 #define CONFIG_FSL_ESDHC
 649 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 650 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 651 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 652 #endif
 653
 654 /*
 655  * Dynamic MTD Partition support with mtdparts
 656  */
 657 #ifdef CONFIG_MTD_NOR_FLASH
 658 #define CONFIG_MTD_DEVICE
 659 #define CONFIG_MTD_PARTITIONS
 660 #define CONFIG_FLASH_CFI_MTD
 661 #endif
 662
 663 /*
 664  * Environment
 665  */
 666
 667 /*
 668  * Miscellaneous configurable options
 669  */
 670 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 671 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 672 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 673 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 674
 675 /*
 676  * For booting Linux, the board info and command line data
 677  * have to be in the first 64 MB of memory, since this is
 678  * the maximum mapped by the Linux kernel during initialization.
 679  */
 680 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 681 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 682
 683 #ifdef CONFIG_CMD_KGDB
 684 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 685 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 686 #endif
 687
 688 /*
 689  * Environment Configuration
 690  */
 691 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 692 #define CONFIG_BOOTFILE  "uImage"
 693 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 694
 695 /* default location for tftp and bootm */
 696 #define CONFIG_LOADADDR         1000000
 697 #define __USB_PHY_TYPE          utmi
 698
 699 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 700         "hwconfig=fsl_ddr:"                                     \
 701         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 702         "bank_intlv=auto;"                                      \
 703         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 704         "netdev=eth0\0"                                         \
 705         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 706         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 707         "tftpflash=tftpboot $loadaddr $uboot && "               \
 708         "protect off $ubootaddr +$filesize && "                 \
 709         "erase $ubootaddr +$filesize && "                       \
 710         "cp.b $loadaddr $ubootaddr $filesize && "               \
 711         "protect on $ubootaddr +$filesize && "                  \
 712         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 713         "consoledev=ttyS0\0"                                    \
 714         "ramdiskaddr=2000000\0"                                 \
 715         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 716         "fdtaddr=1e00000\0"                                     \
 717         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 718         "bdev=sda3\0"
 719
 720 /*
 721  * For emulation this causes u-boot to jump to the start of the
 722  * proof point app code automatically
 723  */
 724 #define CONFIG_PROOF_POINTS                             \
 725         "setenv bootargs root=/dev/$bdev rw "           \
 726         "console=$consoledev,$baudrate $othbootargs;"   \
 727         "cpu 1 release 0x29000000 - - -;"               \
 728         "cpu 2 release 0x29000000 - - -;"               \
 729         "cpu 3 release 0x29000000 - - -;"               \
 730         "cpu 4 release 0x29000000 - - -;"               \
 731         "cpu 5 release 0x29000000 - - -;"               \
 732         "cpu 6 release 0x29000000 - - -;"               \
 733         "cpu 7 release 0x29000000 - - -;"               \
 734         "go 0x29000000"
 735
 736 #define CONFIG_HVBOOT                           \
 737         "setenv bootargs config-addr=0x60000000; "      \
 738         "bootm 0x01000000 - 0x00f00000"
 739
 740 #define CONFIG_ALU                              \
 741         "setenv bootargs root=/dev/$bdev rw "           \
 742         "console=$consoledev,$baudrate $othbootargs;"   \
 743         "cpu 1 release 0x01000000 - - -;"               \
 744         "cpu 2 release 0x01000000 - - -;"               \
 745         "cpu 3 release 0x01000000 - - -;"               \
 746         "cpu 4 release 0x01000000 - - -;"               \
 747         "cpu 5 release 0x01000000 - - -;"               \
 748         "cpu 6 release 0x01000000 - - -;"               \
 749         "cpu 7 release 0x01000000 - - -;"               \
 750         "go 0x01000000"
 751
 752 #define CONFIG_LINUX                            \
 753         "setenv bootargs root=/dev/ram rw "             \
 754         "console=$consoledev,$baudrate $othbootargs;"   \
 755         "setenv ramdiskaddr 0x02000000;"                \
 756         "setenv fdtaddr 0x00c00000;"                    \
 757         "setenv loadaddr 0x1000000;"                    \
 758         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 759
 760 #define CONFIG_HDBOOT                                   \
 761         "setenv bootargs root=/dev/$bdev rw "           \
 762         "console=$consoledev,$baudrate $othbootargs;"   \
 763         "tftp $loadaddr $bootfile;"                     \
 764         "tftp $fdtaddr $fdtfile;"                       \
 765         "bootm $loadaddr - $fdtaddr"
 766
 767 #define CONFIG_NFSBOOTCOMMAND                   \
 768         "setenv bootargs root=/dev/nfs rw "     \
 769         "nfsroot=$serverip:$rootpath "          \
 770         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 771         "console=$consoledev,$baudrate $othbootargs;"   \
 772         "tftp $loadaddr $bootfile;"             \
 773         "tftp $fdtaddr $fdtfile;"               \
 774         "bootm $loadaddr - $fdtaddr"
 775
 776 #define CONFIG_RAMBOOTCOMMAND                           \
 777         "setenv bootargs root=/dev/ram rw "             \
 778         "console=$consoledev,$baudrate $othbootargs;"   \
 779         "tftp $ramdiskaddr $ramdiskfile;"               \
 780         "tftp $loadaddr $bootfile;"                     \
 781         "tftp $fdtaddr $fdtfile;"                       \
 782         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 783
 784 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 785
 786 #include <asm/fsl_secure_boot.h>
 787
 788 #endif  /* __T2080RDB_H */