include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #define CONFIG_FSL_SATA_V2
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #ifdef CONFIG_RAMBOOT_PBL
  27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  28
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #endif
  39
  40 #ifdef CONFIG_MTD_RAW_NAND
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  42 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  43 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  44 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  46 #endif
  47
  48 #ifdef CONFIG_SPIFLASH
  49 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  55 #ifndef CONFIG_SPL_BUILD
  56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  57 #endif
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  59 #endif
  60
  61 #ifdef CONFIG_SDCARD
  62 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  63 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  64 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  65 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  66 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  67 #ifndef CONFIG_SPL_BUILD
  68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  69 #endif
  70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  71 #endif
  72
  73 #endif /* CONFIG_RAMBOOT_PBL */
  74
  75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  77 /* Set 1M boot space */
  78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  80                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  82 #endif
  83
  84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  85 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  86 #endif
  87
  88 /*
  89  * These can be toggled for performance analysis, otherwise use default.
  90  */
  91 #define CONFIG_SYS_CACHE_STASHING
  92 #define CONFIG_BTB              /* toggle branch predition */
  93 #ifdef CONFIG_DDR_ECC
  94 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  95 #endif
  96
  97 #ifndef __ASSEMBLY__
  98 unsigned long get_board_sys_clk(void);
  99 #endif
 100
 101 #define CONFIG_SYS_CLK_FREQ     66660000
 102
 103 /*
 104  * Config the L3 Cache as L3 SRAM
 105  */
 106 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 107 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 108 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 109 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 110 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 111 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 112 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 113
 114 #define CONFIG_SYS_DCSRBAR      0xf0000000
 115 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 116
 117 /* EEPROM */
 118 #define CONFIG_SYS_I2C_EEPROM_NXID
 119 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 120
 121 /*
 122  * DDR Setup
 123  */
 124 #define CONFIG_VERY_BIG_RAM
 125 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 127 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 128 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 129 #define CONFIG_SYS_SPD_BUS_NUM  0
 130 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 131 #define SPD_EEPROM_ADDRESS1     0x51
 132 #define SPD_EEPROM_ADDRESS2     0x52
 133 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 134 #define CTRL_INTLV_PREFERED     cacheline
 135
 136 /*
 137  * IFC Definitions
 138  */
 139 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 140 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 141 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 142 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 143                                 CSPR_PORT_SIZE_16 | \
 144                                 CSPR_MSEL_NOR | \
 145                                 CSPR_V)
 146 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 147
 148 /* NOR Flash Timing Params */
 149 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 150
 151 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 152                                 FTIM0_NOR_TEADC(0x5) | \
 153                                 FTIM0_NOR_TEAHC(0x5))
 154 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 155                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 156                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 157 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 158                                 FTIM2_NOR_TCH(0x4) | \
 159                                 FTIM2_NOR_TWPH(0x0E) | \
 160                                 FTIM2_NOR_TWP(0x1c))
 161 #define CONFIG_SYS_NOR_FTIM3    0x0
 162
 163 #define CONFIG_SYS_FLASH_QUIET_TEST
 164 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 165
 166 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 167 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 168 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 169 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_EMPTY_INFO
 171 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 172
 173 /* CPLD on IFC */
 174 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 175 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 176 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 177 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 178                                 | CSPR_PORT_SIZE_8 \
 179                                 | CSPR_MSEL_GPCM \
 180                                 | CSPR_V)
 181 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 182 #define CONFIG_SYS_CSOR2        0x0
 183
 184 /* CPLD Timing parameters for IFC CS2 */
 185 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 186                                         FTIM0_GPCM_TEADC(0x0e) | \
 187                                         FTIM0_GPCM_TEAHC(0x0e))
 188 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 189                                         FTIM1_GPCM_TRAD(0x1f))
 190 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 191                                         FTIM2_GPCM_TCH(0x8) | \
 192                                         FTIM2_GPCM_TWP(0x1f))
 193 #define CONFIG_SYS_CS2_FTIM3            0x0
 194
 195 /* NAND Flash on IFC */
 196 #define CONFIG_NAND_FSL_IFC
 197 #define CONFIG_SYS_NAND_BASE            0xff800000
 198 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 199
 200 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 201 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 202                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 203                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 204                                 | CSPR_V)
 205 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 206
 207 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 208                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 209                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 210                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 211                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 212                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 213                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 214
 215 #define CONFIG_SYS_NAND_ONFI_DETECTION
 216
 217 /* ONFI NAND Flash mode0 Timing Params */
 218 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 219                                         FTIM0_NAND_TWP(0x18)    | \
 220                                         FTIM0_NAND_TWCHT(0x07)  | \
 221                                         FTIM0_NAND_TWH(0x0a))
 222 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 223                                         FTIM1_NAND_TWBE(0x39)   | \
 224                                         FTIM1_NAND_TRR(0x0e)    | \
 225                                         FTIM1_NAND_TRP(0x18))
 226 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 227                                         FTIM2_NAND_TREH(0x0a)   | \
 228                                         FTIM2_NAND_TWHRE(0x1e))
 229 #define CONFIG_SYS_NAND_FTIM3           0x0
 230
 231 #define CONFIG_SYS_NAND_DDR_LAW         11
 232 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 233 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 234 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 235
 236 #if defined(CONFIG_MTD_RAW_NAND)
 237 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 238 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 239 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 240 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 241 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 242 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 243 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 244 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 245 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 246 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 247 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 248 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 249 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 250 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 251 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 252 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 253 #else
 254 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 255 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 256 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 263 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 264 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 265 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 266 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 267 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 268 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 269 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 270 #endif
 271
 272 #if defined(CONFIG_RAMBOOT_PBL)
 273 #define CONFIG_SYS_RAMBOOT
 274 #endif
 275
 276 #ifdef CONFIG_SPL_BUILD
 277 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 278 #else
 279 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 280 #endif
 281
 282 #define CONFIG_HWCONFIG
 283
 284 /* define to use L1 as initial stack */
 285 #define CONFIG_L1_INIT_RAM
 286 #define CONFIG_SYS_INIT_RAM_LOCK
 287 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 290 /* The assembler doesn't like typecast */
 291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 292                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 293                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 294 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 295 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 296                                                 GENERATED_GBL_DATA_SIZE)
 297 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 298 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 299 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 300
 301 /*
 302  * Serial Port
 303  */
 304 #define CONFIG_SYS_NS16550_SERIAL
 305 #define CONFIG_SYS_NS16550_REG_SIZE     1
 306 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 307 #define CONFIG_SYS_BAUDRATE_TABLE       \
 308         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 311 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 312 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 313
 314 /*
 315  * I2C
 316  */
 317
 318 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 319 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 320 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 321 #define I2C_MUX_CH_DEFAULT      0x8
 322
 323 #define I2C_MUX_CH_VOL_MONITOR  0xa
 324
 325 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 326 #ifndef CONFIG_SPL_BUILD
 327 #define CONFIG_VID
 328 #endif
 329 #define CONFIG_VOL_MONITOR_IR36021_SET
 330 #define CONFIG_VOL_MONITOR_IR36021_READ
 331 /* The lowest and highest voltage allowed for T208xRDB */
 332 #define VDD_MV_MIN                      819
 333 #define VDD_MV_MAX                      1212
 334
 335 /*
 336  * RapidIO
 337  */
 338 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 339 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 340 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 341 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 342 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 343 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 344 /*
 345  * for slave u-boot IMAGE instored in master memory space,
 346  * PHYS must be aligned based on the SIZE
 347  */
 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 352 /*
 353  * for slave UCODE and ENV instored in master memory space,
 354  * PHYS must be aligned based on the SIZE
 355  */
 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 359
 360 /* slave core release by master*/
 361 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 362 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 363
 364 /*
 365  * SRIO_PCIE_BOOT - SLAVE
 366  */
 367 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 370                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 371 #endif
 372
 373 /*
 374  * eSPI - Enhanced SPI
 375  */
 376
 377 /*
 378  * General PCI
 379  * Memory space is mapped 1-1, but I/O space must start from 0.
 380  */
 381 #define CONFIG_PCIE1            /* PCIE controller 1 */
 382 #define CONFIG_PCIE2            /* PCIE controller 2 */
 383 #define CONFIG_PCIE3            /* PCIE controller 3 */
 384 #define CONFIG_PCIE4            /* PCIE controller 4 */
 385 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 386 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 387 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 388 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 389 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 390 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 391
 392 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 393 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 394 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 395 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 396 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 397
 398 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 399 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 400 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 401 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 402 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 403
 404 /* controller 4, Base address 203000 */
 405 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 406 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 407 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 408
 409 #ifdef CONFIG_PCI
 410 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 411 #endif
 412
 413 /* Qman/Bman */
 414 #ifndef CONFIG_NOBQFMAN
 415 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 416 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 417 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 418 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 419 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 420 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 421 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 422 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 423 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 424                                         CONFIG_SYS_BMAN_CENA_SIZE)
 425 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 426 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 427 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 428 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 429 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 430 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 431 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 432 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 433 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 434 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 435 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 436                                         CONFIG_SYS_QMAN_CENA_SIZE)
 437 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 438 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 439
 440 #define CONFIG_SYS_DPAA_FMAN
 441 #define CONFIG_SYS_DPAA_PME
 442 #define CONFIG_SYS_PMAN
 443 #define CONFIG_SYS_DPAA_DCE
 444 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 445 #define CONFIG_SYS_INTERLAKEN
 446
 447 /* Default address of microcode for the Linux Fman driver */
 448 #if defined(CONFIG_SPIFLASH)
 449 /*
 450  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 451  * env, so we got 0x110000.
 452  */
 453 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 454
 455 #elif defined(CONFIG_SDCARD)
 456 /*
 457  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 458  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 459  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 460  */
 461 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 462
 463 #elif defined(CONFIG_MTD_RAW_NAND)
 464 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 465 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 466 /*
 467  * Slave has no ucode locally, it can fetch this from remote. When implementing
 468  * in two corenet boards, slave's ucode could be stored in master's memory
 469  * space, the address can be mapped from slave TLB->slave LAW->
 470  * slave SRIO or PCIE outbound window->master inbound window->
 471  * master LAW->the ucode address in master's memory space.
 472  */
 473 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 474 #else
 475 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 476 #endif
 477 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 478 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 479 #endif /* CONFIG_NOBQFMAN */
 480
 481 #ifdef CONFIG_SYS_DPAA_FMAN
 482 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 483 #define RGMII_PHY2_ADDR         0x02
 484 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 485 #define CORTINA_PHY_ADDR2       0x0d
 486 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 487 #define FM1_10GEC3_PHY_ADDR     0x00
 488 #define FM1_10GEC4_PHY_ADDR     0x01
 489 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 490 #define AQR113C_PHY_ADDR1       0x00
 491 #define AQR113C_PHY_ADDR2       0x08
 492 #endif
 493
 494 #ifdef CONFIG_FMAN_ENET
 495 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 496 #endif
 497
 498 /*
 499  * SATA
 500  */
 501 #ifdef CONFIG_FSL_SATA_V2
 502 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 503 #define CONFIG_SATA1
 504 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 505 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 506 #define CONFIG_SATA2
 507 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 508 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 509 #define CONFIG_LBA48
 510 #endif
 511
 512 /*
 513  * USB
 514  */
 515 #ifdef CONFIG_USB_EHCI_HCD
 516 #define CONFIG_USB_EHCI_FSL
 517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 518 #define CONFIG_HAS_FSL_DR_USB
 519 #endif
 520
 521 /*
 522  * SDHC
 523  */
 524 #ifdef CONFIG_MMC
 525 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 526 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 527 #endif
 528
 529 /*
 530  * Dynamic MTD Partition support with mtdparts
 531  */
 532
 533 /*
 534  * Environment
 535  */
 536
 537 /*
 538  * Miscellaneous configurable options
 539  */
 540 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 541
 542 /*
 543  * For booting Linux, the board info and command line data
 544  * have to be in the first 64 MB of memory, since this is
 545  * the maximum mapped by the Linux kernel during initialization.
 546  */
 547 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 548 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 549
 550 #ifdef CONFIG_CMD_KGDB
 551 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 552 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 553 #endif
 554
 555 /*
 556  * Environment Configuration
 557  */
 558 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 559 #define CONFIG_BOOTFILE  "uImage"
 560 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 561
 562 #define __USB_PHY_TYPE          utmi
 563
 564 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 565         "hwconfig=fsl_ddr:"                                     \
 566         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 567         "bank_intlv=auto;"                                      \
 568         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 569         "netdev=eth0\0"                                         \
 570         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 571         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 572         "tftpflash=tftpboot $loadaddr $uboot && "               \
 573         "protect off $ubootaddr +$filesize && "                 \
 574         "erase $ubootaddr +$filesize && "                       \
 575         "cp.b $loadaddr $ubootaddr $filesize && "               \
 576         "protect on $ubootaddr +$filesize && "                  \
 577         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 578         "consoledev=ttyS0\0"                                    \
 579         "ramdiskaddr=2000000\0"                                 \
 580         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 581         "fdtaddr=1e00000\0"                                     \
 582         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 583         "bdev=sda3\0"
 584
 585 /*
 586  * For emulation this causes u-boot to jump to the start of the
 587  * proof point app code automatically
 588  */
 589 #define PROOF_POINTS                            \
 590         "setenv bootargs root=/dev/$bdev rw "           \
 591         "console=$consoledev,$baudrate $othbootargs;"   \
 592         "cpu 1 release 0x29000000 - - -;"               \
 593         "cpu 2 release 0x29000000 - - -;"               \
 594         "cpu 3 release 0x29000000 - - -;"               \
 595         "cpu 4 release 0x29000000 - - -;"               \
 596         "cpu 5 release 0x29000000 - - -;"               \
 597         "cpu 6 release 0x29000000 - - -;"               \
 598         "cpu 7 release 0x29000000 - - -;"               \
 599         "go 0x29000000"
 600
 601 #define HVBOOT                          \
 602         "setenv bootargs config-addr=0x60000000; "      \
 603         "bootm 0x01000000 - 0x00f00000"
 604
 605 #define ALU                             \
 606         "setenv bootargs root=/dev/$bdev rw "           \
 607         "console=$consoledev,$baudrate $othbootargs;"   \
 608         "cpu 1 release 0x01000000 - - -;"               \
 609         "cpu 2 release 0x01000000 - - -;"               \
 610         "cpu 3 release 0x01000000 - - -;"               \
 611         "cpu 4 release 0x01000000 - - -;"               \
 612         "cpu 5 release 0x01000000 - - -;"               \
 613         "cpu 6 release 0x01000000 - - -;"               \
 614         "cpu 7 release 0x01000000 - - -;"               \
 615         "go 0x01000000"
 616
 617 #define LINUXBOOTCOMMAND                                \
 618         "setenv bootargs root=/dev/ram rw "             \
 619         "console=$consoledev,$baudrate $othbootargs;"   \
 620         "setenv ramdiskaddr 0x02000000;"                \
 621         "setenv fdtaddr 0x00c00000;"                    \
 622         "setenv loadaddr 0x1000000;"                    \
 623         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 624
 625 #define HDBOOT                                  \
 626         "setenv bootargs root=/dev/$bdev rw "           \
 627         "console=$consoledev,$baudrate $othbootargs;"   \
 628         "tftp $loadaddr $bootfile;"                     \
 629         "tftp $fdtaddr $fdtfile;"                       \
 630         "bootm $loadaddr - $fdtaddr"
 631
 632 #define NFSBOOTCOMMAND                  \
 633         "setenv bootargs root=/dev/nfs rw "     \
 634         "nfsroot=$serverip:$rootpath "          \
 635         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 636         "console=$consoledev,$baudrate $othbootargs;"   \
 637         "tftp $loadaddr $bootfile;"             \
 638         "tftp $fdtaddr $fdtfile;"               \
 639         "bootm $loadaddr - $fdtaddr"
 640
 641 #define RAMBOOTCOMMAND                          \
 642         "setenv bootargs root=/dev/ram rw "             \
 643         "console=$consoledev,$baudrate $othbootargs;"   \
 644         "tftp $ramdiskaddr $ramdiskfile;"               \
 645         "tftp $loadaddr $bootfile;"                     \
 646         "tftp $fdtaddr $fdtfile;"                       \
 647         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 648
 649 #define CONFIG_BOOTCOMMAND              LINUXBOOTCOMMAND
 650
 651 #include <asm/fsl_secure_boot.h>
 652
 653 #endif  /* __T2080RDB_H */