include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #define CONFIG_FSL_SATA_V2
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #ifdef CONFIG_RAMBOOT_PBL
  27 #define CONFIG_SPL_FLUSH_IMAGE
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SPL_SKIP_RELOCATE
  34 #define CONFIG_SPL_COMMON_INIT_DDR
  35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  36 #endif
  37
  38 #ifdef CONFIG_MTD_RAW_NAND
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  43 #endif
  44
  45 #ifdef CONFIG_SPIFLASH
  46 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  47 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  52 #ifndef CONFIG_SPL_BUILD
  53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54 #endif
  55 #endif
  56
  57 #ifdef CONFIG_SDCARD
  58 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  59 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  60 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  61 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  62 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  63 #ifndef CONFIG_SPL_BUILD
  64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65 #endif
  66 #endif
  67
  68 #endif /* CONFIG_RAMBOOT_PBL */
  69
  70 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  71 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  72 /* Set 1M boot space */
  73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  74 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  75                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  76 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  77 #endif
  78
  79 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  80 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  81 #endif
  82
  83 /*
  84  * These can be toggled for performance analysis, otherwise use default.
  85  */
  86 #define CONFIG_SYS_CACHE_STASHING
  87 #define CONFIG_BTB              /* toggle branch predition */
  88 #ifdef CONFIG_DDR_ECC
  89 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  90 #endif
  91
  92 #ifndef __ASSEMBLY__
  93 unsigned long get_board_sys_clk(void);
  94 #endif
  95
  96 #define CONFIG_SYS_CLK_FREQ     66660000
  97
  98 /*
  99  * Config the L3 Cache as L3 SRAM
 100  */
 101 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 102 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 103 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 104 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 105 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 106 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 107 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 108
 109 #define CONFIG_SYS_DCSRBAR      0xf0000000
 110 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 111
 112 /* EEPROM */
 113 #define CONFIG_SYS_I2C_EEPROM_NXID
 114 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 115
 116 /*
 117  * DDR Setup
 118  */
 119 #define CONFIG_VERY_BIG_RAM
 120 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 122 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 123 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 124 #define CONFIG_SYS_SPD_BUS_NUM  0
 125 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 126 #define SPD_EEPROM_ADDRESS1     0x51
 127 #define SPD_EEPROM_ADDRESS2     0x52
 128 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 129 #define CTRL_INTLV_PREFERED     cacheline
 130
 131 /*
 132  * IFC Definitions
 133  */
 134 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 135 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 136 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 137 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 138                                 CSPR_PORT_SIZE_16 | \
 139                                 CSPR_MSEL_NOR | \
 140                                 CSPR_V)
 141 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 142
 143 /* NOR Flash Timing Params */
 144 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 145
 146 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 147                                 FTIM0_NOR_TEADC(0x5) | \
 148                                 FTIM0_NOR_TEAHC(0x5))
 149 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 150                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 151                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 152 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 153                                 FTIM2_NOR_TCH(0x4) | \
 154                                 FTIM2_NOR_TWPH(0x0E) | \
 155                                 FTIM2_NOR_TWP(0x1c))
 156 #define CONFIG_SYS_NOR_FTIM3    0x0
 157
 158 #define CONFIG_SYS_FLASH_QUIET_TEST
 159 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 160
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 163 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 165 #define CONFIG_SYS_FLASH_EMPTY_INFO
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 167
 168 /* CPLD on IFC */
 169 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 170 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 171 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 172 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 173                                 | CSPR_PORT_SIZE_8 \
 174                                 | CSPR_MSEL_GPCM \
 175                                 | CSPR_V)
 176 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 177 #define CONFIG_SYS_CSOR2        0x0
 178
 179 /* CPLD Timing parameters for IFC CS2 */
 180 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 181                                         FTIM0_GPCM_TEADC(0x0e) | \
 182                                         FTIM0_GPCM_TEAHC(0x0e))
 183 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 184                                         FTIM1_GPCM_TRAD(0x1f))
 185 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 186                                         FTIM2_GPCM_TCH(0x8) | \
 187                                         FTIM2_GPCM_TWP(0x1f))
 188 #define CONFIG_SYS_CS2_FTIM3            0x0
 189
 190 /* NAND Flash on IFC */
 191 #define CONFIG_NAND_FSL_IFC
 192 #define CONFIG_SYS_NAND_BASE            0xff800000
 193 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 194
 195 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 196 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 197                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 198                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 199                                 | CSPR_V)
 200 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 201
 202 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 203                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 204                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 205                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 206                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 207                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 208                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 209
 210 /* ONFI NAND Flash mode0 Timing Params */
 211 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 212                                         FTIM0_NAND_TWP(0x18)    | \
 213                                         FTIM0_NAND_TWCHT(0x07)  | \
 214                                         FTIM0_NAND_TWH(0x0a))
 215 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 216                                         FTIM1_NAND_TWBE(0x39)   | \
 217                                         FTIM1_NAND_TRR(0x0e)    | \
 218                                         FTIM1_NAND_TRP(0x18))
 219 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 220                                         FTIM2_NAND_TREH(0x0a)   | \
 221                                         FTIM2_NAND_TWHRE(0x1e))
 222 #define CONFIG_SYS_NAND_FTIM3           0x0
 223
 224 #define CONFIG_SYS_NAND_DDR_LAW         11
 225 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 226 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 227
 228 #if defined(CONFIG_MTD_RAW_NAND)
 229 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 230 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 231 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 232 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 233 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 234 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 235 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 236 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 237 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 238 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 239 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 240 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 241 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 242 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 243 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 244 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 245 #else
 246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 262 #endif
 263
 264 #if defined(CONFIG_RAMBOOT_PBL)
 265 #define CONFIG_SYS_RAMBOOT
 266 #endif
 267
 268 #ifdef CONFIG_SPL_BUILD
 269 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 270 #else
 271 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 272 #endif
 273
 274 #define CONFIG_HWCONFIG
 275
 276 /* define to use L1 as initial stack */
 277 #define CONFIG_L1_INIT_RAM
 278 #define CONFIG_SYS_INIT_RAM_LOCK
 279 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 282 /* The assembler doesn't like typecast */
 283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 284                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 285                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 286 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 287 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 288                                                 GENERATED_GBL_DATA_SIZE)
 289 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 290 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 291
 292 /*
 293  * Serial Port
 294  */
 295 #define CONFIG_SYS_NS16550_SERIAL
 296 #define CONFIG_SYS_NS16550_REG_SIZE     1
 297 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 298 #define CONFIG_SYS_BAUDRATE_TABLE       \
 299         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 302 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 303 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 304
 305 /*
 306  * I2C
 307  */
 308
 309 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 310 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 311 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 312 #define I2C_MUX_CH_DEFAULT      0x8
 313
 314 #define I2C_MUX_CH_VOL_MONITOR  0xa
 315
 316 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 317 #ifndef CONFIG_SPL_BUILD
 318 #define CONFIG_VID
 319 #endif
 320 #define CONFIG_VOL_MONITOR_IR36021_SET
 321 #define CONFIG_VOL_MONITOR_IR36021_READ
 322 /* The lowest and highest voltage allowed for T208xRDB */
 323 #define VDD_MV_MIN                      819
 324 #define VDD_MV_MAX                      1212
 325
 326 /*
 327  * RapidIO
 328  */
 329 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 330 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 331 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 332 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 333 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 334 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 335 /*
 336  * for slave u-boot IMAGE instored in master memory space,
 337  * PHYS must be aligned based on the SIZE
 338  */
 339 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 343 /*
 344  * for slave UCODE and ENV instored in master memory space,
 345  * PHYS must be aligned based on the SIZE
 346  */
 347 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 350
 351 /* slave core release by master*/
 352 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 353 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 354
 355 /*
 356  * SRIO_PCIE_BOOT - SLAVE
 357  */
 358 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 359 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 360 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 361                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 362 #endif
 363
 364 /*
 365  * eSPI - Enhanced SPI
 366  */
 367
 368 /*
 369  * General PCI
 370  * Memory space is mapped 1-1, but I/O space must start from 0.
 371  */
 372 #define CONFIG_PCIE1            /* PCIE controller 1 */
 373 #define CONFIG_PCIE2            /* PCIE controller 2 */
 374 #define CONFIG_PCIE3            /* PCIE controller 3 */
 375 #define CONFIG_PCIE4            /* PCIE controller 4 */
 376 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 377 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 378 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 379 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 380 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 381 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 382
 383 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 384 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 385 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 386 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 387 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 388
 389 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 390 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 391 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 392 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 393 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 394
 395 /* controller 4, Base address 203000 */
 396 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 397 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 398 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 399
 400 #ifdef CONFIG_PCI
 401 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 402 #endif
 403
 404 /* Qman/Bman */
 405 #ifndef CONFIG_NOBQFMAN
 406 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 407 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 408 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 409 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 410 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 411 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 412 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 413 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 414 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 415                                         CONFIG_SYS_BMAN_CENA_SIZE)
 416 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 417 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 418 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 419 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 420 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 421 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 422 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 423 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 424 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 425 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 426 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 427                                         CONFIG_SYS_QMAN_CENA_SIZE)
 428 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 429 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 430
 431 #define CONFIG_SYS_DPAA_FMAN
 432 #define CONFIG_SYS_DPAA_PME
 433 #define CONFIG_SYS_PMAN
 434 #define CONFIG_SYS_DPAA_DCE
 435 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 436 #define CONFIG_SYS_INTERLAKEN
 437
 438 /* Default address of microcode for the Linux Fman driver */
 439 #if defined(CONFIG_SPIFLASH)
 440 /*
 441  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 442  * env, so we got 0x110000.
 443  */
 444 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 445
 446 #elif defined(CONFIG_SDCARD)
 447 /*
 448  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 449  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 450  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 451  */
 452 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 453
 454 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 455 /*
 456  * Slave has no ucode locally, it can fetch this from remote. When implementing
 457  * in two corenet boards, slave's ucode could be stored in master's memory
 458  * space, the address can be mapped from slave TLB->slave LAW->
 459  * slave SRIO or PCIE outbound window->master inbound window->
 460  * master LAW->the ucode address in master's memory space.
 461  */
 462 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 463 #else
 464 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 465 #endif
 466 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 467 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 468 #endif /* CONFIG_NOBQFMAN */
 469
 470 #ifdef CONFIG_SYS_DPAA_FMAN
 471 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 472 #define RGMII_PHY2_ADDR         0x02
 473 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 474 #define CORTINA_PHY_ADDR2       0x0d
 475 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 476 #define FM1_10GEC3_PHY_ADDR     0x00
 477 #define FM1_10GEC4_PHY_ADDR     0x01
 478 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 479 #define AQR113C_PHY_ADDR1       0x00
 480 #define AQR113C_PHY_ADDR2       0x08
 481 #endif
 482
 483 #ifdef CONFIG_FMAN_ENET
 484 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 485 #endif
 486
 487 /*
 488  * SATA
 489  */
 490 #ifdef CONFIG_FSL_SATA_V2
 491 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 492 #define CONFIG_SATA1
 493 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 494 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 495 #define CONFIG_SATA2
 496 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 497 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 498 #define CONFIG_LBA48
 499 #endif
 500
 501 /*
 502  * USB
 503  */
 504 #ifdef CONFIG_USB_EHCI_HCD
 505 #define CONFIG_USB_EHCI_FSL
 506 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 507 #define CONFIG_HAS_FSL_DR_USB
 508 #endif
 509
 510 /*
 511  * SDHC
 512  */
 513 #ifdef CONFIG_MMC
 514 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 515 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 516 #endif
 517
 518 /*
 519  * Dynamic MTD Partition support with mtdparts
 520  */
 521
 522 /*
 523  * Environment
 524  */
 525
 526 /*
 527  * Miscellaneous configurable options
 528  */
 529
 530 /*
 531  * For booting Linux, the board info and command line data
 532  * have to be in the first 64 MB of memory, since this is
 533  * the maximum mapped by the Linux kernel during initialization.
 534  */
 535 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 536 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 537
 538 /*
 539  * Environment Configuration
 540  */
 541 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 542 #define CONFIG_BOOTFILE  "uImage"
 543 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 544
 545 #define __USB_PHY_TYPE          utmi
 546
 547 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 548         "hwconfig=fsl_ddr:"                                     \
 549         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 550         "bank_intlv=auto;"                                      \
 551         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 552         "netdev=eth0\0"                                         \
 553         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 554         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 555         "tftpflash=tftpboot $loadaddr $uboot && "               \
 556         "protect off $ubootaddr +$filesize && "                 \
 557         "erase $ubootaddr +$filesize && "                       \
 558         "cp.b $loadaddr $ubootaddr $filesize && "               \
 559         "protect on $ubootaddr +$filesize && "                  \
 560         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 561         "consoledev=ttyS0\0"                                    \
 562         "ramdiskaddr=2000000\0"                                 \
 563         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 564         "fdtaddr=1e00000\0"                                     \
 565         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 566         "bdev=sda3\0"
 567
 568 /*
 569  * For emulation this causes u-boot to jump to the start of the
 570  * proof point app code automatically
 571  */
 572 #define PROOF_POINTS                            \
 573         "setenv bootargs root=/dev/$bdev rw "           \
 574         "console=$consoledev,$baudrate $othbootargs;"   \
 575         "cpu 1 release 0x29000000 - - -;"               \
 576         "cpu 2 release 0x29000000 - - -;"               \
 577         "cpu 3 release 0x29000000 - - -;"               \
 578         "cpu 4 release 0x29000000 - - -;"               \
 579         "cpu 5 release 0x29000000 - - -;"               \
 580         "cpu 6 release 0x29000000 - - -;"               \
 581         "cpu 7 release 0x29000000 - - -;"               \
 582         "go 0x29000000"
 583
 584 #define HVBOOT                          \
 585         "setenv bootargs config-addr=0x60000000; "      \
 586         "bootm 0x01000000 - 0x00f00000"
 587
 588 #define ALU                             \
 589         "setenv bootargs root=/dev/$bdev rw "           \
 590         "console=$consoledev,$baudrate $othbootargs;"   \
 591         "cpu 1 release 0x01000000 - - -;"               \
 592         "cpu 2 release 0x01000000 - - -;"               \
 593         "cpu 3 release 0x01000000 - - -;"               \
 594         "cpu 4 release 0x01000000 - - -;"               \
 595         "cpu 5 release 0x01000000 - - -;"               \
 596         "cpu 6 release 0x01000000 - - -;"               \
 597         "cpu 7 release 0x01000000 - - -;"               \
 598         "go 0x01000000"
 599
 600 #define LINUXBOOTCOMMAND                                \
 601         "setenv bootargs root=/dev/ram rw "             \
 602         "console=$consoledev,$baudrate $othbootargs;"   \
 603         "setenv ramdiskaddr 0x02000000;"                \
 604         "setenv fdtaddr 0x00c00000;"                    \
 605         "setenv loadaddr 0x1000000;"                    \
 606         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 607
 608 #define HDBOOT                                  \
 609         "setenv bootargs root=/dev/$bdev rw "           \
 610         "console=$consoledev,$baudrate $othbootargs;"   \
 611         "tftp $loadaddr $bootfile;"                     \
 612         "tftp $fdtaddr $fdtfile;"                       \
 613         "bootm $loadaddr - $fdtaddr"
 614
 615 #define NFSBOOTCOMMAND                  \
 616         "setenv bootargs root=/dev/nfs rw "     \
 617         "nfsroot=$serverip:$rootpath "          \
 618         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 619         "console=$consoledev,$baudrate $othbootargs;"   \
 620         "tftp $loadaddr $bootfile;"             \
 621         "tftp $fdtaddr $fdtfile;"               \
 622         "bootm $loadaddr - $fdtaddr"
 623
 624 #define RAMBOOTCOMMAND                          \
 625         "setenv bootargs root=/dev/ram rw "             \
 626         "console=$consoledev,$baudrate $othbootargs;"   \
 627         "tftp $ramdiskaddr $ramdiskfile;"               \
 628         "tftp $loadaddr $bootfile;"                     \
 629         "tftp $fdtaddr $fdtfile;"                       \
 630         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 631
 632 #define CONFIG_BOOTCOMMAND              LINUXBOOTCOMMAND
 633
 634 #include <asm/fsl_secure_boot.h>
 635
 636 #endif  /* __T2080RDB_H */