2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080 RDB/PCIe board configuration file
14 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_T2080RDB
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
21 /* High Level Configuration Options */
23 #define CONFIG_E500 /* BOOKE e500 family */
24 #define CONFIG_E500MC /* BOOKE e500mc family */
25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
26 #define CONFIG_MP /* support multiple processors */
27 #define CONFIG_ENABLE_36BIT_PHYS
29 #ifdef CONFIG_PHYS_64BIT
30 #define CONFIG_ADDR_MAP 1
31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
36 #define CONFIG_FSL_IFC /* Enable IFC Support */
37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
38 #define CONFIG_FSL_LAW /* Use common FSL init code */
39 #define CONFIG_ENV_OVERWRITE
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
46 #define CONFIG_SPL_SERIAL_SUPPORT
47 #define CONFIG_SPL_FLUSH_IMAGE
48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
49 #define CONFIG_SPL_LIBGENERIC_SUPPORT
50 #define CONFIG_SPL_LIBCOMMON_SUPPORT
51 #define CONFIG_FSL_LAW /* Use common FSL init code */
52 #define CONFIG_SYS_TEXT_BASE 0x00201000
53 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
54 #define CONFIG_SPL_PAD_TO 0x40000
55 #define CONFIG_SPL_MAX_SIZE 0x28000
56 #define RESET_VECTOR_OFFSET 0x27FFC
57 #define BOOT_PAGE_OFFSET 0x27000
58 #ifdef CONFIG_SPL_BUILD
59 #define CONFIG_SPL_SKIP_RELOCATE
60 #define CONFIG_SPL_COMMON_INIT_DDR
61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
62 #define CONFIG_SYS_NO_FLASH
66 #define CONFIG_SPL_NAND_SUPPORT
67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
68 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
69 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
70 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
72 #define CONFIG_SPL_NAND_BOOT
75 #ifdef CONFIG_SPIFLASH
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
77 #define CONFIG_SPL_SPI_SUPPORT
78 #define CONFIG_SPL_SPI_FLASH_SUPPORT
79 #define CONFIG_SPL_SPI_FLASH_MINIMAL
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
85 #ifndef CONFIG_SPL_BUILD
86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
88 #define CONFIG_SPL_SPI_BOOT
92 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
93 #define CONFIG_SPL_MMC_SUPPORT
94 #define CONFIG_SPL_MMC_MINIMAL
95 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
96 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
97 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
98 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
99 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
100 #ifndef CONFIG_SPL_BUILD
101 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
103 #define CONFIG_SPL_MMC_BOOT
106 #endif /* CONFIG_RAMBOOT_PBL */
108 #define CONFIG_SRIO_PCIE_BOOT_MASTER
109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
110 /* Set 1M boot space */
111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
113 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
115 #define CONFIG_SYS_NO_FLASH
118 #ifndef CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_TEXT_BASE 0xeff40000
122 #ifndef CONFIG_RESET_VECTOR_ADDRESS
123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
127 * These can be toggled for performance analysis, otherwise use default.
129 #define CONFIG_SYS_CACHE_STASHING
130 #define CONFIG_BTB /* toggle branch predition */
131 #define CONFIG_DDR_ECC
132 #ifdef CONFIG_DDR_ECC
133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
138 #define CONFIG_SYS_MEMTEST_END 0x00400000
139 #define CONFIG_SYS_ALT_MEMTEST
141 #ifndef CONFIG_SYS_NO_FLASH
142 #define CONFIG_FLASH_CFI_DRIVER
143 #define CONFIG_SYS_FLASH_CFI
144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
147 #if defined(CONFIG_SPIFLASH)
148 #define CONFIG_SYS_EXTRA_ENV_RELOC
149 #define CONFIG_ENV_IS_IN_SPI_FLASH
150 #define CONFIG_ENV_SPI_BUS 0
151 #define CONFIG_ENV_SPI_CS 0
152 #define CONFIG_ENV_SPI_MAX_HZ 10000000
153 #define CONFIG_ENV_SPI_MODE 0
154 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
155 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
156 #define CONFIG_ENV_SECT_SIZE 0x10000
157 #elif defined(CONFIG_SDCARD)
158 #define CONFIG_SYS_EXTRA_ENV_RELOC
159 #define CONFIG_ENV_IS_IN_MMC
160 #define CONFIG_SYS_MMC_ENV_DEV 0
161 #define CONFIG_ENV_SIZE 0x2000
162 #define CONFIG_ENV_OFFSET (512 * 0x800)
163 #elif defined(CONFIG_NAND)
164 #define CONFIG_SYS_EXTRA_ENV_RELOC
165 #define CONFIG_ENV_IS_IN_NAND
166 #define CONFIG_ENV_SIZE 0x2000
167 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
168 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
169 #define CONFIG_ENV_IS_IN_REMOTE
170 #define CONFIG_ENV_ADDR 0xffe20000
171 #define CONFIG_ENV_SIZE 0x2000
172 #elif defined(CONFIG_ENV_IS_NOWHERE)
173 #define CONFIG_ENV_SIZE 0x2000
175 #define CONFIG_ENV_IS_IN_FLASH
176 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
177 #define CONFIG_ENV_SIZE 0x2000
178 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
182 unsigned long get_board_sys_clk(void);
183 unsigned long get_board_ddr_clk(void);
186 #define CONFIG_SYS_CLK_FREQ 66660000
187 #define CONFIG_DDR_CLK_FREQ 133330000
190 * Config the L3 Cache as L3 SRAM
192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
193 #define CONFIG_SYS_L3_SIZE (512 << 10)
194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
195 #ifdef CONFIG_RAMBOOT_PBL
196 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
201 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
203 #define CONFIG_SYS_DCSRBAR 0xf0000000
204 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
207 #define CONFIG_ID_EEPROM
208 #define CONFIG_SYS_I2C_EEPROM_NXID
209 #define CONFIG_SYS_EEPROM_BUS_NUM 0
210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
216 #define CONFIG_VERY_BIG_RAM
217 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
218 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
219 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
220 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
221 #define CONFIG_DDR_SPD
222 #define CONFIG_SYS_FSL_DDR3
223 #undef CONFIG_FSL_DDR_INTERACTIVE
224 #define CONFIG_SYS_SPD_BUS_NUM 0
225 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
226 #define SPD_EEPROM_ADDRESS1 0x51
227 #define SPD_EEPROM_ADDRESS2 0x52
228 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
229 #define CTRL_INTLV_PREFERED cacheline
234 #define CONFIG_SYS_FLASH_BASE 0xe8000000
235 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
236 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
237 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
238 CSPR_PORT_SIZE_16 | \
241 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
243 /* NOR Flash Timing Params */
244 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
247 FTIM0_NOR_TEADC(0x5) | \
248 FTIM0_NOR_TEAHC(0x5))
249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
250 FTIM1_NOR_TRAD_NOR(0x1A) |\
251 FTIM1_NOR_TSEQRAD_NOR(0x13))
252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
253 FTIM2_NOR_TCH(0x4) | \
254 FTIM2_NOR_TWPH(0x0E) | \
256 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_FLASH_QUIET_TEST
259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
265 #define CONFIG_SYS_FLASH_EMPTY_INFO
266 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
269 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
270 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
271 #define CONFIG_SYS_CSPR2_EXT (0xf)
272 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
276 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
277 #define CONFIG_SYS_CSOR2 0x0
279 /* CPLD Timing parameters for IFC CS2 */
280 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
281 FTIM0_GPCM_TEADC(0x0e) | \
282 FTIM0_GPCM_TEAHC(0x0e))
283 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
284 FTIM1_GPCM_TRAD(0x1f))
285 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
286 FTIM2_GPCM_TCH(0x8) | \
287 FTIM2_GPCM_TWP(0x1f))
288 #define CONFIG_SYS_CS2_FTIM3 0x0
290 /* NAND Flash on IFC */
291 #define CONFIG_NAND_FSL_IFC
292 #define CONFIG_SYS_NAND_BASE 0xff800000
293 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
295 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
296 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
297 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
298 | CSPR_MSEL_NAND /* MSEL = NAND */ \
300 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
302 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
303 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
304 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
305 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
306 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
307 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
308 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
310 #define CONFIG_SYS_NAND_ONFI_DETECTION
312 /* ONFI NAND Flash mode0 Timing Params */
313 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
314 FTIM0_NAND_TWP(0x18) | \
315 FTIM0_NAND_TWCHT(0x07) | \
316 FTIM0_NAND_TWH(0x0a))
317 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
318 FTIM1_NAND_TWBE(0x39) | \
319 FTIM1_NAND_TRR(0x0e) | \
320 FTIM1_NAND_TRP(0x18))
321 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
322 FTIM2_NAND_TREH(0x0a) | \
323 FTIM2_NAND_TWHRE(0x1e))
324 #define CONFIG_SYS_NAND_FTIM3 0x0
326 #define CONFIG_SYS_NAND_DDR_LAW 11
327 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
328 #define CONFIG_SYS_MAX_NAND_DEVICE 1
329 #define CONFIG_CMD_NAND
330 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
332 #if defined(CONFIG_NAND)
333 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
341 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
342 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
343 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
344 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
345 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
346 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
347 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
348 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
350 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
351 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
352 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
353 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
354 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
355 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
356 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
357 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
358 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
359 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
360 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
361 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
362 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
363 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
364 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
365 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
368 #if defined(CONFIG_RAMBOOT_PBL)
369 #define CONFIG_SYS_RAMBOOT
372 #ifdef CONFIG_SPL_BUILD
373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
378 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
379 #define CONFIG_MISC_INIT_R
380 #define CONFIG_HWCONFIG
382 /* define to use L1 as initial stack */
383 #define CONFIG_L1_INIT_RAM
384 #define CONFIG_SYS_INIT_RAM_LOCK
385 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
388 /* The assembler doesn't like typecast */
389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
390 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
391 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
392 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
393 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
394 GENERATED_GBL_DATA_SIZE)
395 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
396 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
397 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
402 #define CONFIG_CONS_INDEX 1
403 #define CONFIG_SYS_NS16550_SERIAL
404 #define CONFIG_SYS_NS16550_REG_SIZE 1
405 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
406 #define CONFIG_SYS_BAUDRATE_TABLE \
407 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
408 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
409 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
410 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
411 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
416 #define CONFIG_SYS_I2C
417 #define CONFIG_SYS_I2C_FSL
418 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
419 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
420 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
421 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
422 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
423 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
424 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
425 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
426 #define CONFIG_SYS_FSL_I2C_SPEED 100000
427 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
428 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
429 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
430 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
431 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
432 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
433 #define I2C_MUX_CH_DEFAULT 0x8
435 #define I2C_MUX_CH_VOL_MONITOR 0xa
437 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
438 #ifndef CONFIG_SPL_BUILD
441 #define CONFIG_VOL_MONITOR_IR36021_SET
442 #define CONFIG_VOL_MONITOR_IR36021_READ
443 /* The lowest and highest voltage allowed for T208xRDB */
444 #define VDD_MV_MIN 819
445 #define VDD_MV_MAX 1212
450 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
451 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
452 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
453 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
454 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
455 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
457 * for slave u-boot IMAGE instored in master memory space,
458 * PHYS must be aligned based on the SIZE
460 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
461 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
462 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
463 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
465 * for slave UCODE and ENV instored in master memory space,
466 * PHYS must be aligned based on the SIZE
468 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
469 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
470 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
472 /* slave core release by master*/
473 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
474 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
477 * SRIO_PCIE_BOOT - SLAVE
479 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
480 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
481 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
482 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
486 * eSPI - Enhanced SPI
488 #ifdef CONFIG_SPI_FLASH
489 #define CONFIG_SPI_FLASH_BAR
490 #define CONFIG_SF_DEFAULT_SPEED 10000000
491 #define CONFIG_SF_DEFAULT_MODE 0
496 * Memory space is mapped 1-1, but I/O space must start from 0.
498 #define CONFIG_PCI /* Enable PCI/PCIE */
499 #define CONFIG_PCIE1 /* PCIE controller 1 */
500 #define CONFIG_PCIE2 /* PCIE controller 2 */
501 #define CONFIG_PCIE3 /* PCIE controller 3 */
502 #define CONFIG_PCIE4 /* PCIE controller 4 */
503 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
504 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
505 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
506 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
507 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
508 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
509 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
510 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
511 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
512 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
513 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
515 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
516 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
517 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
519 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
520 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
521 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
523 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
525 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
526 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
527 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
528 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
529 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
530 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
531 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
532 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
533 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
535 /* controller 4, Base address 203000 */
536 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
537 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
538 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
539 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
540 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
541 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
542 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
545 #define CONFIG_PCI_INDIRECT_BRIDGE
546 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
547 #define CONFIG_PCI_PNP /* do pci plug-and-play */
548 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
549 #define CONFIG_DOS_PARTITION
553 #ifndef CONFIG_NOBQFMAN
554 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
555 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
556 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
557 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
558 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
559 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
560 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
561 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
562 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
563 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
564 CONFIG_SYS_BMAN_CENA_SIZE)
565 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
566 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
567 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
568 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
569 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
570 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
571 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
572 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
573 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
574 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
575 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
576 CONFIG_SYS_QMAN_CENA_SIZE)
577 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
578 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
580 #define CONFIG_SYS_DPAA_FMAN
581 #define CONFIG_SYS_DPAA_PME
582 #define CONFIG_SYS_PMAN
583 #define CONFIG_SYS_DPAA_DCE
584 #define CONFIG_SYS_DPAA_RMAN /* RMan */
585 #define CONFIG_SYS_INTERLAKEN
587 /* Default address of microcode for the Linux Fman driver */
588 #if defined(CONFIG_SPIFLASH)
590 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
591 * env, so we got 0x110000.
593 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
594 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
595 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
596 #define CONFIG_CORTINA_FW_ADDR 0x120000
598 #elif defined(CONFIG_SDCARD)
600 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
601 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
602 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
604 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
605 #define CONFIG_SYS_CORTINA_FW_IN_MMC
606 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
607 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
609 #elif defined(CONFIG_NAND)
610 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
611 #define CONFIG_SYS_CORTINA_FW_IN_NAND
612 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
613 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
614 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
616 * Slave has no ucode locally, it can fetch this from remote. When implementing
617 * in two corenet boards, slave's ucode could be stored in master's memory
618 * space, the address can be mapped from slave TLB->slave LAW->
619 * slave SRIO or PCIE outbound window->master inbound window->
620 * master LAW->the ucode address in master's memory space.
622 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
623 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
624 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
625 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
627 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
628 #define CONFIG_SYS_CORTINA_FW_IN_NOR
629 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
630 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
632 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
633 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
634 #endif /* CONFIG_NOBQFMAN */
636 #ifdef CONFIG_SYS_DPAA_FMAN
637 #define CONFIG_FMAN_ENET
638 #define CONFIG_PHYLIB_10G
639 #define CONFIG_PHY_AQUANTIA
640 #define CONFIG_PHY_CORTINA
641 #define CONFIG_PHY_REALTEK
642 #define CONFIG_CORTINA_FW_LENGTH 0x40000
643 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
644 #define RGMII_PHY2_ADDR 0x02
645 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
646 #define CORTINA_PHY_ADDR2 0x0d
647 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
648 #define FM1_10GEC4_PHY_ADDR 0x01
651 #ifdef CONFIG_FMAN_ENET
652 #define CONFIG_MII /* MII PHY management */
653 #define CONFIG_ETHPRIME "FM1@DTSEC3"
654 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
660 #ifdef CONFIG_FSL_SATA_V2
661 #define CONFIG_LIBATA
662 #define CONFIG_FSL_SATA
663 #define CONFIG_SYS_SATA_MAX_DEVICE 2
665 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
666 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
668 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
669 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
671 #define CONFIG_CMD_SATA
672 #define CONFIG_DOS_PARTITION
678 #ifdef CONFIG_USB_EHCI
679 #define CONFIG_USB_EHCI_FSL
680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
681 #define CONFIG_HAS_FSL_DR_USB
688 #define CONFIG_FSL_ESDHC
689 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
690 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
691 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
692 #define CONFIG_GENERIC_MMC
693 #define CONFIG_DOS_PARTITION
697 * Dynamic MTD Partition support with mtdparts
699 #ifndef CONFIG_SYS_NO_FLASH
700 #define CONFIG_MTD_DEVICE
701 #define CONFIG_MTD_PARTITIONS
702 #define CONFIG_CMD_MTDPARTS
703 #define CONFIG_FLASH_CFI_MTD
704 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
706 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
707 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
708 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
709 "1m(uboot),5m(kernel),128k(dtb),-(user)"
717 * Command line configuration.
719 #define CONFIG_CMD_ERRATA
720 #define CONFIG_CMD_REGINFO
723 #define CONFIG_CMD_PCI
726 /* Hash command with SHA acceleration supported in hardware */
727 #ifdef CONFIG_FSL_CAAM
728 #define CONFIG_CMD_HASH
729 #define CONFIG_SHA_HW_ACCEL
733 * Miscellaneous configurable options
735 #define CONFIG_SYS_LONGHELP /* undef to save memory */
736 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
737 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
738 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
739 #ifdef CONFIG_CMD_KGDB
740 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
742 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
744 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
745 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
746 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
749 * For booting Linux, the board info and command line data
750 * have to be in the first 64 MB of memory, since this is
751 * the maximum mapped by the Linux kernel during initialization.
753 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
754 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
756 #ifdef CONFIG_CMD_KGDB
757 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
758 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
762 * Environment Configuration
764 #define CONFIG_ROOTPATH "/opt/nfsroot"
765 #define CONFIG_BOOTFILE "uImage"
766 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
768 /* default location for tftp and bootm */
769 #define CONFIG_LOADADDR 1000000
770 #define CONFIG_BAUDRATE 115200
771 #define __USB_PHY_TYPE utmi
773 #define CONFIG_EXTRA_ENV_SETTINGS \
774 "hwconfig=fsl_ddr:" \
775 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
777 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
779 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
780 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
781 "tftpflash=tftpboot $loadaddr $uboot && " \
782 "protect off $ubootaddr +$filesize && " \
783 "erase $ubootaddr +$filesize && " \
784 "cp.b $loadaddr $ubootaddr $filesize && " \
785 "protect on $ubootaddr +$filesize && " \
786 "cmp.b $loadaddr $ubootaddr $filesize\0" \
787 "consoledev=ttyS0\0" \
788 "ramdiskaddr=2000000\0" \
789 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
790 "fdtaddr=1e00000\0" \
791 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
795 * For emulation this causes u-boot to jump to the start of the
796 * proof point app code automatically
798 #define CONFIG_PROOF_POINTS \
799 "setenv bootargs root=/dev/$bdev rw " \
800 "console=$consoledev,$baudrate $othbootargs;" \
801 "cpu 1 release 0x29000000 - - -;" \
802 "cpu 2 release 0x29000000 - - -;" \
803 "cpu 3 release 0x29000000 - - -;" \
804 "cpu 4 release 0x29000000 - - -;" \
805 "cpu 5 release 0x29000000 - - -;" \
806 "cpu 6 release 0x29000000 - - -;" \
807 "cpu 7 release 0x29000000 - - -;" \
810 #define CONFIG_HVBOOT \
811 "setenv bootargs config-addr=0x60000000; " \
812 "bootm 0x01000000 - 0x00f00000"
815 "setenv bootargs root=/dev/$bdev rw " \
816 "console=$consoledev,$baudrate $othbootargs;" \
817 "cpu 1 release 0x01000000 - - -;" \
818 "cpu 2 release 0x01000000 - - -;" \
819 "cpu 3 release 0x01000000 - - -;" \
820 "cpu 4 release 0x01000000 - - -;" \
821 "cpu 5 release 0x01000000 - - -;" \
822 "cpu 6 release 0x01000000 - - -;" \
823 "cpu 7 release 0x01000000 - - -;" \
826 #define CONFIG_LINUX \
827 "setenv bootargs root=/dev/ram rw " \
828 "console=$consoledev,$baudrate $othbootargs;" \
829 "setenv ramdiskaddr 0x02000000;" \
830 "setenv fdtaddr 0x00c00000;" \
831 "setenv loadaddr 0x1000000;" \
832 "bootm $loadaddr $ramdiskaddr $fdtaddr"
834 #define CONFIG_HDBOOT \
835 "setenv bootargs root=/dev/$bdev rw " \
836 "console=$consoledev,$baudrate $othbootargs;" \
837 "tftp $loadaddr $bootfile;" \
838 "tftp $fdtaddr $fdtfile;" \
839 "bootm $loadaddr - $fdtaddr"
841 #define CONFIG_NFSBOOTCOMMAND \
842 "setenv bootargs root=/dev/nfs rw " \
843 "nfsroot=$serverip:$rootpath " \
844 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
845 "console=$consoledev,$baudrate $othbootargs;" \
846 "tftp $loadaddr $bootfile;" \
847 "tftp $fdtaddr $fdtfile;" \
848 "bootm $loadaddr - $fdtaddr"
850 #define CONFIG_RAMBOOTCOMMAND \
851 "setenv bootargs root=/dev/ram rw " \
852 "console=$consoledev,$baudrate $othbootargs;" \
853 "tftp $ramdiskaddr $ramdiskfile;" \
854 "tftp $loadaddr $bootfile;" \
855 "tftp $fdtaddr $fdtfile;" \
856 "bootm $loadaddr $ramdiskaddr $fdtaddr"
858 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
860 #include <asm/fsl_secure_boot.h>
862 #endif /* __T2080RDB_H */