include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_FSL_SATA_V2
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  19 #define CONFIG_MP               /* support multiple processors */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #ifdef CONFIG_PHYS_64BIT
  23 #define CONFIG_ADDR_MAP 1
  24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  25 #endif
  26
  27 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  29 #define CONFIG_ENV_OVERWRITE
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  36 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  37 #define CONFIG_SPL_PAD_TO               0x40000
  38 #define CONFIG_SPL_MAX_SIZE             0x28000
  39 #define RESET_VECTOR_OFFSET             0x27FFC
  40 #define BOOT_PAGE_OFFSET                0x27000
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_SKIP_RELOCATE
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  45 #endif
  46
  47 #ifdef CONFIG_NAND
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  51 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  52 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  54 #define CONFIG_SPL_NAND_BOOT
  55 #endif
  56
  57 #ifdef CONFIG_SPIFLASH
  58 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  64 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  69 #define CONFIG_SPL_SPI_BOOT
  70 #endif
  71
  72 #ifdef CONFIG_SDCARD
  73 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  74 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  75 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  76 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  77 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  78 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  79 #ifndef CONFIG_SPL_BUILD
  80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  81 #endif
  82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  83 #define CONFIG_SPL_MMC_BOOT
  84 #endif
  85
  86 #endif /* CONFIG_RAMBOOT_PBL */
  87
  88 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  89 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  90 /* Set 1M boot space */
  91 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  93                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  94 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  95 #endif
  96
  97 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  98 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  99 #endif
 100
 101 /*
 102  * These can be toggled for performance analysis, otherwise use default.
 103  */
 104 #define CONFIG_SYS_CACHE_STASHING
 105 #define CONFIG_BTB              /* toggle branch predition */
 106 #define CONFIG_DDR_ECC
 107 #ifdef CONFIG_DDR_ECC
 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 109 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 110 #endif
 111
 112 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 113 #define CONFIG_SYS_MEMTEST_END          0x00400000
 114
 115 #ifdef CONFIG_MTD_NOR_FLASH
 116 #define CONFIG_FLASH_CFI_DRIVER
 117 #define CONFIG_SYS_FLASH_CFI
 118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 119 #endif
 120
 121 #if defined(CONFIG_SPIFLASH)
 122 #define CONFIG_SYS_EXTRA_ENV_RELOC
 123 #define CONFIG_ENV_SPI_BUS      0
 124 #define CONFIG_ENV_SPI_CS       0
 125 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 126 #define CONFIG_ENV_SPI_MODE     0
 127 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 128 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 129 #define CONFIG_ENV_SECT_SIZE    0x10000
 130 #elif defined(CONFIG_SDCARD)
 131 #define CONFIG_SYS_EXTRA_ENV_RELOC
 132 #define CONFIG_SYS_MMC_ENV_DEV  0
 133 #define CONFIG_ENV_SIZE         0x2000
 134 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 135 #elif defined(CONFIG_NAND)
 136 #define CONFIG_SYS_EXTRA_ENV_RELOC
 137 #define CONFIG_ENV_SIZE         0x2000
 138 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 139 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 140 #define CONFIG_ENV_ADDR         0xffe20000
 141 #define CONFIG_ENV_SIZE         0x2000
 142 #elif defined(CONFIG_ENV_IS_NOWHERE)
 143 #define CONFIG_ENV_SIZE         0x2000
 144 #else
 145 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 146 #define CONFIG_ENV_SIZE         0x2000
 147 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 148 #endif
 149
 150 #ifndef __ASSEMBLY__
 151 unsigned long get_board_sys_clk(void);
 152 unsigned long get_board_ddr_clk(void);
 153 #endif
 154
 155 #define CONFIG_SYS_CLK_FREQ     66660000
 156 #define CONFIG_DDR_CLK_FREQ     133330000
 157
 158 /*
 159  * Config the L3 Cache as L3 SRAM
 160  */
 161 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 162 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 163 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 164 #ifdef CONFIG_RAMBOOT_PBL
 165 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 166 #endif
 167 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 168 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 169 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 170 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 171
 172 #define CONFIG_SYS_DCSRBAR      0xf0000000
 173 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 174
 175 /* EEPROM */
 176 #define CONFIG_ID_EEPROM
 177 #define CONFIG_SYS_I2C_EEPROM_NXID
 178 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 179 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 181
 182 /*
 183  * DDR Setup
 184  */
 185 #define CONFIG_VERY_BIG_RAM
 186 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 187 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 188 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 189 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 190 #define CONFIG_DDR_SPD
 191 #undef CONFIG_FSL_DDR_INTERACTIVE
 192 #define CONFIG_SYS_SPD_BUS_NUM  0
 193 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 194 #define SPD_EEPROM_ADDRESS1     0x51
 195 #define SPD_EEPROM_ADDRESS2     0x52
 196 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 197 #define CTRL_INTLV_PREFERED     cacheline
 198
 199 /*
 200  * IFC Definitions
 201  */
 202 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 203 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 204 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 205 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 206                                 CSPR_PORT_SIZE_16 | \
 207                                 CSPR_MSEL_NOR | \
 208                                 CSPR_V)
 209 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 210
 211 /* NOR Flash Timing Params */
 212 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 213
 214 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 215                                 FTIM0_NOR_TEADC(0x5) | \
 216                                 FTIM0_NOR_TEAHC(0x5))
 217 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 218                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 219                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 220 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 221                                 FTIM2_NOR_TCH(0x4) | \
 222                                 FTIM2_NOR_TWPH(0x0E) | \
 223                                 FTIM2_NOR_TWP(0x1c))
 224 #define CONFIG_SYS_NOR_FTIM3    0x0
 225
 226 #define CONFIG_SYS_FLASH_QUIET_TEST
 227 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 228
 229 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 230 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_EMPTY_INFO
 234 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 235
 236 /* CPLD on IFC */
 237 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 238 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 239 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 240 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 241                                 | CSPR_PORT_SIZE_8 \
 242                                 | CSPR_MSEL_GPCM \
 243                                 | CSPR_V)
 244 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 245 #define CONFIG_SYS_CSOR2        0x0
 246
 247 /* CPLD Timing parameters for IFC CS2 */
 248 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 249                                         FTIM0_GPCM_TEADC(0x0e) | \
 250                                         FTIM0_GPCM_TEAHC(0x0e))
 251 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 252                                         FTIM1_GPCM_TRAD(0x1f))
 253 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 254                                         FTIM2_GPCM_TCH(0x8) | \
 255                                         FTIM2_GPCM_TWP(0x1f))
 256 #define CONFIG_SYS_CS2_FTIM3            0x0
 257
 258 /* NAND Flash on IFC */
 259 #define CONFIG_NAND_FSL_IFC
 260 #define CONFIG_SYS_NAND_BASE            0xff800000
 261 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 262
 263 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 264 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 265                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 266                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 267                                 | CSPR_V)
 268 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 269
 270 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 271                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 272                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 273                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 274                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 275                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 276                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 277
 278 #define CONFIG_SYS_NAND_ONFI_DETECTION
 279
 280 /* ONFI NAND Flash mode0 Timing Params */
 281 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 282                                         FTIM0_NAND_TWP(0x18)    | \
 283                                         FTIM0_NAND_TWCHT(0x07)  | \
 284                                         FTIM0_NAND_TWH(0x0a))
 285 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 286                                         FTIM1_NAND_TWBE(0x39)   | \
 287                                         FTIM1_NAND_TRR(0x0e)    | \
 288                                         FTIM1_NAND_TRP(0x18))
 289 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 290                                         FTIM2_NAND_TREH(0x0a)   | \
 291                                         FTIM2_NAND_TWHRE(0x1e))
 292 #define CONFIG_SYS_NAND_FTIM3           0x0
 293
 294 #define CONFIG_SYS_NAND_DDR_LAW         11
 295 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 296 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 297 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 298
 299 #if defined(CONFIG_NAND)
 300 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 301 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 302 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 303 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 304 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 305 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 306 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 307 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 308 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 309 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 310 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 316 #else
 317 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 318 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 319 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 320 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 321 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 322 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 323 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 324 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 325 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 326 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 327 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 328 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 329 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 330 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 331 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 332 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 333 #endif
 334
 335 #if defined(CONFIG_RAMBOOT_PBL)
 336 #define CONFIG_SYS_RAMBOOT
 337 #endif
 338
 339 #ifdef CONFIG_SPL_BUILD
 340 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 341 #else
 342 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 343 #endif
 344
 345 #define CONFIG_MISC_INIT_R
 346 #define CONFIG_HWCONFIG
 347
 348 /* define to use L1 as initial stack */
 349 #define CONFIG_L1_INIT_RAM
 350 #define CONFIG_SYS_INIT_RAM_LOCK
 351 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 353 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 354 /* The assembler doesn't like typecast */
 355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 356                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 357                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 358 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 359 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 360                                                 GENERATED_GBL_DATA_SIZE)
 361 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 362 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 363 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 364
 365 /*
 366  * Serial Port
 367  */
 368 #define CONFIG_SYS_NS16550_SERIAL
 369 #define CONFIG_SYS_NS16550_REG_SIZE     1
 370 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 371 #define CONFIG_SYS_BAUDRATE_TABLE       \
 372         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 373 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 374 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 375 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 376 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 377
 378 /*
 379  * I2C
 380  */
 381 #define CONFIG_SYS_I2C
 382 #define CONFIG_SYS_I2C_FSL
 383 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 384 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 385 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 386 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 387 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 388 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 389 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 390 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 391 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 392 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 393 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 394 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 395 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 396 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 397 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 398 #define I2C_MUX_CH_DEFAULT      0x8
 399
 400 #define I2C_MUX_CH_VOL_MONITOR  0xa
 401
 402 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 403 #ifndef CONFIG_SPL_BUILD
 404 #define CONFIG_VID
 405 #endif
 406 #define CONFIG_VOL_MONITOR_IR36021_SET
 407 #define CONFIG_VOL_MONITOR_IR36021_READ
 408 /* The lowest and highest voltage allowed for T208xRDB */
 409 #define VDD_MV_MIN                      819
 410 #define VDD_MV_MAX                      1212
 411
 412 /*
 413  * RapidIO
 414  */
 415 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 416 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 417 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 418 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 419 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 420 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 421 /*
 422  * for slave u-boot IMAGE instored in master memory space,
 423  * PHYS must be aligned based on the SIZE
 424  */
 425 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 429 /*
 430  * for slave UCODE and ENV instored in master memory space,
 431  * PHYS must be aligned based on the SIZE
 432  */
 433 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 435 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 436
 437 /* slave core release by master*/
 438 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 439 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 440
 441 /*
 442  * SRIO_PCIE_BOOT - SLAVE
 443  */
 444 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 445 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 446 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 447                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 448 #endif
 449
 450 /*
 451  * eSPI - Enhanced SPI
 452  */
 453 #ifdef CONFIG_SPI_FLASH
 454 #define CONFIG_SPI_FLASH_BAR
 455 #define CONFIG_SF_DEFAULT_SPEED  10000000
 456 #define CONFIG_SF_DEFAULT_MODE    0
 457 #endif
 458
 459 /*
 460  * General PCI
 461  * Memory space is mapped 1-1, but I/O space must start from 0.
 462  */
 463 #define CONFIG_PCIE1            /* PCIE controller 1 */
 464 #define CONFIG_PCIE2            /* PCIE controller 2 */
 465 #define CONFIG_PCIE3            /* PCIE controller 3 */
 466 #define CONFIG_PCIE4            /* PCIE controller 4 */
 467 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 468 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 469 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 470 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 471 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 472 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 473 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 474 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 475 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 476 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 477 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 478
 479 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 480 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 481 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 482 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 483 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 484 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 485 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 486 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 487 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 488
 489 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 490 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 491 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 492 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 493 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 494 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 495 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 496 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 497 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 498
 499 /* controller 4, Base address 203000 */
 500 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 501 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 502 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 503 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 504 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 505 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 506 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 507
 508 #ifdef CONFIG_PCI
 509 #define CONFIG_PCI_INDIRECT_BRIDGE
 510 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 511 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 512 #endif
 513
 514 /* Qman/Bman */
 515 #ifndef CONFIG_NOBQFMAN
 516 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 517 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 518 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 519 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 520 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 521 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 522 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 523 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 524 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 525                                         CONFIG_SYS_BMAN_CENA_SIZE)
 526 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 527 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 528 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 529 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 530 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 531 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 532 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 533 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 534 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 535 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 536 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 537                                         CONFIG_SYS_QMAN_CENA_SIZE)
 538 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 539 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 540
 541 #define CONFIG_SYS_DPAA_FMAN
 542 #define CONFIG_SYS_DPAA_PME
 543 #define CONFIG_SYS_PMAN
 544 #define CONFIG_SYS_DPAA_DCE
 545 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 546 #define CONFIG_SYS_INTERLAKEN
 547
 548 /* Default address of microcode for the Linux Fman driver */
 549 #if defined(CONFIG_SPIFLASH)
 550 /*
 551  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 552  * env, so we got 0x110000.
 553  */
 554 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 555 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 556 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 557 #define CONFIG_CORTINA_FW_ADDR          0x120000
 558
 559 #elif defined(CONFIG_SDCARD)
 560 /*
 561  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 562  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 563  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 564  */
 565 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 566 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 567 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 568 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 569
 570 #elif defined(CONFIG_NAND)
 571 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 572 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 573 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 574 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 575 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 576 /*
 577  * Slave has no ucode locally, it can fetch this from remote. When implementing
 578  * in two corenet boards, slave's ucode could be stored in master's memory
 579  * space, the address can be mapped from slave TLB->slave LAW->
 580  * slave SRIO or PCIE outbound window->master inbound window->
 581  * master LAW->the ucode address in master's memory space.
 582  */
 583 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 584 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 585 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 586 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 587 #else
 588 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 589 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 590 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 591 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 592 #endif
 593 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 594 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 595 #endif /* CONFIG_NOBQFMAN */
 596
 597 #ifdef CONFIG_SYS_DPAA_FMAN
 598 #define CONFIG_FMAN_ENET
 599 #define CONFIG_PHYLIB_10G
 600 #define CONFIG_PHY_AQUANTIA
 601 #define CONFIG_PHY_CORTINA
 602 #define CONFIG_PHY_REALTEK
 603 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 604 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 605 #define RGMII_PHY2_ADDR         0x02
 606 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 607 #define CORTINA_PHY_ADDR2       0x0d
 608 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 609 #define FM1_10GEC4_PHY_ADDR     0x01
 610 #endif
 611
 612 #ifdef CONFIG_FMAN_ENET
 613 #define CONFIG_MII              /* MII PHY management */
 614 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 615 #endif
 616
 617 /*
 618  * SATA
 619  */
 620 #ifdef CONFIG_FSL_SATA_V2
 621 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 622 #define CONFIG_SATA1
 623 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 624 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 625 #define CONFIG_SATA2
 626 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 627 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 628 #define CONFIG_LBA48
 629 #endif
 630
 631 /*
 632  * USB
 633  */
 634 #ifdef CONFIG_USB_EHCI_HCD
 635 #define CONFIG_USB_EHCI_FSL
 636 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 637 #define CONFIG_HAS_FSL_DR_USB
 638 #endif
 639
 640 /*
 641  * SDHC
 642  */
 643 #ifdef CONFIG_MMC
 644 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 645 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 646 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 647 #endif
 648
 649 /*
 650  * Dynamic MTD Partition support with mtdparts
 651  */
 652 #ifdef CONFIG_MTD_NOR_FLASH
 653 #define CONFIG_MTD_DEVICE
 654 #define CONFIG_MTD_PARTITIONS
 655 #define CONFIG_FLASH_CFI_MTD
 656 #endif
 657
 658 /*
 659  * Environment
 660  */
 661
 662 /*
 663  * Miscellaneous configurable options
 664  */
 665 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 666
 667 /*
 668  * For booting Linux, the board info and command line data
 669  * have to be in the first 64 MB of memory, since this is
 670  * the maximum mapped by the Linux kernel during initialization.
 671  */
 672 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 673 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 674
 675 #ifdef CONFIG_CMD_KGDB
 676 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 677 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 678 #endif
 679
 680 /*
 681  * Environment Configuration
 682  */
 683 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 684 #define CONFIG_BOOTFILE  "uImage"
 685 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 686
 687 /* default location for tftp and bootm */
 688 #define CONFIG_LOADADDR         1000000
 689 #define __USB_PHY_TYPE          utmi
 690
 691 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 692         "hwconfig=fsl_ddr:"                                     \
 693         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 694         "bank_intlv=auto;"                                      \
 695         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 696         "netdev=eth0\0"                                         \
 697         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 698         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 699         "tftpflash=tftpboot $loadaddr $uboot && "               \
 700         "protect off $ubootaddr +$filesize && "                 \
 701         "erase $ubootaddr +$filesize && "                       \
 702         "cp.b $loadaddr $ubootaddr $filesize && "               \
 703         "protect on $ubootaddr +$filesize && "                  \
 704         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 705         "consoledev=ttyS0\0"                                    \
 706         "ramdiskaddr=2000000\0"                                 \
 707         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 708         "fdtaddr=1e00000\0"                                     \
 709         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 710         "bdev=sda3\0"
 711
 712 /*
 713  * For emulation this causes u-boot to jump to the start of the
 714  * proof point app code automatically
 715  */
 716 #define CONFIG_PROOF_POINTS                             \
 717         "setenv bootargs root=/dev/$bdev rw "           \
 718         "console=$consoledev,$baudrate $othbootargs;"   \
 719         "cpu 1 release 0x29000000 - - -;"               \
 720         "cpu 2 release 0x29000000 - - -;"               \
 721         "cpu 3 release 0x29000000 - - -;"               \
 722         "cpu 4 release 0x29000000 - - -;"               \
 723         "cpu 5 release 0x29000000 - - -;"               \
 724         "cpu 6 release 0x29000000 - - -;"               \
 725         "cpu 7 release 0x29000000 - - -;"               \
 726         "go 0x29000000"
 727
 728 #define CONFIG_HVBOOT                           \
 729         "setenv bootargs config-addr=0x60000000; "      \
 730         "bootm 0x01000000 - 0x00f00000"
 731
 732 #define CONFIG_ALU                              \
 733         "setenv bootargs root=/dev/$bdev rw "           \
 734         "console=$consoledev,$baudrate $othbootargs;"   \
 735         "cpu 1 release 0x01000000 - - -;"               \
 736         "cpu 2 release 0x01000000 - - -;"               \
 737         "cpu 3 release 0x01000000 - - -;"               \
 738         "cpu 4 release 0x01000000 - - -;"               \
 739         "cpu 5 release 0x01000000 - - -;"               \
 740         "cpu 6 release 0x01000000 - - -;"               \
 741         "cpu 7 release 0x01000000 - - -;"               \
 742         "go 0x01000000"
 743
 744 #define CONFIG_LINUX                            \
 745         "setenv bootargs root=/dev/ram rw "             \
 746         "console=$consoledev,$baudrate $othbootargs;"   \
 747         "setenv ramdiskaddr 0x02000000;"                \
 748         "setenv fdtaddr 0x00c00000;"                    \
 749         "setenv loadaddr 0x1000000;"                    \
 750         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 751
 752 #define CONFIG_HDBOOT                                   \
 753         "setenv bootargs root=/dev/$bdev rw "           \
 754         "console=$consoledev,$baudrate $othbootargs;"   \
 755         "tftp $loadaddr $bootfile;"                     \
 756         "tftp $fdtaddr $fdtfile;"                       \
 757         "bootm $loadaddr - $fdtaddr"
 758
 759 #define CONFIG_NFSBOOTCOMMAND                   \
 760         "setenv bootargs root=/dev/nfs rw "     \
 761         "nfsroot=$serverip:$rootpath "          \
 762         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 763         "console=$consoledev,$baudrate $othbootargs;"   \
 764         "tftp $loadaddr $bootfile;"             \
 765         "tftp $fdtaddr $fdtfile;"               \
 766         "bootm $loadaddr - $fdtaddr"
 767
 768 #define CONFIG_RAMBOOTCOMMAND                           \
 769         "setenv bootargs root=/dev/ram rw "             \
 770         "console=$consoledev,$baudrate $othbootargs;"   \
 771         "tftp $ramdiskaddr $ramdiskfile;"               \
 772         "tftp $loadaddr $bootfile;"                     \
 773         "tftp $fdtaddr $fdtfile;"                       \
 774         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 775
 776 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 777
 778 #include <asm/fsl_secure_boot.h>
 779
 780 #endif  /* __T2080RDB_H */