2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080 RDB/PCIe board configuration file
14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15 #define CONFIG_FSL_SATA_V2
17 /* High Level Configuration Options */
18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
19 #define CONFIG_MP /* support multiple processors */
20 #define CONFIG_ENABLE_36BIT_PHYS
22 #ifdef CONFIG_PHYS_64BIT
23 #define CONFIG_ADDR_MAP 1
24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
29 #define CONFIG_ENV_OVERWRITE
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37 #define CONFIG_SPL_PAD_TO 0x40000
38 #define CONFIG_SPL_MAX_SIZE 0x28000
39 #define RESET_VECTOR_OFFSET 0x27FFC
40 #define BOOT_PAGE_OFFSET 0x27000
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_SKIP_RELOCATE
43 #define CONFIG_SPL_COMMON_INIT_DDR
44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
54 #define CONFIG_SPL_NAND_BOOT
57 #ifdef CONFIG_SPIFLASH
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
69 #define CONFIG_SPL_SPI_BOOT
73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
74 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
75 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
76 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
77 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
79 #ifndef CONFIG_SPL_BUILD
80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
83 #define CONFIG_SPL_MMC_BOOT
86 #endif /* CONFIG_RAMBOOT_PBL */
88 #define CONFIG_SRIO_PCIE_BOOT_MASTER
89 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
90 /* Set 1M boot space */
91 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
93 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
97 #ifndef CONFIG_RESET_VECTOR_ADDRESS
98 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
102 * These can be toggled for performance analysis, otherwise use default.
104 #define CONFIG_SYS_CACHE_STASHING
105 #define CONFIG_BTB /* toggle branch predition */
106 #define CONFIG_DDR_ECC
107 #ifdef CONFIG_DDR_ECC
108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
109 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
113 #define CONFIG_SYS_MEMTEST_END 0x00400000
115 #ifdef CONFIG_MTD_NOR_FLASH
116 #define CONFIG_FLASH_CFI_DRIVER
117 #define CONFIG_SYS_FLASH_CFI
118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
121 #if defined(CONFIG_SPIFLASH)
122 #define CONFIG_SYS_EXTRA_ENV_RELOC
123 #define CONFIG_ENV_SPI_BUS 0
124 #define CONFIG_ENV_SPI_CS 0
125 #define CONFIG_ENV_SPI_MAX_HZ 10000000
126 #define CONFIG_ENV_SPI_MODE 0
127 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
128 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
129 #define CONFIG_ENV_SECT_SIZE 0x10000
130 #elif defined(CONFIG_SDCARD)
131 #define CONFIG_SYS_EXTRA_ENV_RELOC
132 #define CONFIG_SYS_MMC_ENV_DEV 0
133 #define CONFIG_ENV_SIZE 0x2000
134 #define CONFIG_ENV_OFFSET (512 * 0x800)
135 #elif defined(CONFIG_NAND)
136 #define CONFIG_SYS_EXTRA_ENV_RELOC
137 #define CONFIG_ENV_SIZE 0x2000
138 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
139 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
140 #define CONFIG_ENV_ADDR 0xffe20000
141 #define CONFIG_ENV_SIZE 0x2000
142 #elif defined(CONFIG_ENV_IS_NOWHERE)
143 #define CONFIG_ENV_SIZE 0x2000
145 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
146 #define CONFIG_ENV_SIZE 0x2000
147 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
151 unsigned long get_board_sys_clk(void);
152 unsigned long get_board_ddr_clk(void);
155 #define CONFIG_SYS_CLK_FREQ 66660000
156 #define CONFIG_DDR_CLK_FREQ 133330000
159 * Config the L3 Cache as L3 SRAM
161 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
162 #define CONFIG_SYS_L3_SIZE (512 << 10)
163 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
164 #ifdef CONFIG_RAMBOOT_PBL
165 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
167 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
168 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
169 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
170 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
172 #define CONFIG_SYS_DCSRBAR 0xf0000000
173 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
176 #define CONFIG_ID_EEPROM
177 #define CONFIG_SYS_I2C_EEPROM_NXID
178 #define CONFIG_SYS_EEPROM_BUS_NUM 0
179 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
185 #define CONFIG_VERY_BIG_RAM
186 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
187 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
189 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
190 #define CONFIG_DDR_SPD
191 #undef CONFIG_FSL_DDR_INTERACTIVE
192 #define CONFIG_SYS_SPD_BUS_NUM 0
193 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
194 #define SPD_EEPROM_ADDRESS1 0x51
195 #define SPD_EEPROM_ADDRESS2 0x52
196 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
197 #define CTRL_INTLV_PREFERED cacheline
202 #define CONFIG_SYS_FLASH_BASE 0xe8000000
203 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
204 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
205 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
206 CSPR_PORT_SIZE_16 | \
209 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
211 /* NOR Flash Timing Params */
212 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
214 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
215 FTIM0_NOR_TEADC(0x5) | \
216 FTIM0_NOR_TEAHC(0x5))
217 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
218 FTIM1_NOR_TRAD_NOR(0x1A) |\
219 FTIM1_NOR_TSEQRAD_NOR(0x13))
220 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
221 FTIM2_NOR_TCH(0x4) | \
222 FTIM2_NOR_TWPH(0x0E) | \
224 #define CONFIG_SYS_NOR_FTIM3 0x0
226 #define CONFIG_SYS_FLASH_QUIET_TEST
227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
229 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
233 #define CONFIG_SYS_FLASH_EMPTY_INFO
234 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
237 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
238 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
239 #define CONFIG_SYS_CSPR2_EXT (0xf)
240 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
244 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
245 #define CONFIG_SYS_CSOR2 0x0
247 /* CPLD Timing parameters for IFC CS2 */
248 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
249 FTIM0_GPCM_TEADC(0x0e) | \
250 FTIM0_GPCM_TEAHC(0x0e))
251 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
252 FTIM1_GPCM_TRAD(0x1f))
253 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
254 FTIM2_GPCM_TCH(0x8) | \
255 FTIM2_GPCM_TWP(0x1f))
256 #define CONFIG_SYS_CS2_FTIM3 0x0
258 /* NAND Flash on IFC */
259 #define CONFIG_NAND_FSL_IFC
260 #define CONFIG_SYS_NAND_BASE 0xff800000
261 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
263 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
264 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
265 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
266 | CSPR_MSEL_NAND /* MSEL = NAND */ \
268 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
270 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
271 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
272 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
273 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
274 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
275 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
276 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
278 #define CONFIG_SYS_NAND_ONFI_DETECTION
280 /* ONFI NAND Flash mode0 Timing Params */
281 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
282 FTIM0_NAND_TWP(0x18) | \
283 FTIM0_NAND_TWCHT(0x07) | \
284 FTIM0_NAND_TWH(0x0a))
285 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
286 FTIM1_NAND_TWBE(0x39) | \
287 FTIM1_NAND_TRR(0x0e) | \
288 FTIM1_NAND_TRP(0x18))
289 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
290 FTIM2_NAND_TREH(0x0a) | \
291 FTIM2_NAND_TWHRE(0x1e))
292 #define CONFIG_SYS_NAND_FTIM3 0x0
294 #define CONFIG_SYS_NAND_DDR_LAW 11
295 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
296 #define CONFIG_SYS_MAX_NAND_DEVICE 1
297 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
299 #if defined(CONFIG_NAND)
300 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
301 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
302 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
303 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
304 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
305 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
306 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
307 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
308 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
318 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
319 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
325 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
335 #if defined(CONFIG_RAMBOOT_PBL)
336 #define CONFIG_SYS_RAMBOOT
339 #ifdef CONFIG_SPL_BUILD
340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
342 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
345 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
346 #define CONFIG_MISC_INIT_R
347 #define CONFIG_HWCONFIG
349 /* define to use L1 as initial stack */
350 #define CONFIG_L1_INIT_RAM
351 #define CONFIG_SYS_INIT_RAM_LOCK
352 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
353 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
355 /* The assembler doesn't like typecast */
356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
357 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
358 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
359 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
360 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
361 GENERATED_GBL_DATA_SIZE)
362 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
363 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
364 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
369 #define CONFIG_SYS_NS16550_SERIAL
370 #define CONFIG_SYS_NS16550_REG_SIZE 1
371 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
372 #define CONFIG_SYS_BAUDRATE_TABLE \
373 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
374 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
375 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
376 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
377 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
382 #define CONFIG_SYS_I2C
383 #define CONFIG_SYS_I2C_FSL
384 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
385 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
386 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
387 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
388 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
389 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
390 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
391 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
392 #define CONFIG_SYS_FSL_I2C_SPEED 100000
393 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
394 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
395 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
396 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
397 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
398 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
399 #define I2C_MUX_CH_DEFAULT 0x8
401 #define I2C_MUX_CH_VOL_MONITOR 0xa
403 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
404 #ifndef CONFIG_SPL_BUILD
407 #define CONFIG_VOL_MONITOR_IR36021_SET
408 #define CONFIG_VOL_MONITOR_IR36021_READ
409 /* The lowest and highest voltage allowed for T208xRDB */
410 #define VDD_MV_MIN 819
411 #define VDD_MV_MAX 1212
416 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
417 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
418 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
419 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
420 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
421 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
423 * for slave u-boot IMAGE instored in master memory space,
424 * PHYS must be aligned based on the SIZE
426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
431 * for slave UCODE and ENV instored in master memory space,
432 * PHYS must be aligned based on the SIZE
434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
435 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
436 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
438 /* slave core release by master*/
439 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
440 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
443 * SRIO_PCIE_BOOT - SLAVE
445 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
446 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
447 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
448 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
452 * eSPI - Enhanced SPI
454 #ifdef CONFIG_SPI_FLASH
455 #define CONFIG_SPI_FLASH_BAR
456 #define CONFIG_SF_DEFAULT_SPEED 10000000
457 #define CONFIG_SF_DEFAULT_MODE 0
462 * Memory space is mapped 1-1, but I/O space must start from 0.
464 #define CONFIG_PCIE1 /* PCIE controller 1 */
465 #define CONFIG_PCIE2 /* PCIE controller 2 */
466 #define CONFIG_PCIE3 /* PCIE controller 3 */
467 #define CONFIG_PCIE4 /* PCIE controller 4 */
468 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
469 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
470 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
471 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
472 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
474 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
475 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
476 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
478 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
480 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
481 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
482 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
483 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
486 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
487 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
488 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
490 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
491 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
492 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
493 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
494 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
495 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
496 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
497 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
498 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
500 /* controller 4, Base address 203000 */
501 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
502 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
503 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
504 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
505 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
506 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
507 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
510 #define CONFIG_PCI_INDIRECT_BRIDGE
511 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
512 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
516 #ifndef CONFIG_NOBQFMAN
517 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
518 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
519 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
520 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
521 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
522 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
523 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
524 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
525 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
526 CONFIG_SYS_BMAN_CENA_SIZE)
527 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
528 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
529 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
530 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
531 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
532 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
533 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
534 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
535 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
536 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
537 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
538 CONFIG_SYS_QMAN_CENA_SIZE)
539 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
540 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
542 #define CONFIG_SYS_DPAA_FMAN
543 #define CONFIG_SYS_DPAA_PME
544 #define CONFIG_SYS_PMAN
545 #define CONFIG_SYS_DPAA_DCE
546 #define CONFIG_SYS_DPAA_RMAN /* RMan */
547 #define CONFIG_SYS_INTERLAKEN
549 /* Default address of microcode for the Linux Fman driver */
550 #if defined(CONFIG_SPIFLASH)
552 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
553 * env, so we got 0x110000.
555 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
556 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
557 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
558 #define CONFIG_CORTINA_FW_ADDR 0x120000
560 #elif defined(CONFIG_SDCARD)
562 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
563 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
564 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
566 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
567 #define CONFIG_SYS_CORTINA_FW_IN_MMC
568 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
569 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
571 #elif defined(CONFIG_NAND)
572 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
573 #define CONFIG_SYS_CORTINA_FW_IN_NAND
574 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
575 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
576 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
578 * Slave has no ucode locally, it can fetch this from remote. When implementing
579 * in two corenet boards, slave's ucode could be stored in master's memory
580 * space, the address can be mapped from slave TLB->slave LAW->
581 * slave SRIO or PCIE outbound window->master inbound window->
582 * master LAW->the ucode address in master's memory space.
584 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
585 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
586 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
587 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
589 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
590 #define CONFIG_SYS_CORTINA_FW_IN_NOR
591 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
592 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
594 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
595 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
596 #endif /* CONFIG_NOBQFMAN */
598 #ifdef CONFIG_SYS_DPAA_FMAN
599 #define CONFIG_FMAN_ENET
600 #define CONFIG_PHYLIB_10G
601 #define CONFIG_PHY_AQUANTIA
602 #define CONFIG_PHY_CORTINA
603 #define CONFIG_PHY_REALTEK
604 #define CONFIG_CORTINA_FW_LENGTH 0x40000
605 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
606 #define RGMII_PHY2_ADDR 0x02
607 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
608 #define CORTINA_PHY_ADDR2 0x0d
609 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
610 #define FM1_10GEC4_PHY_ADDR 0x01
613 #ifdef CONFIG_FMAN_ENET
614 #define CONFIG_MII /* MII PHY management */
615 #define CONFIG_ETHPRIME "FM1@DTSEC3"
621 #ifdef CONFIG_FSL_SATA_V2
622 #define CONFIG_SYS_SATA_MAX_DEVICE 2
624 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
625 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
627 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
628 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
635 #ifdef CONFIG_USB_EHCI_HCD
636 #define CONFIG_USB_EHCI_FSL
637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
638 #define CONFIG_HAS_FSL_DR_USB
645 #define CONFIG_FSL_ESDHC
646 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
647 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
648 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
652 * Dynamic MTD Partition support with mtdparts
654 #ifdef CONFIG_MTD_NOR_FLASH
655 #define CONFIG_MTD_DEVICE
656 #define CONFIG_MTD_PARTITIONS
657 #define CONFIG_FLASH_CFI_MTD
665 * Miscellaneous configurable options
667 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
670 * For booting Linux, the board info and command line data
671 * have to be in the first 64 MB of memory, since this is
672 * the maximum mapped by the Linux kernel during initialization.
674 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
675 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
677 #ifdef CONFIG_CMD_KGDB
678 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
679 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
683 * Environment Configuration
685 #define CONFIG_ROOTPATH "/opt/nfsroot"
686 #define CONFIG_BOOTFILE "uImage"
687 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
689 /* default location for tftp and bootm */
690 #define CONFIG_LOADADDR 1000000
691 #define __USB_PHY_TYPE utmi
693 #define CONFIG_EXTRA_ENV_SETTINGS \
694 "hwconfig=fsl_ddr:" \
695 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
697 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
699 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
700 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
701 "tftpflash=tftpboot $loadaddr $uboot && " \
702 "protect off $ubootaddr +$filesize && " \
703 "erase $ubootaddr +$filesize && " \
704 "cp.b $loadaddr $ubootaddr $filesize && " \
705 "protect on $ubootaddr +$filesize && " \
706 "cmp.b $loadaddr $ubootaddr $filesize\0" \
707 "consoledev=ttyS0\0" \
708 "ramdiskaddr=2000000\0" \
709 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
710 "fdtaddr=1e00000\0" \
711 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
715 * For emulation this causes u-boot to jump to the start of the
716 * proof point app code automatically
718 #define CONFIG_PROOF_POINTS \
719 "setenv bootargs root=/dev/$bdev rw " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "cpu 1 release 0x29000000 - - -;" \
722 "cpu 2 release 0x29000000 - - -;" \
723 "cpu 3 release 0x29000000 - - -;" \
724 "cpu 4 release 0x29000000 - - -;" \
725 "cpu 5 release 0x29000000 - - -;" \
726 "cpu 6 release 0x29000000 - - -;" \
727 "cpu 7 release 0x29000000 - - -;" \
730 #define CONFIG_HVBOOT \
731 "setenv bootargs config-addr=0x60000000; " \
732 "bootm 0x01000000 - 0x00f00000"
735 "setenv bootargs root=/dev/$bdev rw " \
736 "console=$consoledev,$baudrate $othbootargs;" \
737 "cpu 1 release 0x01000000 - - -;" \
738 "cpu 2 release 0x01000000 - - -;" \
739 "cpu 3 release 0x01000000 - - -;" \
740 "cpu 4 release 0x01000000 - - -;" \
741 "cpu 5 release 0x01000000 - - -;" \
742 "cpu 6 release 0x01000000 - - -;" \
743 "cpu 7 release 0x01000000 - - -;" \
746 #define CONFIG_LINUX \
747 "setenv bootargs root=/dev/ram rw " \
748 "console=$consoledev,$baudrate $othbootargs;" \
749 "setenv ramdiskaddr 0x02000000;" \
750 "setenv fdtaddr 0x00c00000;" \
751 "setenv loadaddr 0x1000000;" \
752 "bootm $loadaddr $ramdiskaddr $fdtaddr"
754 #define CONFIG_HDBOOT \
755 "setenv bootargs root=/dev/$bdev rw " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr - $fdtaddr"
761 #define CONFIG_NFSBOOTCOMMAND \
762 "setenv bootargs root=/dev/nfs rw " \
763 "nfsroot=$serverip:$rootpath " \
764 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
765 "console=$consoledev,$baudrate $othbootargs;" \
766 "tftp $loadaddr $bootfile;" \
767 "tftp $fdtaddr $fdtfile;" \
768 "bootm $loadaddr - $fdtaddr"
770 #define CONFIG_RAMBOOTCOMMAND \
771 "setenv bootargs root=/dev/ram rw " \
772 "console=$consoledev,$baudrate $othbootargs;" \
773 "tftp $ramdiskaddr $ramdiskfile;" \
774 "tftp $loadaddr $bootfile;" \
775 "tftp $fdtaddr $fdtfile;" \
776 "bootm $loadaddr $ramdiskaddr $fdtaddr"
778 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
780 #include <asm/fsl_secure_boot.h>
782 #endif /* __T2080RDB_H */