include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CFG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CFG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CFG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CFG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CFG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CFG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #ifdef CONFIG_DDR_ECC
  66 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67 #endif
  68
  69 /*
  70  * Config the L3 Cache as L3 SRAM
  71  */
  72 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  73 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  74
  75 #define CFG_SYS_DCSRBAR 0xf0000000
  76 #define CFG_SYS_DCSRBAR_PHYS    0xf00000000ull
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #define CONFIG_VERY_BIG_RAM
  82 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  83 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  84 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  85 #define SPD_EEPROM_ADDRESS1     0x51
  86 #define SPD_EEPROM_ADDRESS2     0x52
  87 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  88 #define CTRL_INTLV_PREFERED     cacheline
  89
  90 /*
  91  * IFC Definitions
  92  */
  93 #define CFG_SYS_FLASH_BASE              0xe8000000
  94 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  95 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
  96 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  97                                 CSPR_PORT_SIZE_16 | \
  98                                 CSPR_MSEL_NOR | \
  99                                 CSPR_V)
 100 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 101
 102 /* NOR Flash Timing Params */
 103 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 104
 105 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 106                                 FTIM0_NOR_TEADC(0x5) | \
 107                                 FTIM0_NOR_TEAHC(0x5))
 108 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 109                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 110                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 111 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 112                                 FTIM2_NOR_TCH(0x4) | \
 113                                 FTIM2_NOR_TWPH(0x0E) | \
 114                                 FTIM2_NOR_TWP(0x1c))
 115 #define CFG_SYS_NOR_FTIM3       0x0
 116
 117 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS }
 118
 119 /* CPLD on IFC */
 120 #define CFG_SYS_CPLD_BASE       0xffdf0000
 121 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 122 #define CFG_SYS_CSPR2_EXT       (0xf)
 123 #define CFG_SYS_CSPR2   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 124                                 | CSPR_PORT_SIZE_8 \
 125                                 | CSPR_MSEL_GPCM \
 126                                 | CSPR_V)
 127 #define CFG_SYS_AMASK2  IFC_AMASK(64*1024)
 128 #define CFG_SYS_CSOR2   0x0
 129
 130 /* CPLD Timing parameters for IFC CS2 */
 131 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 132                                         FTIM0_GPCM_TEADC(0x0e) | \
 133                                         FTIM0_GPCM_TEAHC(0x0e))
 134 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 135                                         FTIM1_GPCM_TRAD(0x1f))
 136 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 137                                         FTIM2_GPCM_TCH(0x8) | \
 138                                         FTIM2_GPCM_TWP(0x1f))
 139 #define CFG_SYS_CS2_FTIM3               0x0
 140
 141 /* NAND Flash on IFC */
 142 #define CFG_SYS_NAND_BASE               0xff800000
 143 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 144
 145 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 146 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 147                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 148                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 149                                 | CSPR_V)
 150 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 151
 152 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 153                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 154                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 155                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 156                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 157                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 158                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 159
 160 /* ONFI NAND Flash mode0 Timing Params */
 161 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 162                                         FTIM0_NAND_TWP(0x18)    | \
 163                                         FTIM0_NAND_TWCHT(0x07)  | \
 164                                         FTIM0_NAND_TWH(0x0a))
 165 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 166                                         FTIM1_NAND_TWBE(0x39)   | \
 167                                         FTIM1_NAND_TRR(0x0e)    | \
 168                                         FTIM1_NAND_TRP(0x18))
 169 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 170                                         FTIM2_NAND_TREH(0x0a)   | \
 171                                         FTIM2_NAND_TWHRE(0x1e))
 172 #define CFG_SYS_NAND_FTIM3              0x0
 173
 174 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 175
 176 #if defined(CONFIG_MTD_RAW_NAND)
 177 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 178 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 179 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 180 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 181 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 182 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 183 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 184 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 185 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 186 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 187 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 188 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 189 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 190 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 191 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 192 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 193 #else
 194 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 195 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 196 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 197 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 198 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 199 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 200 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 201 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 202 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 203 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 204 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 205 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 206 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 207 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 208 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 209 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 210 #endif
 211
 212 /* define to use L1 as initial stack */
 213 #define CONFIG_L1_INIT_RAM
 214 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000 /* Initial L1 address */
 215 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 216 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 217 /* The assembler doesn't like typecast */
 218 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 219                         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 220                         CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 221 #define CFG_SYS_INIT_RAM_SIZE   0x00004000
 222 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 223
 224 /*
 225  * Serial Port
 226  */
 227 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 228 #define CFG_SYS_BAUDRATE_TABLE  \
 229         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 230 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
 231 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
 232 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
 233 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 234
 235 /*
 236  * I2C
 237  */
 238
 239 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 240 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 241 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 242 #define I2C_MUX_CH_DEFAULT      0x8
 243
 244 #define I2C_MUX_CH_VOL_MONITOR  0xa
 245
 246 /* The lowest and highest voltage allowed for T208xRDB */
 247 #define VDD_MV_MIN                      819
 248 #define VDD_MV_MAX                      1212
 249
 250 /*
 251  * RapidIO
 252  */
 253 #define CFG_SYS_SRIO1_MEM_VIRT  0xa0000000
 254 #define CFG_SYS_SRIO1_MEM_PHYS  0xc20000000ull
 255 #define CFG_SYS_SRIO1_MEM_SIZE  0x10000000 /* 256M */
 256 #define CFG_SYS_SRIO2_MEM_VIRT  0xb0000000
 257 #define CFG_SYS_SRIO2_MEM_PHYS  0xc30000000ull
 258 #define CFG_SYS_SRIO2_MEM_SIZE  0x10000000 /* 256M */
 259 /*
 260  * for slave u-boot IMAGE instored in master memory space,
 261  * PHYS must be aligned based on the SIZE
 262  */
 263 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 264 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 265 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 266 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 267 /*
 268  * for slave UCODE and ENV instored in master memory space,
 269  * PHYS must be aligned based on the SIZE
 270  */
 271 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 272 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 273 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000    /* 256K */
 274
 275 /* slave core release by master*/
 276 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 277 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 278
 279 /*
 280  * SRIO_PCIE_BOOT - SLAVE
 281  */
 282 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 283 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 284 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 285                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 286 #endif
 287
 288 /*
 289  * eSPI - Enhanced SPI
 290  */
 291
 292 /*
 293  * General PCI
 294  * Memory space is mapped 1-1, but I/O space must start from 0.
 295  */
 296 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 297 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 298 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 299 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 300 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 301
 302 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 303 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 304 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 305 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 306 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 307
 308 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 309 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 310 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 311
 312 /* controller 4, Base address 203000 */
 313 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 314 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 315
 316 /* Qman/Bman */
 317 #ifndef CONFIG_NOBQFMAN
 318 #define CFG_SYS_BMAN_NUM_PORTALS        18
 319 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 320 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 321 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 322 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 323 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 324 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 325 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 326 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 327                                         CFG_SYS_BMAN_CENA_SIZE)
 328 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 329 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 330 #define CFG_SYS_QMAN_NUM_PORTALS        18
 331 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 332 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 333 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 334 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 335 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 336 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 337                                         CFG_SYS_QMAN_CENA_SIZE)
 338 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 339 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 340 #endif /* CONFIG_NOBQFMAN */
 341
 342 #ifdef CONFIG_SYS_DPAA_FMAN
 343 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 344 #define RGMII_PHY2_ADDR         0x02
 345 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 346 #define CORTINA_PHY_ADDR2       0x0d
 347 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 348 #define FM1_10GEC3_PHY_ADDR     0x00
 349 #define FM1_10GEC4_PHY_ADDR     0x01
 350 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 351 #define AQR113C_PHY_ADDR1       0x00
 352 #define AQR113C_PHY_ADDR2       0x08
 353 #endif
 354
 355 /*
 356  * USB
 357  */
 358
 359 /*
 360  * SDHC
 361  */
 362 #ifdef CONFIG_MMC
 363 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 364 #endif
 365
 366 /*
 367  * Dynamic MTD Partition support with mtdparts
 368  */
 369
 370 /*
 371  * Environment
 372  */
 373
 374 /*
 375  * Miscellaneous configurable options
 376  */
 377
 378 /*
 379  * For booting Linux, the board info and command line data
 380  * have to be in the first 64 MB of memory, since this is
 381  * the maximum mapped by the Linux kernel during initialization.
 382  */
 383 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 384
 385 /*
 386  * Environment Configuration
 387  */
 388
 389 #define __USB_PHY_TYPE          utmi
 390
 391 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 392         "hwconfig=fsl_ddr:"                                     \
 393         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 394         "bank_intlv=auto;"                                      \
 395         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 396         "netdev=eth0\0"                                         \
 397         "uboot=" CONFIG_UBOOTPATH "\0"          \
 398         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 399         "tftpflash=tftpboot $loadaddr $uboot && "               \
 400         "protect off $ubootaddr +$filesize && "                 \
 401         "erase $ubootaddr +$filesize && "                       \
 402         "cp.b $loadaddr $ubootaddr $filesize && "               \
 403         "protect on $ubootaddr +$filesize && "                  \
 404         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 405         "consoledev=ttyS0\0"                                    \
 406         "ramdiskaddr=2000000\0"                                 \
 407         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 408         "fdtaddr=1e00000\0"                                     \
 409         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 410         "bdev=sda3\0"
 411
 412 /*
 413  * For emulation this causes u-boot to jump to the start of the
 414  * proof point app code automatically
 415  */
 416 #define PROOF_POINTS                            \
 417         "setenv bootargs root=/dev/$bdev rw "           \
 418         "console=$consoledev,$baudrate $othbootargs;"   \
 419         "cpu 1 release 0x29000000 - - -;"               \
 420         "cpu 2 release 0x29000000 - - -;"               \
 421         "cpu 3 release 0x29000000 - - -;"               \
 422         "cpu 4 release 0x29000000 - - -;"               \
 423         "cpu 5 release 0x29000000 - - -;"               \
 424         "cpu 6 release 0x29000000 - - -;"               \
 425         "cpu 7 release 0x29000000 - - -;"               \
 426         "go 0x29000000"
 427
 428 #define HVBOOT                          \
 429         "setenv bootargs config-addr=0x60000000; "      \
 430         "bootm 0x01000000 - 0x00f00000"
 431
 432 #define ALU                             \
 433         "setenv bootargs root=/dev/$bdev rw "           \
 434         "console=$consoledev,$baudrate $othbootargs;"   \
 435         "cpu 1 release 0x01000000 - - -;"               \
 436         "cpu 2 release 0x01000000 - - -;"               \
 437         "cpu 3 release 0x01000000 - - -;"               \
 438         "cpu 4 release 0x01000000 - - -;"               \
 439         "cpu 5 release 0x01000000 - - -;"               \
 440         "cpu 6 release 0x01000000 - - -;"               \
 441         "cpu 7 release 0x01000000 - - -;"               \
 442         "go 0x01000000"
 443
 444 #include <asm/fsl_secure_boot.h>
 445
 446 #endif  /* __T2080RDB_H */