include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_FSL_SATA_V2
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  19 #define CONFIG_MP               /* support multiple processors */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #ifdef CONFIG_PHYS_64BIT
  23 #define CONFIG_ADDR_MAP 1
  24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  25 #endif
  26
  27 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  29 #define CONFIG_ENV_OVERWRITE
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  36 #define CONFIG_SYS_TEXT_BASE            0x00201000
  37 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  38 #define CONFIG_SPL_PAD_TO               0x40000
  39 #define CONFIG_SPL_MAX_SIZE             0x28000
  40 #define RESET_VECTOR_OFFSET             0x27FFC
  41 #define BOOT_PAGE_OFFSET                0x27000
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_SKIP_RELOCATE
  44 #define CONFIG_SPL_COMMON_INIT_DDR
  45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  46 #endif
  47
  48 #ifdef CONFIG_NAND
  49 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  50 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  51 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  53 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  55 #define CONFIG_SPL_NAND_BOOT
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  65 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68 #endif
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  70 #define CONFIG_SPL_SPI_BOOT
  71 #endif
  72
  73 #ifdef CONFIG_SDCARD
  74 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  75 #define CONFIG_SPL_MMC_MINIMAL
  76 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  77 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  78 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  79 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  80 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  85 #define CONFIG_SPL_MMC_BOOT
  86 #endif
  87
  88 #endif /* CONFIG_RAMBOOT_PBL */
  89
  90 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  91 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  92 /* Set 1M boot space */
  93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  94 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  95                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  96 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  97 #endif
  98
  99 #ifndef CONFIG_SYS_TEXT_BASE
 100 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 101 #endif
 102
 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 104 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 105 #endif
 106
 107 /*
 108  * These can be toggled for performance analysis, otherwise use default.
 109  */
 110 #define CONFIG_SYS_CACHE_STASHING
 111 #define CONFIG_BTB              /* toggle branch predition */
 112 #define CONFIG_DDR_ECC
 113 #ifdef CONFIG_DDR_ECC
 114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 115 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 116 #endif
 117
 118 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 119 #define CONFIG_SYS_MEMTEST_END          0x00400000
 120 #define CONFIG_SYS_ALT_MEMTEST
 121
 122 #ifdef CONFIG_MTD_NOR_FLASH
 123 #define CONFIG_FLASH_CFI_DRIVER
 124 #define CONFIG_SYS_FLASH_CFI
 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 126 #endif
 127
 128 #if defined(CONFIG_SPIFLASH)
 129 #define CONFIG_SYS_EXTRA_ENV_RELOC
 130 #define CONFIG_ENV_IS_IN_SPI_FLASH
 131 #define CONFIG_ENV_SPI_BUS      0
 132 #define CONFIG_ENV_SPI_CS       0
 133 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 134 #define CONFIG_ENV_SPI_MODE     0
 135 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 136 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 137 #define CONFIG_ENV_SECT_SIZE    0x10000
 138 #elif defined(CONFIG_SDCARD)
 139 #define CONFIG_SYS_EXTRA_ENV_RELOC
 140 #define CONFIG_SYS_MMC_ENV_DEV  0
 141 #define CONFIG_ENV_SIZE         0x2000
 142 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 143 #elif defined(CONFIG_NAND)
 144 #define CONFIG_SYS_EXTRA_ENV_RELOC
 145 #define CONFIG_ENV_SIZE         0x2000
 146 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 147 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 148 #define CONFIG_ENV_IS_IN_REMOTE
 149 #define CONFIG_ENV_ADDR         0xffe20000
 150 #define CONFIG_ENV_SIZE         0x2000
 151 #elif defined(CONFIG_ENV_IS_NOWHERE)
 152 #define CONFIG_ENV_SIZE         0x2000
 153 #else
 154 #define CONFIG_ENV_IS_IN_FLASH
 155 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 156 #define CONFIG_ENV_SIZE         0x2000
 157 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 158 #endif
 159
 160 #ifndef __ASSEMBLY__
 161 unsigned long get_board_sys_clk(void);
 162 unsigned long get_board_ddr_clk(void);
 163 #endif
 164
 165 #define CONFIG_SYS_CLK_FREQ     66660000
 166 #define CONFIG_DDR_CLK_FREQ     133330000
 167
 168 /*
 169  * Config the L3 Cache as L3 SRAM
 170  */
 171 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 172 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 173 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 174 #ifdef CONFIG_RAMBOOT_PBL
 175 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 176 #endif
 177 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 178 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 179 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 180 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 181
 182 #define CONFIG_SYS_DCSRBAR      0xf0000000
 183 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 184
 185 /* EEPROM */
 186 #define CONFIG_ID_EEPROM
 187 #define CONFIG_SYS_I2C_EEPROM_NXID
 188 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 191
 192 /*
 193  * DDR Setup
 194  */
 195 #define CONFIG_VERY_BIG_RAM
 196 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 197 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 198 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 199 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 200 #define CONFIG_DDR_SPD
 201 #undef CONFIG_FSL_DDR_INTERACTIVE
 202 #define CONFIG_SYS_SPD_BUS_NUM  0
 203 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 204 #define SPD_EEPROM_ADDRESS1     0x51
 205 #define SPD_EEPROM_ADDRESS2     0x52
 206 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 207 #define CTRL_INTLV_PREFERED     cacheline
 208
 209 /*
 210  * IFC Definitions
 211  */
 212 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 213 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 214 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 215 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 216                                 CSPR_PORT_SIZE_16 | \
 217                                 CSPR_MSEL_NOR | \
 218                                 CSPR_V)
 219 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 220
 221 /* NOR Flash Timing Params */
 222 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 223
 224 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 225                                 FTIM0_NOR_TEADC(0x5) | \
 226                                 FTIM0_NOR_TEAHC(0x5))
 227 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 228                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 229                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 230 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 231                                 FTIM2_NOR_TCH(0x4) | \
 232                                 FTIM2_NOR_TWPH(0x0E) | \
 233                                 FTIM2_NOR_TWP(0x1c))
 234 #define CONFIG_SYS_NOR_FTIM3    0x0
 235
 236 #define CONFIG_SYS_FLASH_QUIET_TEST
 237 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 238
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 240 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 243 #define CONFIG_SYS_FLASH_EMPTY_INFO
 244 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 245
 246 /* CPLD on IFC */
 247 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 248 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 249 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 250 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 251                                 | CSPR_PORT_SIZE_8 \
 252                                 | CSPR_MSEL_GPCM \
 253                                 | CSPR_V)
 254 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 255 #define CONFIG_SYS_CSOR2        0x0
 256
 257 /* CPLD Timing parameters for IFC CS2 */
 258 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 259                                         FTIM0_GPCM_TEADC(0x0e) | \
 260                                         FTIM0_GPCM_TEAHC(0x0e))
 261 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 262                                         FTIM1_GPCM_TRAD(0x1f))
 263 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 264                                         FTIM2_GPCM_TCH(0x8) | \
 265                                         FTIM2_GPCM_TWP(0x1f))
 266 #define CONFIG_SYS_CS2_FTIM3            0x0
 267
 268 /* NAND Flash on IFC */
 269 #define CONFIG_NAND_FSL_IFC
 270 #define CONFIG_SYS_NAND_BASE            0xff800000
 271 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 272
 273 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 274 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 275                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 276                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 277                                 | CSPR_V)
 278 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 279
 280 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 281                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 282                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 283                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 284                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 285                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 286                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 287
 288 #define CONFIG_SYS_NAND_ONFI_DETECTION
 289
 290 /* ONFI NAND Flash mode0 Timing Params */
 291 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 292                                         FTIM0_NAND_TWP(0x18)    | \
 293                                         FTIM0_NAND_TWCHT(0x07)  | \
 294                                         FTIM0_NAND_TWH(0x0a))
 295 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 296                                         FTIM1_NAND_TWBE(0x39)   | \
 297                                         FTIM1_NAND_TRR(0x0e)    | \
 298                                         FTIM1_NAND_TRP(0x18))
 299 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 300                                         FTIM2_NAND_TREH(0x0a)   | \
 301                                         FTIM2_NAND_TWHRE(0x1e))
 302 #define CONFIG_SYS_NAND_FTIM3           0x0
 303
 304 #define CONFIG_SYS_NAND_DDR_LAW         11
 305 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 306 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 307 #define CONFIG_CMD_NAND
 308 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 309
 310 #if defined(CONFIG_NAND)
 311 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 312 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 313 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 314 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 315 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 316 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 317 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 318 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 319 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #else
 328 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 329 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 330 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 331 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 332 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 333 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 334 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 335 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 336 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 337 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 338 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 339 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 340 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 341 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 342 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 343 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 344 #endif
 345
 346 #if defined(CONFIG_RAMBOOT_PBL)
 347 #define CONFIG_SYS_RAMBOOT
 348 #endif
 349
 350 #ifdef CONFIG_SPL_BUILD
 351 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 352 #else
 353 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 354 #endif
 355
 356 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 357 #define CONFIG_MISC_INIT_R
 358 #define CONFIG_HWCONFIG
 359
 360 /* define to use L1 as initial stack */
 361 #define CONFIG_L1_INIT_RAM
 362 #define CONFIG_SYS_INIT_RAM_LOCK
 363 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 364 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 366 /* The assembler doesn't like typecast */
 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 368                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 369                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 370 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 371 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 372                                                 GENERATED_GBL_DATA_SIZE)
 373 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 374 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 375 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 376
 377 /*
 378  * Serial Port
 379  */
 380 #define CONFIG_CONS_INDEX               1
 381 #define CONFIG_SYS_NS16550_SERIAL
 382 #define CONFIG_SYS_NS16550_REG_SIZE     1
 383 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 384 #define CONFIG_SYS_BAUDRATE_TABLE       \
 385         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 386 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 387 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 388 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 389 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 390
 391 /*
 392  * I2C
 393  */
 394 #define CONFIG_SYS_I2C
 395 #define CONFIG_SYS_I2C_FSL
 396 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 397 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 398 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 399 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 400 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 401 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 402 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 403 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 404 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 405 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 406 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 407 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 408 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 409 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 410 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 411 #define I2C_MUX_CH_DEFAULT      0x8
 412
 413 #define I2C_MUX_CH_VOL_MONITOR  0xa
 414
 415 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 416 #ifndef CONFIG_SPL_BUILD
 417 #define CONFIG_VID
 418 #endif
 419 #define CONFIG_VOL_MONITOR_IR36021_SET
 420 #define CONFIG_VOL_MONITOR_IR36021_READ
 421 /* The lowest and highest voltage allowed for T208xRDB */
 422 #define VDD_MV_MIN                      819
 423 #define VDD_MV_MAX                      1212
 424
 425 /*
 426  * RapidIO
 427  */
 428 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 429 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 430 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 431 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 432 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 433 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 434 /*
 435  * for slave u-boot IMAGE instored in master memory space,
 436  * PHYS must be aligned based on the SIZE
 437  */
 438 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 439 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 440 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 441 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 442 /*
 443  * for slave UCODE and ENV instored in master memory space,
 444  * PHYS must be aligned based on the SIZE
 445  */
 446 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 447 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 448 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 449
 450 /* slave core release by master*/
 451 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 452 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 453
 454 /*
 455  * SRIO_PCIE_BOOT - SLAVE
 456  */
 457 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 458 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 459 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 460                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 461 #endif
 462
 463 /*
 464  * eSPI - Enhanced SPI
 465  */
 466 #ifdef CONFIG_SPI_FLASH
 467 #define CONFIG_SPI_FLASH_BAR
 468 #define CONFIG_SF_DEFAULT_SPEED  10000000
 469 #define CONFIG_SF_DEFAULT_MODE    0
 470 #endif
 471
 472 /*
 473  * General PCI
 474  * Memory space is mapped 1-1, but I/O space must start from 0.
 475  */
 476 #define CONFIG_PCIE1            /* PCIE controller 1 */
 477 #define CONFIG_PCIE2            /* PCIE controller 2 */
 478 #define CONFIG_PCIE3            /* PCIE controller 3 */
 479 #define CONFIG_PCIE4            /* PCIE controller 4 */
 480 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 481 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 482 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 483 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 484 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 485 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 486 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 487 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 488 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 489 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 490 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 491
 492 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 493 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 494 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 495 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 496 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 497 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 498 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 499 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 500 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 501
 502 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 503 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 504 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 505 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 506 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 507 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 508 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 509 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 510 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 511
 512 /* controller 4, Base address 203000 */
 513 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 514 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 515 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 516 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 517 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 518 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 519 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 520
 521 #ifdef CONFIG_PCI
 522 #define CONFIG_PCI_INDIRECT_BRIDGE
 523 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 524 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 525 #endif
 526
 527 /* Qman/Bman */
 528 #ifndef CONFIG_NOBQFMAN
 529 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 530 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 531 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 532 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 533 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 534 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 535 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 536 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 537 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 538 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 539                                         CONFIG_SYS_BMAN_CENA_SIZE)
 540 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 541 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 542 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 543 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 544 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 545 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 546 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 547 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 548 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 549 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 550 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 551                                         CONFIG_SYS_QMAN_CENA_SIZE)
 552 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 553 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 554
 555 #define CONFIG_SYS_DPAA_FMAN
 556 #define CONFIG_SYS_DPAA_PME
 557 #define CONFIG_SYS_PMAN
 558 #define CONFIG_SYS_DPAA_DCE
 559 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 560 #define CONFIG_SYS_INTERLAKEN
 561
 562 /* Default address of microcode for the Linux Fman driver */
 563 #if defined(CONFIG_SPIFLASH)
 564 /*
 565  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 566  * env, so we got 0x110000.
 567  */
 568 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 569 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 570 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 571 #define CONFIG_CORTINA_FW_ADDR          0x120000
 572
 573 #elif defined(CONFIG_SDCARD)
 574 /*
 575  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 576  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 577  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 578  */
 579 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 580 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 581 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 582 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 583
 584 #elif defined(CONFIG_NAND)
 585 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 586 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 587 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 588 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 589 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 590 /*
 591  * Slave has no ucode locally, it can fetch this from remote. When implementing
 592  * in two corenet boards, slave's ucode could be stored in master's memory
 593  * space, the address can be mapped from slave TLB->slave LAW->
 594  * slave SRIO or PCIE outbound window->master inbound window->
 595  * master LAW->the ucode address in master's memory space.
 596  */
 597 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 598 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 599 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 600 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 601 #else
 602 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 603 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 604 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 605 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 606 #endif
 607 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 608 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 609 #endif /* CONFIG_NOBQFMAN */
 610
 611 #ifdef CONFIG_SYS_DPAA_FMAN
 612 #define CONFIG_FMAN_ENET
 613 #define CONFIG_PHYLIB_10G
 614 #define CONFIG_PHY_AQUANTIA
 615 #define CONFIG_PHY_CORTINA
 616 #define CONFIG_PHY_REALTEK
 617 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 618 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 619 #define RGMII_PHY2_ADDR         0x02
 620 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 621 #define CORTINA_PHY_ADDR2       0x0d
 622 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 623 #define FM1_10GEC4_PHY_ADDR     0x01
 624 #endif
 625
 626 #ifdef CONFIG_FMAN_ENET
 627 #define CONFIG_MII              /* MII PHY management */
 628 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 629 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 630 #endif
 631
 632 /*
 633  * SATA
 634  */
 635 #ifdef CONFIG_FSL_SATA_V2
 636 #define CONFIG_LIBATA
 637 #define CONFIG_FSL_SATA
 638 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 639 #define CONFIG_SATA1
 640 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 641 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 642 #define CONFIG_SATA2
 643 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 644 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 645 #define CONFIG_LBA48
 646 #endif
 647
 648 /*
 649  * USB
 650  */
 651 #ifdef CONFIG_USB_EHCI_HCD
 652 #define CONFIG_USB_EHCI_FSL
 653 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 654 #define CONFIG_HAS_FSL_DR_USB
 655 #endif
 656
 657 /*
 658  * SDHC
 659  */
 660 #ifdef CONFIG_MMC
 661 #define CONFIG_FSL_ESDHC
 662 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 663 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 664 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 665 #endif
 666
 667 /*
 668  * Dynamic MTD Partition support with mtdparts
 669  */
 670 #ifdef CONFIG_MTD_NOR_FLASH
 671 #define CONFIG_MTD_DEVICE
 672 #define CONFIG_MTD_PARTITIONS
 673 #define CONFIG_FLASH_CFI_MTD
 674 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 675                         "spi0=spife110000.1"
 676 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 677                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 678                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
 679                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 680 #endif
 681
 682 /*
 683  * Environment
 684  */
 685
 686 /*
 687  * Command line configuration.
 688  */
 689 #define CONFIG_CMD_REGINFO
 690
 691 #ifdef CONFIG_PCI
 692 #define CONFIG_CMD_PCI
 693 #endif
 694
 695 /*
 696  * Miscellaneous configurable options
 697  */
 698 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 699 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 700 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 701 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 702 #ifdef CONFIG_CMD_KGDB
 703 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 704 #else
 705 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 706 #endif
 707 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 708 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 709 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 710
 711 /*
 712  * For booting Linux, the board info and command line data
 713  * have to be in the first 64 MB of memory, since this is
 714  * the maximum mapped by the Linux kernel during initialization.
 715  */
 716 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 717 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 718
 719 #ifdef CONFIG_CMD_KGDB
 720 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 721 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 722 #endif
 723
 724 /*
 725  * Environment Configuration
 726  */
 727 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 728 #define CONFIG_BOOTFILE  "uImage"
 729 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 730
 731 /* default location for tftp and bootm */
 732 #define CONFIG_LOADADDR         1000000
 733 #define __USB_PHY_TYPE          utmi
 734
 735 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 736         "hwconfig=fsl_ddr:"                                     \
 737         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 738         "bank_intlv=auto;"                                      \
 739         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 740         "netdev=eth0\0"                                         \
 741         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 742         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 743         "tftpflash=tftpboot $loadaddr $uboot && "               \
 744         "protect off $ubootaddr +$filesize && "                 \
 745         "erase $ubootaddr +$filesize && "                       \
 746         "cp.b $loadaddr $ubootaddr $filesize && "               \
 747         "protect on $ubootaddr +$filesize && "                  \
 748         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 749         "consoledev=ttyS0\0"                                    \
 750         "ramdiskaddr=2000000\0"                                 \
 751         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 752         "fdtaddr=1e00000\0"                                     \
 753         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 754         "bdev=sda3\0"
 755
 756 /*
 757  * For emulation this causes u-boot to jump to the start of the
 758  * proof point app code automatically
 759  */
 760 #define CONFIG_PROOF_POINTS                             \
 761         "setenv bootargs root=/dev/$bdev rw "           \
 762         "console=$consoledev,$baudrate $othbootargs;"   \
 763         "cpu 1 release 0x29000000 - - -;"               \
 764         "cpu 2 release 0x29000000 - - -;"               \
 765         "cpu 3 release 0x29000000 - - -;"               \
 766         "cpu 4 release 0x29000000 - - -;"               \
 767         "cpu 5 release 0x29000000 - - -;"               \
 768         "cpu 6 release 0x29000000 - - -;"               \
 769         "cpu 7 release 0x29000000 - - -;"               \
 770         "go 0x29000000"
 771
 772 #define CONFIG_HVBOOT                           \
 773         "setenv bootargs config-addr=0x60000000; "      \
 774         "bootm 0x01000000 - 0x00f00000"
 775
 776 #define CONFIG_ALU                              \
 777         "setenv bootargs root=/dev/$bdev rw "           \
 778         "console=$consoledev,$baudrate $othbootargs;"   \
 779         "cpu 1 release 0x01000000 - - -;"               \
 780         "cpu 2 release 0x01000000 - - -;"               \
 781         "cpu 3 release 0x01000000 - - -;"               \
 782         "cpu 4 release 0x01000000 - - -;"               \
 783         "cpu 5 release 0x01000000 - - -;"               \
 784         "cpu 6 release 0x01000000 - - -;"               \
 785         "cpu 7 release 0x01000000 - - -;"               \
 786         "go 0x01000000"
 787
 788 #define CONFIG_LINUX                            \
 789         "setenv bootargs root=/dev/ram rw "             \
 790         "console=$consoledev,$baudrate $othbootargs;"   \
 791         "setenv ramdiskaddr 0x02000000;"                \
 792         "setenv fdtaddr 0x00c00000;"                    \
 793         "setenv loadaddr 0x1000000;"                    \
 794         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 795
 796 #define CONFIG_HDBOOT                                   \
 797         "setenv bootargs root=/dev/$bdev rw "           \
 798         "console=$consoledev,$baudrate $othbootargs;"   \
 799         "tftp $loadaddr $bootfile;"                     \
 800         "tftp $fdtaddr $fdtfile;"                       \
 801         "bootm $loadaddr - $fdtaddr"
 802
 803 #define CONFIG_NFSBOOTCOMMAND                   \
 804         "setenv bootargs root=/dev/nfs rw "     \
 805         "nfsroot=$serverip:$rootpath "          \
 806         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 807         "console=$consoledev,$baudrate $othbootargs;"   \
 808         "tftp $loadaddr $bootfile;"             \
 809         "tftp $fdtaddr $fdtfile;"               \
 810         "bootm $loadaddr - $fdtaddr"
 811
 812 #define CONFIG_RAMBOOTCOMMAND                           \
 813         "setenv bootargs root=/dev/ram rw "             \
 814         "console=$consoledev,$baudrate $othbootargs;"   \
 815         "tftp $ramdiskaddr $ramdiskfile;"               \
 816         "tftp $loadaddr $bootfile;"                     \
 817         "tftp $fdtaddr $fdtfile;"                       \
 818         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 819
 820 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 821
 822 #include <asm/fsl_secure_boot.h>
 823
 824 #endif  /* __T2080RDB_H */