include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_COMMON_INIT_DDR
  36 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  37 #endif
  38
  39 #ifdef CONFIG_MTD_RAW_NAND
  40 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  43 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  45 #endif
  46 #endif
  47
  48 #ifdef CONFIG_SPIFLASH
  49 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  55 #ifndef CONFIG_SPL_BUILD
  56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  57 #endif
  58 #endif
  59
  60 #ifdef CONFIG_SDCARD
  61 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  62 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  63 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  64 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  65 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68 #endif
  69 #endif
  70
  71 #endif /* CONFIG_RAMBOOT_PBL */
  72
  73 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  74 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  75 /* Set 1M boot space */
  76 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  77 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  78                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  79 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  80 #endif
  81
  82 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  83 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  84 #endif
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #ifdef CONFIG_DDR_ECC
  91 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  92 #endif
  93
  94 /*
  95  * Config the L3 Cache as L3 SRAM
  96  */
  97 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  98 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  99 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 100 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 101 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 102 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 103 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 104
 105 #define CONFIG_SYS_DCSRBAR      0xf0000000
 106 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 107
 108 /* EEPROM */
 109 #define CONFIG_SYS_I2C_EEPROM_NXID
 110 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 111
 112 /*
 113  * DDR Setup
 114  */
 115 #define CONFIG_VERY_BIG_RAM
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118 #define CONFIG_SYS_SPD_BUS_NUM  0
 119 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 120 #define SPD_EEPROM_ADDRESS1     0x51
 121 #define SPD_EEPROM_ADDRESS2     0x52
 122 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 123 #define CTRL_INTLV_PREFERED     cacheline
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 129 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 130 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 131 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 132                                 + 0x8000000) | \
 133                                 CSPR_PORT_SIZE_16 | \
 134                                 CSPR_MSEL_NOR | \
 135                                 CSPR_V)
 136 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 137 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 138                                 CSPR_PORT_SIZE_16 | \
 139                                 CSPR_MSEL_NOR | \
 140                                 CSPR_V)
 141 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 142 /* NOR Flash Timing Params */
 143 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 144
 145 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 146                                 FTIM0_NOR_TEADC(0x5) | \
 147                                 FTIM0_NOR_TEAHC(0x5))
 148 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 149                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 150                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 151 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 152                                 FTIM2_NOR_TCH(0x4) | \
 153                                 FTIM2_NOR_TWPH(0x0E) | \
 154                                 FTIM2_NOR_TWP(0x1c))
 155 #define CONFIG_SYS_NOR_FTIM3    0x0
 156
 157 #define CONFIG_SYS_FLASH_QUIET_TEST
 158 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 159
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 166                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 167
 168 #define QIXIS_BASE                      0xffdf0000
 169 #define QIXIS_LBMAP_SWITCH              6
 170 #define QIXIS_LBMAP_MASK                0x0f
 171 #define QIXIS_LBMAP_SHIFT               0
 172 #define QIXIS_LBMAP_DFLTBANK            0x00
 173 #define QIXIS_LBMAP_ALTBANK             0x04
 174 #define QIXIS_LBMAP_NAND                0x09
 175 #define QIXIS_LBMAP_SD                  0x00
 176 #define QIXIS_RCW_SRC_NAND              0x104
 177 #define QIXIS_RCW_SRC_SD                0x040
 178 #define QIXIS_RST_CTL_RESET             0x83
 179 #define QIXIS_RST_FORCE_MEM             0x1
 180 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 181 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 182 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 183 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 184
 185 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 186 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 187                                 | CSPR_PORT_SIZE_8 \
 188                                 | CSPR_MSEL_GPCM \
 189                                 | CSPR_V)
 190 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 191 #define CONFIG_SYS_CSOR3        0x0
 192 /* QIXIS Timing parameters for IFC CS3 */
 193 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 194                                         FTIM0_GPCM_TEADC(0x0e) | \
 195                                         FTIM0_GPCM_TEAHC(0x0e))
 196 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 197                                         FTIM1_GPCM_TRAD(0x3f))
 198 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 199                                         FTIM2_GPCM_TCH(0x8) | \
 200                                         FTIM2_GPCM_TWP(0x1f))
 201 #define CONFIG_SYS_CS3_FTIM3            0x0
 202
 203 /* NAND Flash on IFC */
 204 #define CONFIG_SYS_NAND_BASE            0xff800000
 205 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 206
 207 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 209                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 210                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 211                                 | CSPR_V)
 212 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 213
 214 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 215                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 216                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 217                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 218                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 219                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 220                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 221
 222 /* ONFI NAND Flash mode0 Timing Params */
 223 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 224                                         FTIM0_NAND_TWP(0x18)    | \
 225                                         FTIM0_NAND_TWCHT(0x07)  | \
 226                                         FTIM0_NAND_TWH(0x0a))
 227 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 228                                         FTIM1_NAND_TWBE(0x39)   | \
 229                                         FTIM1_NAND_TRR(0x0e)    | \
 230                                         FTIM1_NAND_TRP(0x18))
 231 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 232                                         FTIM2_NAND_TREH(0x0a)   | \
 233                                         FTIM2_NAND_TWHRE(0x1e))
 234 #define CONFIG_SYS_NAND_FTIM3           0x0
 235
 236 #define CONFIG_SYS_NAND_DDR_LAW         11
 237 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 238 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 239
 240 #if defined(CONFIG_MTD_RAW_NAND)
 241 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 242 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 243 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 244 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 245 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 246 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 247 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 248 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 249 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 250 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 251 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 258 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 259 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 260 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 261 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 262 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 263 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 264 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 265 #else
 266 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 267 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 268 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 269 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 270 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 271 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 272 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 273 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 274 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 275 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 276 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 277 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 278 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 279 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 280 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 281 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 282 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 283 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 284 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 285 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 286 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 287 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 288 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 289 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 290 #endif
 291
 292 #if defined(CONFIG_RAMBOOT_PBL)
 293 #define CONFIG_SYS_RAMBOOT
 294 #endif
 295
 296 #define CONFIG_HWCONFIG
 297
 298 /* define to use L1 as initial stack */
 299 #define CONFIG_L1_INIT_RAM
 300 #define CONFIG_SYS_INIT_RAM_LOCK
 301 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 304 /* The assembler doesn't like typecast */
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 306                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 307                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 308 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 309 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 310                                                 GENERATED_GBL_DATA_SIZE)
 311 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 312 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 313
 314 /*
 315  * Serial Port
 316  */
 317 #define CONFIG_SYS_NS16550_SERIAL
 318 #define CONFIG_SYS_NS16550_REG_SIZE     1
 319 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 320 #define CONFIG_SYS_BAUDRATE_TABLE       \
 321         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 324 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 325 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 326
 327 /*
 328  * I2C
 329  */
 330
 331 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 332 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 333 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 334 #define I2C_MUX_CH_DEFAULT      0x8
 335
 336 #define I2C_MUX_CH_VOL_MONITOR 0xa
 337
 338 /* Voltage monitor on channel 2*/
 339 #define I2C_VOL_MONITOR_ADDR           0x40
 340 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 341 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 342 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 343
 344 /* The lowest and highest voltage allowed for T208xQDS */
 345 #define VDD_MV_MIN                      819
 346 #define VDD_MV_MAX                      1212
 347
 348 /*
 349  * RapidIO
 350  */
 351 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 352 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 353 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 354 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 355 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 356 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 357 /*
 358  * for slave u-boot IMAGE instored in master memory space,
 359  * PHYS must be aligned based on the SIZE
 360  */
 361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 362 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 363 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 364 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 365 /*
 366  * for slave UCODE and ENV instored in master memory space,
 367  * PHYS must be aligned based on the SIZE
 368  */
 369 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 370 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 371 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 372
 373 /* slave core release by master*/
 374 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 375 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 376
 377 /*
 378  * SRIO_PCIE_BOOT - SLAVE
 379  */
 380 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 381 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 382 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 383                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 384 #endif
 385
 386 /*
 387  * eSPI - Enhanced SPI
 388  */
 389
 390 /*
 391  * General PCI
 392  * Memory space is mapped 1-1, but I/O space must start from 0.
 393  */
 394 #define CONFIG_PCIE1            /* PCIE controller 1 */
 395 #define CONFIG_PCIE2            /* PCIE controller 2 */
 396 #define CONFIG_PCIE3            /* PCIE controller 3 */
 397 #define CONFIG_PCIE4            /* PCIE controller 4 */
 398 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 399 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 400 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 401 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 402 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 403
 404 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 405 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 406 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 407 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 408 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 409
 410 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 411 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 412 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 413 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 414 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 415
 416 /* controller 4, Base address 203000 */
 417 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 418 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 419 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 420
 421 #ifdef CONFIG_PCI
 422 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 423 #endif
 424
 425 /* Qman/Bman */
 426 #ifndef CONFIG_NOBQFMAN
 427 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 428 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 429 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 430 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 431 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 432 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 433 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 434 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 435 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 436                                         CONFIG_SYS_BMAN_CENA_SIZE)
 437 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 438 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 439 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 440 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 441 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 442 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 443 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 444 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 445 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 446 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 447 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 448                                         CONFIG_SYS_QMAN_CENA_SIZE)
 449 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 450 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 451
 452 #define CONFIG_SYS_DPAA_FMAN
 453 #define CONFIG_SYS_DPAA_PME
 454 #define CONFIG_SYS_PMAN
 455 #define CONFIG_SYS_DPAA_DCE
 456 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 457 #define CONFIG_SYS_INTERLAKEN
 458
 459 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 460 #endif /* CONFIG_NOBQFMAN */
 461
 462 #ifdef CONFIG_SYS_DPAA_FMAN
 463 #define RGMII_PHY1_ADDR 0x1
 464 #define RGMII_PHY2_ADDR 0x2
 465 #define FM1_10GEC1_PHY_ADDR       0x3
 466 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 467 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 468 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 469 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 470 #endif
 471
 472 /*
 473  * SATA
 474  */
 475 #ifdef CONFIG_FSL_SATA_V2
 476 #define CONFIG_SATA1
 477 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 478 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 479 #define CONFIG_SATA2
 480 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 481 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 482 #define CONFIG_LBA48
 483 #endif
 484
 485 /*
 486  * USB
 487  */
 488 #ifdef CONFIG_USB_EHCI_HCD
 489 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 490 #define CONFIG_HAS_FSL_DR_USB
 491 #endif
 492
 493 /*
 494  * SDHC
 495  */
 496 #ifdef CONFIG_MMC
 497 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 498 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 499 #endif
 500
 501 /*
 502  * Dynamic MTD Partition support with mtdparts
 503  */
 504
 505 /*
 506  * Environment
 507  */
 508 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 509 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 510
 511 /*
 512  * Miscellaneous configurable options
 513  */
 514
 515 /*
 516  * For booting Linux, the board info and command line data
 517  * have to be in the first 64 MB of memory, since this is
 518  * the maximum mapped by the Linux kernel during initialization.
 519  */
 520 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 521 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 522
 523 /*
 524  * Environment Configuration
 525  */
 526 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 527 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 528
 529 #define __USB_PHY_TYPE          utmi
 530
 531 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 532         "hwconfig=fsl_ddr:"                                     \
 533         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 534         "bank_intlv=auto;"                                      \
 535         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 536         "netdev=eth0\0"                                         \
 537         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 538         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 539         "tftpflash=tftpboot $loadaddr $uboot && "               \
 540         "protect off $ubootaddr +$filesize && "                 \
 541         "erase $ubootaddr +$filesize && "                       \
 542         "cp.b $loadaddr $ubootaddr $filesize && "               \
 543         "protect on $ubootaddr +$filesize && "                  \
 544         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 545         "consoledev=ttyS0\0"                                    \
 546         "ramdiskaddr=2000000\0"                                 \
 547         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 548         "fdtaddr=1e00000\0"                                     \
 549         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 550         "bdev=sda3\0"
 551
 552 /*
 553  * For emulation this causes u-boot to jump to the start of the
 554  * proof point app code automatically
 555  */
 556 #define PROOF_POINTS                            \
 557         "setenv bootargs root=/dev/$bdev rw "           \
 558         "console=$consoledev,$baudrate $othbootargs;"   \
 559         "cpu 1 release 0x29000000 - - -;"               \
 560         "cpu 2 release 0x29000000 - - -;"               \
 561         "cpu 3 release 0x29000000 - - -;"               \
 562         "cpu 4 release 0x29000000 - - -;"               \
 563         "cpu 5 release 0x29000000 - - -;"               \
 564         "cpu 6 release 0x29000000 - - -;"               \
 565         "cpu 7 release 0x29000000 - - -;"               \
 566         "go 0x29000000"
 567
 568 #define HVBOOT                          \
 569         "setenv bootargs config-addr=0x60000000; "      \
 570         "bootm 0x01000000 - 0x00f00000"
 571
 572 #define ALU                             \
 573         "setenv bootargs root=/dev/$bdev rw "           \
 574         "console=$consoledev,$baudrate $othbootargs;"   \
 575         "cpu 1 release 0x01000000 - - -;"               \
 576         "cpu 2 release 0x01000000 - - -;"               \
 577         "cpu 3 release 0x01000000 - - -;"               \
 578         "cpu 4 release 0x01000000 - - -;"               \
 579         "cpu 5 release 0x01000000 - - -;"               \
 580         "cpu 6 release 0x01000000 - - -;"               \
 581         "cpu 7 release 0x01000000 - - -;"               \
 582         "go 0x01000000"
 583
 584 #include <asm/fsl_secure_boot.h>
 585
 586 #endif  /* __T208xQDS_H */