include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  19 #define CONFIG_SRIO1            /* SRIO port 1 */
  20 #define CONFIG_SRIO2            /* SRIO port 2 */
  21 #endif
  22
  23 /* High Level Configuration Options */
  24
  25 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #ifdef CONFIG_RAMBOOT_PBL
  28 #define RESET_VECTOR_OFFSET             0x27FFC
  29 #define BOOT_PAGE_OFFSET                0x27000
  30
  31 #ifdef CONFIG_MTD_RAW_NAND
  32 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  35 #endif
  36
  37 #ifdef CONFIG_SPIFLASH
  38 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  43 #endif
  44
  45 #ifdef CONFIG_SDCARD
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  47 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  48 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  49 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  50 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  51 #endif
  52
  53 #endif /* CONFIG_RAMBOOT_PBL */
  54
  55 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  56 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  57 /* Set 1M boot space */
  58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  60                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  61 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #ifdef CONFIG_DDR_ECC
  72 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  73 #endif
  74
  75 /*
  76  * Config the L3 Cache as L3 SRAM
  77  */
  78 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  79 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  80 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  81
  82 #define CONFIG_SYS_DCSRBAR      0xf0000000
  83 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  84
  85 /* EEPROM */
  86 #define CONFIG_SYS_I2C_EEPROM_NXID
  87 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  88
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_VERY_BIG_RAM
  93 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  94 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  95 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  96 #define SPD_EEPROM_ADDRESS1     0x51
  97 #define SPD_EEPROM_ADDRESS2     0x52
  98 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  99 #define CTRL_INTLV_PREFERED     cacheline
 100
 101 /*
 102  * IFC Definitions
 103  */
 104 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 105 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 106 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 107 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 108                                 + 0x8000000) | \
 109                                 CSPR_PORT_SIZE_16 | \
 110                                 CSPR_MSEL_NOR | \
 111                                 CSPR_V)
 112 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 113 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 114                                 CSPR_PORT_SIZE_16 | \
 115                                 CSPR_MSEL_NOR | \
 116                                 CSPR_V)
 117 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 118 /* NOR Flash Timing Params */
 119 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 120
 121 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 122                                 FTIM0_NOR_TEADC(0x5) | \
 123                                 FTIM0_NOR_TEAHC(0x5))
 124 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 125                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 126                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 127 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 128                                 FTIM2_NOR_TCH(0x4) | \
 129                                 FTIM2_NOR_TWPH(0x0E) | \
 130                                 FTIM2_NOR_TWP(0x1c))
 131 #define CONFIG_SYS_NOR_FTIM3    0x0
 132
 133 #define CONFIG_SYS_FLASH_QUIET_TEST
 134 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 135
 136 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 137 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 138 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 139
 140 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 141                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 142
 143 #define QIXIS_BASE                      0xffdf0000
 144 #define QIXIS_LBMAP_SWITCH              6
 145 #define QIXIS_LBMAP_MASK                0x0f
 146 #define QIXIS_LBMAP_SHIFT               0
 147 #define QIXIS_LBMAP_DFLTBANK            0x00
 148 #define QIXIS_LBMAP_ALTBANK             0x04
 149 #define QIXIS_LBMAP_NAND                0x09
 150 #define QIXIS_LBMAP_SD                  0x00
 151 #define QIXIS_RCW_SRC_NAND              0x104
 152 #define QIXIS_RCW_SRC_SD                0x040
 153 #define QIXIS_RST_CTL_RESET             0x83
 154 #define QIXIS_RST_FORCE_MEM             0x1
 155 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 156 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 157 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 158 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 159
 160 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 161 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8 \
 163                                 | CSPR_MSEL_GPCM \
 164                                 | CSPR_V)
 165 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 166 #define CONFIG_SYS_CSOR3        0x0
 167 /* QIXIS Timing parameters for IFC CS3 */
 168 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 169                                         FTIM0_GPCM_TEADC(0x0e) | \
 170                                         FTIM0_GPCM_TEAHC(0x0e))
 171 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 172                                         FTIM1_GPCM_TRAD(0x3f))
 173 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 174                                         FTIM2_GPCM_TCH(0x8) | \
 175                                         FTIM2_GPCM_TWP(0x1f))
 176 #define CONFIG_SYS_CS3_FTIM3            0x0
 177
 178 /* NAND Flash on IFC */
 179 #define CONFIG_SYS_NAND_BASE            0xff800000
 180 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 181
 182 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 183 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 184                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 185                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 186                                 | CSPR_V)
 187 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 188
 189 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 190                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 191                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 192                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 193                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 194                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 195                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 196
 197 /* ONFI NAND Flash mode0 Timing Params */
 198 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 199                                         FTIM0_NAND_TWP(0x18)    | \
 200                                         FTIM0_NAND_TWCHT(0x07)  | \
 201                                         FTIM0_NAND_TWH(0x0a))
 202 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 203                                         FTIM1_NAND_TWBE(0x39)   | \
 204                                         FTIM1_NAND_TRR(0x0e)    | \
 205                                         FTIM1_NAND_TRP(0x18))
 206 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 207                                         FTIM2_NAND_TREH(0x0a)   | \
 208                                         FTIM2_NAND_TWHRE(0x1e))
 209 #define CONFIG_SYS_NAND_FTIM3           0x0
 210
 211 #define CONFIG_SYS_NAND_DDR_LAW         11
 212 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 213 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 214
 215 #if defined(CONFIG_MTD_RAW_NAND)
 216 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 217 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 218 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 219 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 220 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 221 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 222 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 223 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 224 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 225 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 226 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 227 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 228 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 229 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 230 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 231 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 232 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 233 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 234 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 235 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 236 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 237 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 238 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 239 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 240 #else
 241 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 242 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 243 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 244 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 245 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 246 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 247 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 248 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 249 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 250 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 251 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 258 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 259 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 260 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 261 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 262 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 263 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 264 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 265 #endif
 266
 267 #define CONFIG_HWCONFIG
 268
 269 /* define to use L1 as initial stack */
 270 #define CONFIG_L1_INIT_RAM
 271 #define CONFIG_SYS_INIT_RAM_LOCK
 272 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 275 /* The assembler doesn't like typecast */
 276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 277                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 278                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 279 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 280 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 281 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 282
 283 /*
 284  * Serial Port
 285  */
 286 #define CONFIG_SYS_NS16550_SERIAL
 287 #define CONFIG_SYS_NS16550_REG_SIZE     1
 288 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 289 #define CONFIG_SYS_BAUDRATE_TABLE       \
 290         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 293 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 294 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 295
 296 /*
 297  * I2C
 298  */
 299
 300 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 301 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 302 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 303 #define I2C_MUX_CH_DEFAULT      0x8
 304
 305 #define I2C_MUX_CH_VOL_MONITOR 0xa
 306
 307 /* Voltage monitor on channel 2*/
 308 #define I2C_VOL_MONITOR_ADDR           0x40
 309 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 310 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 311 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 312
 313 /* The lowest and highest voltage allowed for T208xQDS */
 314 #define VDD_MV_MIN                      819
 315 #define VDD_MV_MAX                      1212
 316
 317 /*
 318  * RapidIO
 319  */
 320 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 321 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 322 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 323 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 324 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 325 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 326 /*
 327  * for slave u-boot IMAGE instored in master memory space,
 328  * PHYS must be aligned based on the SIZE
 329  */
 330 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 334 /*
 335  * for slave UCODE and ENV instored in master memory space,
 336  * PHYS must be aligned based on the SIZE
 337  */
 338 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 339 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 340 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 341
 342 /* slave core release by master*/
 343 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 344 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 345
 346 /*
 347  * SRIO_PCIE_BOOT - SLAVE
 348  */
 349 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 350 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 351 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 352                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 353 #endif
 354
 355 /*
 356  * eSPI - Enhanced SPI
 357  */
 358
 359 /*
 360  * General PCI
 361  * Memory space is mapped 1-1, but I/O space must start from 0.
 362  */
 363 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 364 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 365 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 366 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 367 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 368
 369 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 370 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 371 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 372 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 373 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 374
 375 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 376 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 377 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 378 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 379 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 380
 381 /* controller 4, Base address 203000 */
 382 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 383 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 384 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 385
 386 /* Qman/Bman */
 387 #ifndef CONFIG_NOBQFMAN
 388 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 389 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 390 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 391 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 392 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 393 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 394 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 395 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 396 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 397                                         CONFIG_SYS_BMAN_CENA_SIZE)
 398 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 399 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 400 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 401 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 402 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 403 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 404 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 405 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 406 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 407 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 408 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 409                                         CONFIG_SYS_QMAN_CENA_SIZE)
 410 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 411 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 412
 413 #define CONFIG_SYS_DPAA_FMAN
 414 #define CONFIG_SYS_DPAA_PME
 415 #define CONFIG_SYS_PMAN
 416 #define CONFIG_SYS_DPAA_DCE
 417 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 418 #define CONFIG_SYS_INTERLAKEN
 419
 420 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 421 #endif /* CONFIG_NOBQFMAN */
 422
 423 #ifdef CONFIG_SYS_DPAA_FMAN
 424 #define RGMII_PHY1_ADDR 0x1
 425 #define RGMII_PHY2_ADDR 0x2
 426 #define FM1_10GEC1_PHY_ADDR       0x3
 427 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 428 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 429 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 430 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 431 #endif
 432
 433 /*
 434  * USB
 435  */
 436
 437 /*
 438  * SDHC
 439  */
 440 #ifdef CONFIG_MMC
 441 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 442 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 443 #endif
 444
 445 /*
 446  * Dynamic MTD Partition support with mtdparts
 447  */
 448
 449 /*
 450  * Environment
 451  */
 452 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 454
 455 /*
 456  * Miscellaneous configurable options
 457  */
 458
 459 /*
 460  * For booting Linux, the board info and command line data
 461  * have to be in the first 64 MB of memory, since this is
 462  * the maximum mapped by the Linux kernel during initialization.
 463  */
 464 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 465
 466 /*
 467  * Environment Configuration
 468  */
 469 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 470 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 471
 472 #define __USB_PHY_TYPE          utmi
 473
 474 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 475         "hwconfig=fsl_ddr:"                                     \
 476         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 477         "bank_intlv=auto;"                                      \
 478         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 479         "netdev=eth0\0"                                         \
 480         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 481         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 482         "tftpflash=tftpboot $loadaddr $uboot && "               \
 483         "protect off $ubootaddr +$filesize && "                 \
 484         "erase $ubootaddr +$filesize && "                       \
 485         "cp.b $loadaddr $ubootaddr $filesize && "               \
 486         "protect on $ubootaddr +$filesize && "                  \
 487         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 488         "consoledev=ttyS0\0"                                    \
 489         "ramdiskaddr=2000000\0"                                 \
 490         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 491         "fdtaddr=1e00000\0"                                     \
 492         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 493         "bdev=sda3\0"
 494
 495 /*
 496  * For emulation this causes u-boot to jump to the start of the
 497  * proof point app code automatically
 498  */
 499 #define PROOF_POINTS                            \
 500         "setenv bootargs root=/dev/$bdev rw "           \
 501         "console=$consoledev,$baudrate $othbootargs;"   \
 502         "cpu 1 release 0x29000000 - - -;"               \
 503         "cpu 2 release 0x29000000 - - -;"               \
 504         "cpu 3 release 0x29000000 - - -;"               \
 505         "cpu 4 release 0x29000000 - - -;"               \
 506         "cpu 5 release 0x29000000 - - -;"               \
 507         "cpu 6 release 0x29000000 - - -;"               \
 508         "cpu 7 release 0x29000000 - - -;"               \
 509         "go 0x29000000"
 510
 511 #define HVBOOT                          \
 512         "setenv bootargs config-addr=0x60000000; "      \
 513         "bootm 0x01000000 - 0x00f00000"
 514
 515 #define ALU                             \
 516         "setenv bootargs root=/dev/$bdev rw "           \
 517         "console=$consoledev,$baudrate $othbootargs;"   \
 518         "cpu 1 release 0x01000000 - - -;"               \
 519         "cpu 2 release 0x01000000 - - -;"               \
 520         "cpu 3 release 0x01000000 - - -;"               \
 521         "cpu 4 release 0x01000000 - - -;"               \
 522         "cpu 5 release 0x01000000 - - -;"               \
 523         "cpu 6 release 0x01000000 - - -;"               \
 524         "cpu 7 release 0x01000000 - - -;"               \
 525         "go 0x01000000"
 526
 527 #include <asm/fsl_secure_boot.h>
 528
 529 #endif  /* __T208xQDS_H */