include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  19 #define CONFIG_SRIO1            /* SRIO port 1 */
  20 #define CONFIG_SRIO2            /* SRIO port 2 */
  21 #endif
  22
  23 /* High Level Configuration Options */
  24
  25 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #ifdef CONFIG_RAMBOOT_PBL
  28 #define RESET_VECTOR_OFFSET             0x27FFC
  29 #define BOOT_PAGE_OFFSET                0x27000
  30
  31 #ifdef CONFIG_MTD_RAW_NAND
  32 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  35 #endif
  36
  37 #ifdef CONFIG_SPIFLASH
  38 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  43 #endif
  44
  45 #ifdef CONFIG_SDCARD
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  47 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  48 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  49 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  50 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  51 #endif
  52
  53 #endif /* CONFIG_RAMBOOT_PBL */
  54
  55 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  56 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  57 /* Set 1M boot space */
  58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  60                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  61 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #define CONFIG_SYS_CACHE_STASHING
  72 #ifdef CONFIG_DDR_ECC
  73 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  74 #endif
  75
  76 /*
  77  * Config the L3 Cache as L3 SRAM
  78  */
  79 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  80 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  81 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  82
  83 #define CONFIG_SYS_DCSRBAR      0xf0000000
  84 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  85
  86 /* EEPROM */
  87 #define CONFIG_SYS_I2C_EEPROM_NXID
  88 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  89
  90 /*
  91  * DDR Setup
  92  */
  93 #define CONFIG_VERY_BIG_RAM
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  97 #define SPD_EEPROM_ADDRESS1     0x51
  98 #define SPD_EEPROM_ADDRESS2     0x52
  99 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 100 #define CTRL_INTLV_PREFERED     cacheline
 101
 102 /*
 103  * IFC Definitions
 104  */
 105 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 106 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 107 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 108 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 109                                 + 0x8000000) | \
 110                                 CSPR_PORT_SIZE_16 | \
 111                                 CSPR_MSEL_NOR | \
 112                                 CSPR_V)
 113 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 114 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 115                                 CSPR_PORT_SIZE_16 | \
 116                                 CSPR_MSEL_NOR | \
 117                                 CSPR_V)
 118 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 119 /* NOR Flash Timing Params */
 120 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 121
 122 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 123                                 FTIM0_NOR_TEADC(0x5) | \
 124                                 FTIM0_NOR_TEAHC(0x5))
 125 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 126                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 127                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 128 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 129                                 FTIM2_NOR_TCH(0x4) | \
 130                                 FTIM2_NOR_TWPH(0x0E) | \
 131                                 FTIM2_NOR_TWP(0x1c))
 132 #define CONFIG_SYS_NOR_FTIM3    0x0
 133
 134 #define CONFIG_SYS_FLASH_QUIET_TEST
 135 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 136
 137 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 140
 141 #define CONFIG_SYS_FLASH_EMPTY_INFO
 142 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 143                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 144
 145 #define QIXIS_BASE                      0xffdf0000
 146 #define QIXIS_LBMAP_SWITCH              6
 147 #define QIXIS_LBMAP_MASK                0x0f
 148 #define QIXIS_LBMAP_SHIFT               0
 149 #define QIXIS_LBMAP_DFLTBANK            0x00
 150 #define QIXIS_LBMAP_ALTBANK             0x04
 151 #define QIXIS_LBMAP_NAND                0x09
 152 #define QIXIS_LBMAP_SD                  0x00
 153 #define QIXIS_RCW_SRC_NAND              0x104
 154 #define QIXIS_RCW_SRC_SD                0x040
 155 #define QIXIS_RST_CTL_RESET             0x83
 156 #define QIXIS_RST_FORCE_MEM             0x1
 157 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 158 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 159 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 160 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 161
 162 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 163 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 164                                 | CSPR_PORT_SIZE_8 \
 165                                 | CSPR_MSEL_GPCM \
 166                                 | CSPR_V)
 167 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 168 #define CONFIG_SYS_CSOR3        0x0
 169 /* QIXIS Timing parameters for IFC CS3 */
 170 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 171                                         FTIM0_GPCM_TEADC(0x0e) | \
 172                                         FTIM0_GPCM_TEAHC(0x0e))
 173 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 174                                         FTIM1_GPCM_TRAD(0x3f))
 175 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 176                                         FTIM2_GPCM_TCH(0x8) | \
 177                                         FTIM2_GPCM_TWP(0x1f))
 178 #define CONFIG_SYS_CS3_FTIM3            0x0
 179
 180 /* NAND Flash on IFC */
 181 #define CONFIG_SYS_NAND_BASE            0xff800000
 182 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 183
 184 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 185 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 186                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 187                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 190
 191 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 192                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 193                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 194                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 195                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 196                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 197                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 198
 199 /* ONFI NAND Flash mode0 Timing Params */
 200 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 201                                         FTIM0_NAND_TWP(0x18)    | \
 202                                         FTIM0_NAND_TWCHT(0x07)  | \
 203                                         FTIM0_NAND_TWH(0x0a))
 204 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 205                                         FTIM1_NAND_TWBE(0x39)   | \
 206                                         FTIM1_NAND_TRR(0x0e)    | \
 207                                         FTIM1_NAND_TRP(0x18))
 208 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 209                                         FTIM2_NAND_TREH(0x0a)   | \
 210                                         FTIM2_NAND_TWHRE(0x1e))
 211 #define CONFIG_SYS_NAND_FTIM3           0x0
 212
 213 #define CONFIG_SYS_NAND_DDR_LAW         11
 214 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216
 217 #if defined(CONFIG_MTD_RAW_NAND)
 218 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 219 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 220 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 221 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 222 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 223 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 224 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 225 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 226 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 227 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 228 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 235 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 236 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 237 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 238 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 239 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 240 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 241 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 242 #else
 243 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 244 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 245 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 246 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 247 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 248 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 249 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 250 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 251 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 252 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 253 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 254 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 255 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 256 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 257 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 258 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 259 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 260 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 261 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 262 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 263 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 264 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 265 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 266 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 267 #endif
 268
 269 #define CONFIG_HWCONFIG
 270
 271 /* define to use L1 as initial stack */
 272 #define CONFIG_L1_INIT_RAM
 273 #define CONFIG_SYS_INIT_RAM_LOCK
 274 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 277 /* The assembler doesn't like typecast */
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 279                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 280                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 281 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 282 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 283 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 284
 285 /*
 286  * Serial Port
 287  */
 288 #define CONFIG_SYS_NS16550_SERIAL
 289 #define CONFIG_SYS_NS16550_REG_SIZE     1
 290 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 291 #define CONFIG_SYS_BAUDRATE_TABLE       \
 292         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 295 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 296 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 297
 298 /*
 299  * I2C
 300  */
 301
 302 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 303 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 304 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 305 #define I2C_MUX_CH_DEFAULT      0x8
 306
 307 #define I2C_MUX_CH_VOL_MONITOR 0xa
 308
 309 /* Voltage monitor on channel 2*/
 310 #define I2C_VOL_MONITOR_ADDR           0x40
 311 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 312 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 313 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 314
 315 /* The lowest and highest voltage allowed for T208xQDS */
 316 #define VDD_MV_MIN                      819
 317 #define VDD_MV_MAX                      1212
 318
 319 /*
 320  * RapidIO
 321  */
 322 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 323 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 324 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 325 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 326 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 327 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 328 /*
 329  * for slave u-boot IMAGE instored in master memory space,
 330  * PHYS must be aligned based on the SIZE
 331  */
 332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 336 /*
 337  * for slave UCODE and ENV instored in master memory space,
 338  * PHYS must be aligned based on the SIZE
 339  */
 340 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 343
 344 /* slave core release by master*/
 345 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 346 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 347
 348 /*
 349  * SRIO_PCIE_BOOT - SLAVE
 350  */
 351 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 352 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 354                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 355 #endif
 356
 357 /*
 358  * eSPI - Enhanced SPI
 359  */
 360
 361 /*
 362  * General PCI
 363  * Memory space is mapped 1-1, but I/O space must start from 0.
 364  */
 365 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 366 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 367 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 368 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 369 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 370
 371 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 372 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 373 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 374 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 375 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 376
 377 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 378 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 379 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 380 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 381 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 382
 383 /* controller 4, Base address 203000 */
 384 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 385 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 386 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 387
 388 /* Qman/Bman */
 389 #ifndef CONFIG_NOBQFMAN
 390 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 391 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 392 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 393 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 394 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 395 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 396 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 397 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 398 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 399                                         CONFIG_SYS_BMAN_CENA_SIZE)
 400 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 401 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 402 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 403 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 404 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 405 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 406 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 407 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 408 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 409 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 410 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 411                                         CONFIG_SYS_QMAN_CENA_SIZE)
 412 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 413 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 414
 415 #define CONFIG_SYS_DPAA_FMAN
 416 #define CONFIG_SYS_DPAA_PME
 417 #define CONFIG_SYS_PMAN
 418 #define CONFIG_SYS_DPAA_DCE
 419 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 420 #define CONFIG_SYS_INTERLAKEN
 421
 422 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 423 #endif /* CONFIG_NOBQFMAN */
 424
 425 #ifdef CONFIG_SYS_DPAA_FMAN
 426 #define RGMII_PHY1_ADDR 0x1
 427 #define RGMII_PHY2_ADDR 0x2
 428 #define FM1_10GEC1_PHY_ADDR       0x3
 429 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 430 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 431 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 432 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 433 #endif
 434
 435 /*
 436  * USB
 437  */
 438
 439 /*
 440  * SDHC
 441  */
 442 #ifdef CONFIG_MMC
 443 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 444 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 445 #endif
 446
 447 /*
 448  * Dynamic MTD Partition support with mtdparts
 449  */
 450
 451 /*
 452  * Environment
 453  */
 454 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 455 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 456
 457 /*
 458  * Miscellaneous configurable options
 459  */
 460
 461 /*
 462  * For booting Linux, the board info and command line data
 463  * have to be in the first 64 MB of memory, since this is
 464  * the maximum mapped by the Linux kernel during initialization.
 465  */
 466 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 472 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 473
 474 #define __USB_PHY_TYPE          utmi
 475
 476 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 477         "hwconfig=fsl_ddr:"                                     \
 478         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 479         "bank_intlv=auto;"                                      \
 480         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 481         "netdev=eth0\0"                                         \
 482         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 483         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 484         "tftpflash=tftpboot $loadaddr $uboot && "               \
 485         "protect off $ubootaddr +$filesize && "                 \
 486         "erase $ubootaddr +$filesize && "                       \
 487         "cp.b $loadaddr $ubootaddr $filesize && "               \
 488         "protect on $ubootaddr +$filesize && "                  \
 489         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 490         "consoledev=ttyS0\0"                                    \
 491         "ramdiskaddr=2000000\0"                                 \
 492         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 493         "fdtaddr=1e00000\0"                                     \
 494         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 495         "bdev=sda3\0"
 496
 497 /*
 498  * For emulation this causes u-boot to jump to the start of the
 499  * proof point app code automatically
 500  */
 501 #define PROOF_POINTS                            \
 502         "setenv bootargs root=/dev/$bdev rw "           \
 503         "console=$consoledev,$baudrate $othbootargs;"   \
 504         "cpu 1 release 0x29000000 - - -;"               \
 505         "cpu 2 release 0x29000000 - - -;"               \
 506         "cpu 3 release 0x29000000 - - -;"               \
 507         "cpu 4 release 0x29000000 - - -;"               \
 508         "cpu 5 release 0x29000000 - - -;"               \
 509         "cpu 6 release 0x29000000 - - -;"               \
 510         "cpu 7 release 0x29000000 - - -;"               \
 511         "go 0x29000000"
 512
 513 #define HVBOOT                          \
 514         "setenv bootargs config-addr=0x60000000; "      \
 515         "bootm 0x01000000 - 0x00f00000"
 516
 517 #define ALU                             \
 518         "setenv bootargs root=/dev/$bdev rw "           \
 519         "console=$consoledev,$baudrate $othbootargs;"   \
 520         "cpu 1 release 0x01000000 - - -;"               \
 521         "cpu 2 release 0x01000000 - - -;"               \
 522         "cpu 3 release 0x01000000 - - -;"               \
 523         "cpu 4 release 0x01000000 - - -;"               \
 524         "cpu 5 release 0x01000000 - - -;"               \
 525         "cpu 6 release 0x01000000 - - -;"               \
 526         "cpu 7 release 0x01000000 - - -;"               \
 527         "go 0x01000000"
 528
 529 #include <asm/fsl_secure_boot.h>
 530
 531 #endif  /* __T208xQDS_H */