include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  44 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #ifdef CONFIG_DDR_ECC
  66 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67 #endif
  68
  69 /*
  70  * Config the L3 Cache as L3 SRAM
  71  */
  72 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  73 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  74
  75 #define CONFIG_SYS_DCSRBAR      0xf0000000
  76 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #define CONFIG_VERY_BIG_RAM
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  83 #define CFG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_SDRAM_BASE
  84 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  85 #define SPD_EEPROM_ADDRESS1     0x51
  86 #define SPD_EEPROM_ADDRESS2     0x52
  87 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  88 #define CTRL_INTLV_PREFERED     cacheline
  89
  90 /*
  91  * IFC Definitions
  92  */
  93 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  94 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  95 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
  96 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  97                                 + 0x8000000) | \
  98                                 CSPR_PORT_SIZE_16 | \
  99                                 CSPR_MSEL_NOR | \
 100                                 CSPR_V)
 101 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 102 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 103                                 CSPR_PORT_SIZE_16 | \
 104                                 CSPR_MSEL_NOR | \
 105                                 CSPR_V)
 106 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 107 /* NOR Flash Timing Params */
 108 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 109
 110 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 111                                 FTIM0_NOR_TEADC(0x5) | \
 112                                 FTIM0_NOR_TEAHC(0x5))
 113 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 114                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 115                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 116 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 117                                 FTIM2_NOR_TCH(0x4) | \
 118                                 FTIM2_NOR_TWPH(0x0E) | \
 119                                 FTIM2_NOR_TWP(0x1c))
 120 #define CFG_SYS_NOR_FTIM3       0x0
 121
 122 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 123
 124 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 125                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 126
 127 #define QIXIS_BASE                      0xffdf0000
 128 #define QIXIS_LBMAP_SWITCH              6
 129 #define QIXIS_LBMAP_MASK                0x0f
 130 #define QIXIS_LBMAP_SHIFT               0
 131 #define QIXIS_LBMAP_DFLTBANK            0x00
 132 #define QIXIS_LBMAP_ALTBANK             0x04
 133 #define QIXIS_LBMAP_NAND                0x09
 134 #define QIXIS_LBMAP_SD                  0x00
 135 #define QIXIS_RCW_SRC_NAND              0x104
 136 #define QIXIS_RCW_SRC_SD                0x040
 137 #define QIXIS_RST_CTL_RESET             0x83
 138 #define QIXIS_RST_FORCE_MEM             0x1
 139 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 140 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 141 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 142 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 143
 144 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 145 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 146                                 | CSPR_PORT_SIZE_8 \
 147                                 | CSPR_MSEL_GPCM \
 148                                 | CSPR_V)
 149 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 150 #define CONFIG_SYS_CSOR3        0x0
 151 /* QIXIS Timing parameters for IFC CS3 */
 152 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 153                                         FTIM0_GPCM_TEADC(0x0e) | \
 154                                         FTIM0_GPCM_TEAHC(0x0e))
 155 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 156                                         FTIM1_GPCM_TRAD(0x3f))
 157 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 158                                         FTIM2_GPCM_TCH(0x8) | \
 159                                         FTIM2_GPCM_TWP(0x1f))
 160 #define CONFIG_SYS_CS3_FTIM3            0x0
 161
 162 /* NAND Flash on IFC */
 163 #define CFG_SYS_NAND_BASE               0xff800000
 164 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 165
 166 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 167 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 168                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 169                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 170                                 | CSPR_V)
 171 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 172
 173 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 174                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 175                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 176                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 177                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 178                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 179                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 180
 181 /* ONFI NAND Flash mode0 Timing Params */
 182 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 183                                         FTIM0_NAND_TWP(0x18)    | \
 184                                         FTIM0_NAND_TWCHT(0x07)  | \
 185                                         FTIM0_NAND_TWH(0x0a))
 186 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 187                                         FTIM1_NAND_TWBE(0x39)   | \
 188                                         FTIM1_NAND_TRR(0x0e)    | \
 189                                         FTIM1_NAND_TRP(0x18))
 190 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 191                                         FTIM2_NAND_TREH(0x0a)   | \
 192                                         FTIM2_NAND_TWHRE(0x1e))
 193 #define CFG_SYS_NAND_FTIM3              0x0
 194
 195 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 196
 197 #if defined(CONFIG_MTD_RAW_NAND)
 198 #define CONFIG_SYS_CSPR0_EXT            CFG_SYS_NAND_CSPR_EXT
 199 #define CONFIG_SYS_CSPR0                CFG_SYS_NAND_CSPR
 200 #define CONFIG_SYS_AMASK0               CFG_SYS_NAND_AMASK
 201 #define CONFIG_SYS_CSOR0                CFG_SYS_NAND_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NAND_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NAND_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NAND_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NAND_FTIM3
 206 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 208 #define CONFIG_SYS_AMASK1               CFG_SYS_NOR_AMASK
 209 #define CONFIG_SYS_CSOR1                CFG_SYS_NOR_CSOR
 210 #define CONFIG_SYS_CS1_FTIM0            CFG_SYS_NOR_FTIM0
 211 #define CONFIG_SYS_CS1_FTIM1            CFG_SYS_NOR_FTIM1
 212 #define CONFIG_SYS_CS1_FTIM2            CFG_SYS_NOR_FTIM2
 213 #define CONFIG_SYS_CS1_FTIM3            CFG_SYS_NOR_FTIM3
 214 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 215 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 216 #define CONFIG_SYS_AMASK2               CFG_SYS_NOR_AMASK
 217 #define CONFIG_SYS_CSOR2                CFG_SYS_NOR_CSOR
 218 #define CONFIG_SYS_CS2_FTIM0            CFG_SYS_NOR_FTIM0
 219 #define CONFIG_SYS_CS2_FTIM1            CFG_SYS_NOR_FTIM1
 220 #define CONFIG_SYS_CS2_FTIM2            CFG_SYS_NOR_FTIM2
 221 #define CONFIG_SYS_CS2_FTIM3            CFG_SYS_NOR_FTIM3
 222 #else
 223 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 224 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 225 #define CONFIG_SYS_AMASK0               CFG_SYS_NOR_AMASK
 226 #define CONFIG_SYS_CSOR0                CFG_SYS_NOR_CSOR
 227 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NOR_FTIM0
 228 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NOR_FTIM1
 229 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NOR_FTIM2
 230 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NOR_FTIM3
 231 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 232 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 233 #define CONFIG_SYS_AMASK1               CFG_SYS_NOR_AMASK
 234 #define CONFIG_SYS_CSOR1                CFG_SYS_NOR_CSOR
 235 #define CONFIG_SYS_CS1_FTIM0            CFG_SYS_NOR_FTIM0
 236 #define CONFIG_SYS_CS1_FTIM1            CFG_SYS_NOR_FTIM1
 237 #define CONFIG_SYS_CS1_FTIM2            CFG_SYS_NOR_FTIM2
 238 #define CONFIG_SYS_CS1_FTIM3            CFG_SYS_NOR_FTIM3
 239 #define CONFIG_SYS_CSPR2_EXT            CFG_SYS_NAND_CSPR_EXT
 240 #define CONFIG_SYS_CSPR2                CFG_SYS_NAND_CSPR
 241 #define CONFIG_SYS_AMASK2               CFG_SYS_NAND_AMASK
 242 #define CONFIG_SYS_CSOR2                CFG_SYS_NAND_CSOR
 243 #define CONFIG_SYS_CS2_FTIM0            CFG_SYS_NAND_FTIM0
 244 #define CONFIG_SYS_CS2_FTIM1            CFG_SYS_NAND_FTIM1
 245 #define CONFIG_SYS_CS2_FTIM2            CFG_SYS_NAND_FTIM2
 246 #define CONFIG_SYS_CS2_FTIM3            CFG_SYS_NAND_FTIM3
 247 #endif
 248
 249 #define CONFIG_HWCONFIG
 250
 251 /* define to use L1 as initial stack */
 252 #define CONFIG_L1_INIT_RAM
 253 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 256 /* The assembler doesn't like typecast */
 257 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 258                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 259                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 260 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 261 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 262
 263 /*
 264  * Serial Port
 265  */
 266 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 267 #define CONFIG_SYS_BAUDRATE_TABLE       \
 268         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 269 #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 270 #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 271 #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 272 #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 273
 274 /*
 275  * I2C
 276  */
 277
 278 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 279 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 280 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 281 #define I2C_MUX_CH_DEFAULT      0x8
 282
 283 #define I2C_MUX_CH_VOL_MONITOR 0xa
 284
 285 /* Voltage monitor on channel 2*/
 286 #define I2C_VOL_MONITOR_ADDR           0x40
 287 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 288 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 289 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 290
 291 /* The lowest and highest voltage allowed for T208xQDS */
 292 #define VDD_MV_MIN                      819
 293 #define VDD_MV_MAX                      1212
 294
 295 /*
 296  * RapidIO
 297  */
 298 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 299 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 300 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 301 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 302 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 303 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 304 /*
 305  * for slave u-boot IMAGE instored in master memory space,
 306  * PHYS must be aligned based on the SIZE
 307  */
 308 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 309 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 310 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 311 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 312 /*
 313  * for slave UCODE and ENV instored in master memory space,
 314  * PHYS must be aligned based on the SIZE
 315  */
 316 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 317 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 318 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 319
 320 /* slave core release by master*/
 321 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 322 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 323
 324 /*
 325  * SRIO_PCIE_BOOT - SLAVE
 326  */
 327 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 328 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 329 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 330                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 331 #endif
 332
 333 /*
 334  * eSPI - Enhanced SPI
 335  */
 336
 337 /*
 338  * General PCI
 339  * Memory space is mapped 1-1, but I/O space must start from 0.
 340  */
 341 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 342 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 343 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 344 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 345 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 346
 347 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 348 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 349 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 350 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 351 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 352
 353 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 354 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 355 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 356
 357 /* controller 4, Base address 203000 */
 358 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 359 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 360
 361 /* Qman/Bman */
 362 #ifndef CONFIG_NOBQFMAN
 363 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 364 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 365 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 366 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 367 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 368 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 369 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 370 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 371 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 372                                         CONFIG_SYS_BMAN_CENA_SIZE)
 373 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 374 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 375 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 376 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 377 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 378 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 379 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 380 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 381 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 382                                         CONFIG_SYS_QMAN_CENA_SIZE)
 383 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 384 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 385 #endif /* CONFIG_NOBQFMAN */
 386
 387 #ifdef CONFIG_SYS_DPAA_FMAN
 388 #define RGMII_PHY1_ADDR 0x1
 389 #define RGMII_PHY2_ADDR 0x2
 390 #define FM1_10GEC1_PHY_ADDR       0x3
 391 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 392 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 393 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 394 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 395 #endif
 396
 397 /*
 398  * USB
 399  */
 400
 401 /*
 402  * SDHC
 403  */
 404 #ifdef CONFIG_MMC
 405 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 406 #endif
 407
 408 /*
 409  * Dynamic MTD Partition support with mtdparts
 410  */
 411
 412 /*
 413  * Miscellaneous configurable options
 414  */
 415
 416 /*
 417  * For booting Linux, the board info and command line data
 418  * have to be in the first 64 MB of memory, since this is
 419  * the maximum mapped by the Linux kernel during initialization.
 420  */
 421 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 422
 423 /*
 424  * Environment Configuration
 425  */
 426 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 427 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 428
 429 #define __USB_PHY_TYPE          utmi
 430
 431 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 432         "hwconfig=fsl_ddr:"                                     \
 433         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 434         "bank_intlv=auto;"                                      \
 435         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 436         "netdev=eth0\0"                                         \
 437         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 438         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 439         "tftpflash=tftpboot $loadaddr $uboot && "               \
 440         "protect off $ubootaddr +$filesize && "                 \
 441         "erase $ubootaddr +$filesize && "                       \
 442         "cp.b $loadaddr $ubootaddr $filesize && "               \
 443         "protect on $ubootaddr +$filesize && "                  \
 444         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 445         "consoledev=ttyS0\0"                                    \
 446         "ramdiskaddr=2000000\0"                                 \
 447         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 448         "fdtaddr=1e00000\0"                                     \
 449         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 450         "bdev=sda3\0"
 451
 452 /*
 453  * For emulation this causes u-boot to jump to the start of the
 454  * proof point app code automatically
 455  */
 456 #define PROOF_POINTS                            \
 457         "setenv bootargs root=/dev/$bdev rw "           \
 458         "console=$consoledev,$baudrate $othbootargs;"   \
 459         "cpu 1 release 0x29000000 - - -;"               \
 460         "cpu 2 release 0x29000000 - - -;"               \
 461         "cpu 3 release 0x29000000 - - -;"               \
 462         "cpu 4 release 0x29000000 - - -;"               \
 463         "cpu 5 release 0x29000000 - - -;"               \
 464         "cpu 6 release 0x29000000 - - -;"               \
 465         "cpu 7 release 0x29000000 - - -;"               \
 466         "go 0x29000000"
 467
 468 #define HVBOOT                          \
 469         "setenv bootargs config-addr=0x60000000; "      \
 470         "bootm 0x01000000 - 0x00f00000"
 471
 472 #define ALU                             \
 473         "setenv bootargs root=/dev/$bdev rw "           \
 474         "console=$consoledev,$baudrate $othbootargs;"   \
 475         "cpu 1 release 0x01000000 - - -;"               \
 476         "cpu 2 release 0x01000000 - - -;"               \
 477         "cpu 3 release 0x01000000 - - -;"               \
 478         "cpu 4 release 0x01000000 - - -;"               \
 479         "cpu 5 release 0x01000000 - - -;"               \
 480         "cpu 6 release 0x01000000 - - -;"               \
 481         "cpu 7 release 0x01000000 - - -;"               \
 482         "go 0x01000000"
 483
 484 #include <asm/fsl_secure_boot.h>
 485
 486 #endif  /* __T208xQDS_H */