include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34
  35 #ifdef CONFIG_MTD_RAW_NAND
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  37 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  38 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  39 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41 #endif
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  50 #ifndef CONFIG_SPL_BUILD
  51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_SDCARD
  56 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  57 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  58 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  59 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  60 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  61 #ifndef CONFIG_SPL_BUILD
  62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  63 #endif
  64 #endif
  65
  66 #endif /* CONFIG_RAMBOOT_PBL */
  67
  68 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  69 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  70 /* Set 1M boot space */
  71 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  73                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  74 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  75 #endif
  76
  77 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  78 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  79 #endif
  80
  81 /*
  82  * These can be toggled for performance analysis, otherwise use default.
  83  */
  84 #define CONFIG_SYS_CACHE_STASHING
  85 #ifdef CONFIG_DDR_ECC
  86 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  87 #endif
  88
  89 /*
  90  * Config the L3 Cache as L3 SRAM
  91  */
  92 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  93 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  94 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  95
  96 #define CONFIG_SYS_DCSRBAR      0xf0000000
  97 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  98
  99 /* EEPROM */
 100 #define CONFIG_SYS_I2C_EEPROM_NXID
 101 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 102
 103 /*
 104  * DDR Setup
 105  */
 106 #define CONFIG_VERY_BIG_RAM
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 109 #define CONFIG_SYS_SPD_BUS_NUM  0
 110 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 111 #define SPD_EEPROM_ADDRESS1     0x51
 112 #define SPD_EEPROM_ADDRESS2     0x52
 113 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 114 #define CTRL_INTLV_PREFERED     cacheline
 115
 116 /*
 117  * IFC Definitions
 118  */
 119 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 120 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 121 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 122 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 123                                 + 0x8000000) | \
 124                                 CSPR_PORT_SIZE_16 | \
 125                                 CSPR_MSEL_NOR | \
 126                                 CSPR_V)
 127 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 128 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 129                                 CSPR_PORT_SIZE_16 | \
 130                                 CSPR_MSEL_NOR | \
 131                                 CSPR_V)
 132 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 133 /* NOR Flash Timing Params */
 134 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 135
 136 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 137                                 FTIM0_NOR_TEADC(0x5) | \
 138                                 FTIM0_NOR_TEAHC(0x5))
 139 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 140                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 141                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 142 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 143                                 FTIM2_NOR_TCH(0x4) | \
 144                                 FTIM2_NOR_TWPH(0x0E) | \
 145                                 FTIM2_NOR_TWP(0x1c))
 146 #define CONFIG_SYS_NOR_FTIM3    0x0
 147
 148 #define CONFIG_SYS_FLASH_QUIET_TEST
 149 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 150
 151 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 154
 155 #define CONFIG_SYS_FLASH_EMPTY_INFO
 156 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 157                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 158
 159 #define QIXIS_BASE                      0xffdf0000
 160 #define QIXIS_LBMAP_SWITCH              6
 161 #define QIXIS_LBMAP_MASK                0x0f
 162 #define QIXIS_LBMAP_SHIFT               0
 163 #define QIXIS_LBMAP_DFLTBANK            0x00
 164 #define QIXIS_LBMAP_ALTBANK             0x04
 165 #define QIXIS_LBMAP_NAND                0x09
 166 #define QIXIS_LBMAP_SD                  0x00
 167 #define QIXIS_RCW_SRC_NAND              0x104
 168 #define QIXIS_RCW_SRC_SD                0x040
 169 #define QIXIS_RST_CTL_RESET             0x83
 170 #define QIXIS_RST_FORCE_MEM             0x1
 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 172 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 174 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 175
 176 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 177 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 178                                 | CSPR_PORT_SIZE_8 \
 179                                 | CSPR_MSEL_GPCM \
 180                                 | CSPR_V)
 181 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 182 #define CONFIG_SYS_CSOR3        0x0
 183 /* QIXIS Timing parameters for IFC CS3 */
 184 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 185                                         FTIM0_GPCM_TEADC(0x0e) | \
 186                                         FTIM0_GPCM_TEAHC(0x0e))
 187 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 188                                         FTIM1_GPCM_TRAD(0x3f))
 189 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 190                                         FTIM2_GPCM_TCH(0x8) | \
 191                                         FTIM2_GPCM_TWP(0x1f))
 192 #define CONFIG_SYS_CS3_FTIM3            0x0
 193
 194 /* NAND Flash on IFC */
 195 #define CONFIG_SYS_NAND_BASE            0xff800000
 196 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 197
 198 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 199 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 200                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 201                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 202                                 | CSPR_V)
 203 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 204
 205 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 206                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 207                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 208                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 209                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 210                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 211                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 212
 213 /* ONFI NAND Flash mode0 Timing Params */
 214 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 215                                         FTIM0_NAND_TWP(0x18)    | \
 216                                         FTIM0_NAND_TWCHT(0x07)  | \
 217                                         FTIM0_NAND_TWH(0x0a))
 218 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 219                                         FTIM1_NAND_TWBE(0x39)   | \
 220                                         FTIM1_NAND_TRR(0x0e)    | \
 221                                         FTIM1_NAND_TRP(0x18))
 222 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 223                                         FTIM2_NAND_TREH(0x0a)   | \
 224                                         FTIM2_NAND_TWHRE(0x1e))
 225 #define CONFIG_SYS_NAND_FTIM3           0x0
 226
 227 #define CONFIG_SYS_NAND_DDR_LAW         11
 228 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 230
 231 #if defined(CONFIG_MTD_RAW_NAND)
 232 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 233 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 234 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 235 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 236 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 237 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 238 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 239 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 240 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 241 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 242 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 243 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 244 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 245 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 246 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 247 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 248 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 249 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 250 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 251 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 252 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 253 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 254 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 255 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 256 #else
 257 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 258 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 259 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 260 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 261 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 262 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 263 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 264 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 265 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 266 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 267 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 268 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 269 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 270 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 271 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 272 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 273 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 274 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 275 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 276 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 277 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 278 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 279 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 280 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 281 #endif
 282
 283 #if defined(CONFIG_RAMBOOT_PBL)
 284 #define CONFIG_SYS_RAMBOOT
 285 #endif
 286
 287 #define CONFIG_HWCONFIG
 288
 289 /* define to use L1 as initial stack */
 290 #define CONFIG_L1_INIT_RAM
 291 #define CONFIG_SYS_INIT_RAM_LOCK
 292 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 295 /* The assembler doesn't like typecast */
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 297                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 298                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 299 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 300 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 301 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 302
 303 /*
 304  * Serial Port
 305  */
 306 #define CONFIG_SYS_NS16550_SERIAL
 307 #define CONFIG_SYS_NS16550_REG_SIZE     1
 308 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 309 #define CONFIG_SYS_BAUDRATE_TABLE       \
 310         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 313 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 314 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 315
 316 /*
 317  * I2C
 318  */
 319
 320 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 321 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 322 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 323 #define I2C_MUX_CH_DEFAULT      0x8
 324
 325 #define I2C_MUX_CH_VOL_MONITOR 0xa
 326
 327 /* Voltage monitor on channel 2*/
 328 #define I2C_VOL_MONITOR_ADDR           0x40
 329 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 330 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 331 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 332
 333 /* The lowest and highest voltage allowed for T208xQDS */
 334 #define VDD_MV_MIN                      819
 335 #define VDD_MV_MAX                      1212
 336
 337 /*
 338  * RapidIO
 339  */
 340 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 341 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 342 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 343 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 344 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 345 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 346 /*
 347  * for slave u-boot IMAGE instored in master memory space,
 348  * PHYS must be aligned based on the SIZE
 349  */
 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 354 /*
 355  * for slave UCODE and ENV instored in master memory space,
 356  * PHYS must be aligned based on the SIZE
 357  */
 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 361
 362 /* slave core release by master*/
 363 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 364 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 365
 366 /*
 367  * SRIO_PCIE_BOOT - SLAVE
 368  */
 369 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 372                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 373 #endif
 374
 375 /*
 376  * eSPI - Enhanced SPI
 377  */
 378
 379 /*
 380  * General PCI
 381  * Memory space is mapped 1-1, but I/O space must start from 0.
 382  */
 383 #define CONFIG_PCIE1            /* PCIE controller 1 */
 384 #define CONFIG_PCIE2            /* PCIE controller 2 */
 385 #define CONFIG_PCIE3            /* PCIE controller 3 */
 386 #define CONFIG_PCIE4            /* PCIE controller 4 */
 387 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 388 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 389 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 390 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 391 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 392
 393 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 394 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 395 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 396 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 397 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 398
 399 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 400 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 401 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 402 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 403 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 404
 405 /* controller 4, Base address 203000 */
 406 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 407 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 408 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 409
 410 #ifdef CONFIG_PCI
 411 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 412 #endif
 413
 414 /* Qman/Bman */
 415 #ifndef CONFIG_NOBQFMAN
 416 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 417 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 418 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 419 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 420 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 421 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 422 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 423 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 424 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 425                                         CONFIG_SYS_BMAN_CENA_SIZE)
 426 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 427 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 428 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 429 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 430 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 431 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 432 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 433 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 434 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 435 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 436 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 437                                         CONFIG_SYS_QMAN_CENA_SIZE)
 438 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 439 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 440
 441 #define CONFIG_SYS_DPAA_FMAN
 442 #define CONFIG_SYS_DPAA_PME
 443 #define CONFIG_SYS_PMAN
 444 #define CONFIG_SYS_DPAA_DCE
 445 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 446 #define CONFIG_SYS_INTERLAKEN
 447
 448 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 449 #endif /* CONFIG_NOBQFMAN */
 450
 451 #ifdef CONFIG_SYS_DPAA_FMAN
 452 #define RGMII_PHY1_ADDR 0x1
 453 #define RGMII_PHY2_ADDR 0x2
 454 #define FM1_10GEC1_PHY_ADDR       0x3
 455 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 456 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 457 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 458 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 459 #endif
 460
 461 /*
 462  * SATA
 463  */
 464 #ifdef CONFIG_FSL_SATA_V2
 465 #define CONFIG_LBA48
 466 #endif
 467
 468 /*
 469  * USB
 470  */
 471
 472 /*
 473  * SDHC
 474  */
 475 #ifdef CONFIG_MMC
 476 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 477 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 478 #endif
 479
 480 /*
 481  * Dynamic MTD Partition support with mtdparts
 482  */
 483
 484 /*
 485  * Environment
 486  */
 487 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 488 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 489
 490 /*
 491  * Miscellaneous configurable options
 492  */
 493
 494 /*
 495  * For booting Linux, the board info and command line data
 496  * have to be in the first 64 MB of memory, since this is
 497  * the maximum mapped by the Linux kernel during initialization.
 498  */
 499 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 500 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 501
 502 /*
 503  * Environment Configuration
 504  */
 505 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 506 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 507
 508 #define __USB_PHY_TYPE          utmi
 509
 510 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 511         "hwconfig=fsl_ddr:"                                     \
 512         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 513         "bank_intlv=auto;"                                      \
 514         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 515         "netdev=eth0\0"                                         \
 516         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 517         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 518         "tftpflash=tftpboot $loadaddr $uboot && "               \
 519         "protect off $ubootaddr +$filesize && "                 \
 520         "erase $ubootaddr +$filesize && "                       \
 521         "cp.b $loadaddr $ubootaddr $filesize && "               \
 522         "protect on $ubootaddr +$filesize && "                  \
 523         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 524         "consoledev=ttyS0\0"                                    \
 525         "ramdiskaddr=2000000\0"                                 \
 526         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 527         "fdtaddr=1e00000\0"                                     \
 528         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 529         "bdev=sda3\0"
 530
 531 /*
 532  * For emulation this causes u-boot to jump to the start of the
 533  * proof point app code automatically
 534  */
 535 #define PROOF_POINTS                            \
 536         "setenv bootargs root=/dev/$bdev rw "           \
 537         "console=$consoledev,$baudrate $othbootargs;"   \
 538         "cpu 1 release 0x29000000 - - -;"               \
 539         "cpu 2 release 0x29000000 - - -;"               \
 540         "cpu 3 release 0x29000000 - - -;"               \
 541         "cpu 4 release 0x29000000 - - -;"               \
 542         "cpu 5 release 0x29000000 - - -;"               \
 543         "cpu 6 release 0x29000000 - - -;"               \
 544         "cpu 7 release 0x29000000 - - -;"               \
 545         "go 0x29000000"
 546
 547 #define HVBOOT                          \
 548         "setenv bootargs config-addr=0x60000000; "      \
 549         "bootm 0x01000000 - 0x00f00000"
 550
 551 #define ALU                             \
 552         "setenv bootargs root=/dev/$bdev rw "           \
 553         "console=$consoledev,$baudrate $othbootargs;"   \
 554         "cpu 1 release 0x01000000 - - -;"               \
 555         "cpu 2 release 0x01000000 - - -;"               \
 556         "cpu 3 release 0x01000000 - - -;"               \
 557         "cpu 4 release 0x01000000 - - -;"               \
 558         "cpu 5 release 0x01000000 - - -;"               \
 559         "cpu 6 release 0x01000000 - - -;"               \
 560         "cpu 7 release 0x01000000 - - -;"               \
 561         "go 0x01000000"
 562
 563 #include <asm/fsl_secure_boot.h>
 564
 565 #endif  /* __T208xQDS_H */