include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  19 #define CONFIG_SRIO1            /* SRIO port 1 */
  20 #define CONFIG_SRIO2            /* SRIO port 2 */
  21 #endif
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  25 #define CONFIG_ENABLE_36BIT_PHYS
  26
  27 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define RESET_VECTOR_OFFSET             0x27FFC
  32 #define BOOT_PAGE_OFFSET                0x27000
  33
  34 #ifdef CONFIG_MTD_RAW_NAND
  35 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  36 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  37 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  38 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #endif
  41 #endif
  42
  43 #ifdef CONFIG_SPIFLASH
  44 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  49 #ifndef CONFIG_SPL_BUILD
  50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_SDCARD
  55 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  56 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  57 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  58 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  59 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  60 #ifndef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #endif
  64
  65 #endif /* CONFIG_RAMBOOT_PBL */
  66
  67 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  68 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  69 /* Set 1M boot space */
  70 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  71 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  72                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  73 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  74 #endif
  75
  76 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  77 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  78 #endif
  79
  80 /*
  81  * These can be toggled for performance analysis, otherwise use default.
  82  */
  83 #define CONFIG_SYS_CACHE_STASHING
  84 #ifdef CONFIG_DDR_ECC
  85 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  86 #endif
  87
  88 /*
  89  * Config the L3 Cache as L3 SRAM
  90  */
  91 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  92 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  93 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  94
  95 #define CONFIG_SYS_DCSRBAR      0xf0000000
  96 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  97
  98 /* EEPROM */
  99 #define CONFIG_SYS_I2C_EEPROM_NXID
 100 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 101
 102 /*
 103  * DDR Setup
 104  */
 105 #define CONFIG_VERY_BIG_RAM
 106 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 107 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 108 #define CONFIG_SYS_SPD_BUS_NUM  0
 109 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 110 #define SPD_EEPROM_ADDRESS1     0x51
 111 #define SPD_EEPROM_ADDRESS2     0x52
 112 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 113 #define CTRL_INTLV_PREFERED     cacheline
 114
 115 /*
 116  * IFC Definitions
 117  */
 118 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 119 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 120 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 121 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 122                                 + 0x8000000) | \
 123                                 CSPR_PORT_SIZE_16 | \
 124                                 CSPR_MSEL_NOR | \
 125                                 CSPR_V)
 126 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 127 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 128                                 CSPR_PORT_SIZE_16 | \
 129                                 CSPR_MSEL_NOR | \
 130                                 CSPR_V)
 131 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 132 /* NOR Flash Timing Params */
 133 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 134
 135 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 136                                 FTIM0_NOR_TEADC(0x5) | \
 137                                 FTIM0_NOR_TEAHC(0x5))
 138 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 139                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 140                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 141 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 142                                 FTIM2_NOR_TCH(0x4) | \
 143                                 FTIM2_NOR_TWPH(0x0E) | \
 144                                 FTIM2_NOR_TWP(0x1c))
 145 #define CONFIG_SYS_NOR_FTIM3    0x0
 146
 147 #define CONFIG_SYS_FLASH_QUIET_TEST
 148 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 149
 150 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 151 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 152 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 153
 154 #define CONFIG_SYS_FLASH_EMPTY_INFO
 155 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 156                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 157
 158 #define QIXIS_BASE                      0xffdf0000
 159 #define QIXIS_LBMAP_SWITCH              6
 160 #define QIXIS_LBMAP_MASK                0x0f
 161 #define QIXIS_LBMAP_SHIFT               0
 162 #define QIXIS_LBMAP_DFLTBANK            0x00
 163 #define QIXIS_LBMAP_ALTBANK             0x04
 164 #define QIXIS_LBMAP_NAND                0x09
 165 #define QIXIS_LBMAP_SD                  0x00
 166 #define QIXIS_RCW_SRC_NAND              0x104
 167 #define QIXIS_RCW_SRC_SD                0x040
 168 #define QIXIS_RST_CTL_RESET             0x83
 169 #define QIXIS_RST_FORCE_MEM             0x1
 170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 171 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 173 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 174
 175 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 176 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 177                                 | CSPR_PORT_SIZE_8 \
 178                                 | CSPR_MSEL_GPCM \
 179                                 | CSPR_V)
 180 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 181 #define CONFIG_SYS_CSOR3        0x0
 182 /* QIXIS Timing parameters for IFC CS3 */
 183 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 184                                         FTIM0_GPCM_TEADC(0x0e) | \
 185                                         FTIM0_GPCM_TEAHC(0x0e))
 186 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 187                                         FTIM1_GPCM_TRAD(0x3f))
 188 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 189                                         FTIM2_GPCM_TCH(0x8) | \
 190                                         FTIM2_GPCM_TWP(0x1f))
 191 #define CONFIG_SYS_CS3_FTIM3            0x0
 192
 193 /* NAND Flash on IFC */
 194 #define CONFIG_SYS_NAND_BASE            0xff800000
 195 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 196
 197 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 198 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 199                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 200                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 201                                 | CSPR_V)
 202 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 203
 204 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 205                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 206                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 207                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 208                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 209                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 210                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 211
 212 /* ONFI NAND Flash mode0 Timing Params */
 213 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 214                                         FTIM0_NAND_TWP(0x18)    | \
 215                                         FTIM0_NAND_TWCHT(0x07)  | \
 216                                         FTIM0_NAND_TWH(0x0a))
 217 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 218                                         FTIM1_NAND_TWBE(0x39)   | \
 219                                         FTIM1_NAND_TRR(0x0e)    | \
 220                                         FTIM1_NAND_TRP(0x18))
 221 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 222                                         FTIM2_NAND_TREH(0x0a)   | \
 223                                         FTIM2_NAND_TWHRE(0x1e))
 224 #define CONFIG_SYS_NAND_FTIM3           0x0
 225
 226 #define CONFIG_SYS_NAND_DDR_LAW         11
 227 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 228 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 229
 230 #if defined(CONFIG_MTD_RAW_NAND)
 231 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 232 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 233 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 234 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 235 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 236 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 237 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 238 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 239 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 240 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 241 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 242 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 243 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 244 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 245 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 246 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 247 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 248 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 249 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 250 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 251 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 252 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 253 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 254 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 255 #else
 256 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 257 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 258 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 259 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 260 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 261 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 262 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 263 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 264 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 265 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 266 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #endif
 281
 282 #if defined(CONFIG_RAMBOOT_PBL)
 283 #define CONFIG_SYS_RAMBOOT
 284 #endif
 285
 286 #define CONFIG_HWCONFIG
 287
 288 /* define to use L1 as initial stack */
 289 #define CONFIG_L1_INIT_RAM
 290 #define CONFIG_SYS_INIT_RAM_LOCK
 291 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 294 /* The assembler doesn't like typecast */
 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 296                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 297                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 298 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 299 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 300 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 301
 302 /*
 303  * Serial Port
 304  */
 305 #define CONFIG_SYS_NS16550_SERIAL
 306 #define CONFIG_SYS_NS16550_REG_SIZE     1
 307 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 308 #define CONFIG_SYS_BAUDRATE_TABLE       \
 309         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 312 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 313 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 314
 315 /*
 316  * I2C
 317  */
 318
 319 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 320 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 321 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 322 #define I2C_MUX_CH_DEFAULT      0x8
 323
 324 #define I2C_MUX_CH_VOL_MONITOR 0xa
 325
 326 /* Voltage monitor on channel 2*/
 327 #define I2C_VOL_MONITOR_ADDR           0x40
 328 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 329 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 330 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 331
 332 /* The lowest and highest voltage allowed for T208xQDS */
 333 #define VDD_MV_MIN                      819
 334 #define VDD_MV_MAX                      1212
 335
 336 /*
 337  * RapidIO
 338  */
 339 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 340 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 341 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 342 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 343 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 344 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 345 /*
 346  * for slave u-boot IMAGE instored in master memory space,
 347  * PHYS must be aligned based on the SIZE
 348  */
 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 353 /*
 354  * for slave UCODE and ENV instored in master memory space,
 355  * PHYS must be aligned based on the SIZE
 356  */
 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 360
 361 /* slave core release by master*/
 362 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 363 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 364
 365 /*
 366  * SRIO_PCIE_BOOT - SLAVE
 367  */
 368 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 371                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 372 #endif
 373
 374 /*
 375  * eSPI - Enhanced SPI
 376  */
 377
 378 /*
 379  * General PCI
 380  * Memory space is mapped 1-1, but I/O space must start from 0.
 381  */
 382 #define CONFIG_PCIE1            /* PCIE controller 1 */
 383 #define CONFIG_PCIE2            /* PCIE controller 2 */
 384 #define CONFIG_PCIE3            /* PCIE controller 3 */
 385 #define CONFIG_PCIE4            /* PCIE controller 4 */
 386 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 387 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 388 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 389 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 390 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 391
 392 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 393 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 394 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 395 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 396 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 397
 398 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 399 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 400 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 401 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 402 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 403
 404 /* controller 4, Base address 203000 */
 405 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 406 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 407 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 408
 409 #ifdef CONFIG_PCI
 410 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 411 #endif
 412
 413 /* Qman/Bman */
 414 #ifndef CONFIG_NOBQFMAN
 415 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 416 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 417 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 418 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 419 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 420 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 421 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 422 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 423 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 424                                         CONFIG_SYS_BMAN_CENA_SIZE)
 425 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 426 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 427 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 428 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 429 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 430 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 431 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 432 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 433 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 434 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 435 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 436                                         CONFIG_SYS_QMAN_CENA_SIZE)
 437 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 438 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 439
 440 #define CONFIG_SYS_DPAA_FMAN
 441 #define CONFIG_SYS_DPAA_PME
 442 #define CONFIG_SYS_PMAN
 443 #define CONFIG_SYS_DPAA_DCE
 444 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 445 #define CONFIG_SYS_INTERLAKEN
 446
 447 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 448 #endif /* CONFIG_NOBQFMAN */
 449
 450 #ifdef CONFIG_SYS_DPAA_FMAN
 451 #define RGMII_PHY1_ADDR 0x1
 452 #define RGMII_PHY2_ADDR 0x2
 453 #define FM1_10GEC1_PHY_ADDR       0x3
 454 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 455 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 456 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 457 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 458 #endif
 459
 460 /*
 461  * SATA
 462  */
 463 #ifdef CONFIG_FSL_SATA_V2
 464 #define CONFIG_LBA48
 465 #endif
 466
 467 /*
 468  * USB
 469  */
 470
 471 /*
 472  * SDHC
 473  */
 474 #ifdef CONFIG_MMC
 475 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 476 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 477 #endif
 478
 479 /*
 480  * Dynamic MTD Partition support with mtdparts
 481  */
 482
 483 /*
 484  * Environment
 485  */
 486 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 487 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 488
 489 /*
 490  * Miscellaneous configurable options
 491  */
 492
 493 /*
 494  * For booting Linux, the board info and command line data
 495  * have to be in the first 64 MB of memory, since this is
 496  * the maximum mapped by the Linux kernel during initialization.
 497  */
 498 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 499 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 500
 501 /*
 502  * Environment Configuration
 503  */
 504 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 505 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 506
 507 #define __USB_PHY_TYPE          utmi
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 510         "hwconfig=fsl_ddr:"                                     \
 511         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 512         "bank_intlv=auto;"                                      \
 513         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 514         "netdev=eth0\0"                                         \
 515         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 516         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 517         "tftpflash=tftpboot $loadaddr $uboot && "               \
 518         "protect off $ubootaddr +$filesize && "                 \
 519         "erase $ubootaddr +$filesize && "                       \
 520         "cp.b $loadaddr $ubootaddr $filesize && "               \
 521         "protect on $ubootaddr +$filesize && "                  \
 522         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 523         "consoledev=ttyS0\0"                                    \
 524         "ramdiskaddr=2000000\0"                                 \
 525         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 526         "fdtaddr=1e00000\0"                                     \
 527         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 528         "bdev=sda3\0"
 529
 530 /*
 531  * For emulation this causes u-boot to jump to the start of the
 532  * proof point app code automatically
 533  */
 534 #define PROOF_POINTS                            \
 535         "setenv bootargs root=/dev/$bdev rw "           \
 536         "console=$consoledev,$baudrate $othbootargs;"   \
 537         "cpu 1 release 0x29000000 - - -;"               \
 538         "cpu 2 release 0x29000000 - - -;"               \
 539         "cpu 3 release 0x29000000 - - -;"               \
 540         "cpu 4 release 0x29000000 - - -;"               \
 541         "cpu 5 release 0x29000000 - - -;"               \
 542         "cpu 6 release 0x29000000 - - -;"               \
 543         "cpu 7 release 0x29000000 - - -;"               \
 544         "go 0x29000000"
 545
 546 #define HVBOOT                          \
 547         "setenv bootargs config-addr=0x60000000; "      \
 548         "bootm 0x01000000 - 0x00f00000"
 549
 550 #define ALU                             \
 551         "setenv bootargs root=/dev/$bdev rw "           \
 552         "console=$consoledev,$baudrate $othbootargs;"   \
 553         "cpu 1 release 0x01000000 - - -;"               \
 554         "cpu 2 release 0x01000000 - - -;"               \
 555         "cpu 3 release 0x01000000 - - -;"               \
 556         "cpu 4 release 0x01000000 - - -;"               \
 557         "cpu 5 release 0x01000000 - - -;"               \
 558         "cpu 6 release 0x01000000 - - -;"               \
 559         "cpu 7 release 0x01000000 - - -;"               \
 560         "go 0x01000000"
 561
 562 #include <asm/fsl_secure_boot.h>
 563
 564 #endif  /* __T208xQDS_H */