include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_MTD_RAW_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #endif
  48
  49 #ifdef CONFIG_SPIFLASH
  50 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  51 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  56 #ifndef CONFIG_SPL_BUILD
  57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58 #endif
  59 #endif
  60
  61 #ifdef CONFIG_SDCARD
  62 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  63 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  64 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  65 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  66 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  67 #ifndef CONFIG_SPL_BUILD
  68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  69 #endif
  70 #endif
  71
  72 #endif /* CONFIG_RAMBOOT_PBL */
  73
  74 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  75 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  76 /* Set 1M boot space */
  77 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  79                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  80 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  81 #endif
  82
  83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  84 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  85 #endif
  86
  87 /*
  88  * These can be toggled for performance analysis, otherwise use default.
  89  */
  90 #define CONFIG_SYS_CACHE_STASHING
  91 #define CONFIG_BTB              /* toggle branch predition */
  92 #ifdef CONFIG_DDR_ECC
  93 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  94 #endif
  95
  96 /*
  97  * Config the L3 Cache as L3 SRAM
  98  */
  99 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 100 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 101 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 102 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 103 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 104 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 105 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 106
 107 #define CONFIG_SYS_DCSRBAR      0xf0000000
 108 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 109
 110 /* EEPROM */
 111 #define CONFIG_SYS_I2C_EEPROM_NXID
 112 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 113
 114 /*
 115  * DDR Setup
 116  */
 117 #define CONFIG_VERY_BIG_RAM
 118 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 119 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 120 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 121 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 122 #define CONFIG_SYS_SPD_BUS_NUM  0
 123 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 124 #define SPD_EEPROM_ADDRESS1     0x51
 125 #define SPD_EEPROM_ADDRESS2     0x52
 126 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 127 #define CTRL_INTLV_PREFERED     cacheline
 128
 129 /*
 130  * IFC Definitions
 131  */
 132 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 133 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 134 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 135 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 136                                 + 0x8000000) | \
 137                                 CSPR_PORT_SIZE_16 | \
 138                                 CSPR_MSEL_NOR | \
 139                                 CSPR_V)
 140 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 141 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 142                                 CSPR_PORT_SIZE_16 | \
 143                                 CSPR_MSEL_NOR | \
 144                                 CSPR_V)
 145 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 146 /* NOR Flash Timing Params */
 147 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 148
 149 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 150                                 FTIM0_NOR_TEADC(0x5) | \
 151                                 FTIM0_NOR_TEAHC(0x5))
 152 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 153                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 154                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 155 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 156                                 FTIM2_NOR_TCH(0x4) | \
 157                                 FTIM2_NOR_TWPH(0x0E) | \
 158                                 FTIM2_NOR_TWP(0x1c))
 159 #define CONFIG_SYS_NOR_FTIM3    0x0
 160
 161 #define CONFIG_SYS_FLASH_QUIET_TEST
 162 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 163
 164 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 165 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 166 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 167
 168 #define CONFIG_SYS_FLASH_EMPTY_INFO
 169 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 170                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 171
 172 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 173 #define QIXIS_BASE                      0xffdf0000
 174 #define QIXIS_LBMAP_SWITCH              6
 175 #define QIXIS_LBMAP_MASK                0x0f
 176 #define QIXIS_LBMAP_SHIFT               0
 177 #define QIXIS_LBMAP_DFLTBANK            0x00
 178 #define QIXIS_LBMAP_ALTBANK             0x04
 179 #define QIXIS_LBMAP_NAND                0x09
 180 #define QIXIS_LBMAP_SD                  0x00
 181 #define QIXIS_RCW_SRC_NAND              0x104
 182 #define QIXIS_RCW_SRC_SD                0x040
 183 #define QIXIS_RST_CTL_RESET             0x83
 184 #define QIXIS_RST_FORCE_MEM             0x1
 185 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 186 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 187 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 188 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 189
 190 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 191 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 192                                 | CSPR_PORT_SIZE_8 \
 193                                 | CSPR_MSEL_GPCM \
 194                                 | CSPR_V)
 195 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 196 #define CONFIG_SYS_CSOR3        0x0
 197 /* QIXIS Timing parameters for IFC CS3 */
 198 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 199                                         FTIM0_GPCM_TEADC(0x0e) | \
 200                                         FTIM0_GPCM_TEAHC(0x0e))
 201 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 202                                         FTIM1_GPCM_TRAD(0x3f))
 203 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 204                                         FTIM2_GPCM_TCH(0x8) | \
 205                                         FTIM2_GPCM_TWP(0x1f))
 206 #define CONFIG_SYS_CS3_FTIM3            0x0
 207
 208 /* NAND Flash on IFC */
 209 #define CONFIG_SYS_NAND_BASE            0xff800000
 210 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 211
 212 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 213 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 214                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 215                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 216                                 | CSPR_V)
 217 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 218
 219 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 220                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 221                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 222                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 223                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 224                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 225                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 226
 227 /* ONFI NAND Flash mode0 Timing Params */
 228 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 229                                         FTIM0_NAND_TWP(0x18)    | \
 230                                         FTIM0_NAND_TWCHT(0x07)  | \
 231                                         FTIM0_NAND_TWH(0x0a))
 232 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 233                                         FTIM1_NAND_TWBE(0x39)   | \
 234                                         FTIM1_NAND_TRR(0x0e)    | \
 235                                         FTIM1_NAND_TRP(0x18))
 236 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 237                                         FTIM2_NAND_TREH(0x0a)   | \
 238                                         FTIM2_NAND_TWHRE(0x1e))
 239 #define CONFIG_SYS_NAND_FTIM3           0x0
 240
 241 #define CONFIG_SYS_NAND_DDR_LAW         11
 242 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 243 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 244
 245 #if defined(CONFIG_MTD_RAW_NAND)
 246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 263 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 264 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 265 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 266 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 267 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 268 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 269 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 270 #else
 271 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 272 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 273 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 280 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 281 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #endif
 296
 297 #if defined(CONFIG_RAMBOOT_PBL)
 298 #define CONFIG_SYS_RAMBOOT
 299 #endif
 300
 301 #ifdef CONFIG_SPL_BUILD
 302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 303 #else
 304 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 305 #endif
 306
 307 #define CONFIG_HWCONFIG
 308
 309 /* define to use L1 as initial stack */
 310 #define CONFIG_L1_INIT_RAM
 311 #define CONFIG_SYS_INIT_RAM_LOCK
 312 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 315 /* The assembler doesn't like typecast */
 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 317                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 318                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 319 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 320 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 321                                                 GENERATED_GBL_DATA_SIZE)
 322 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 323 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 324
 325 /*
 326  * Serial Port
 327  */
 328 #define CONFIG_SYS_NS16550_SERIAL
 329 #define CONFIG_SYS_NS16550_REG_SIZE     1
 330 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 331 #define CONFIG_SYS_BAUDRATE_TABLE       \
 332         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 335 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 336 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 337
 338 /*
 339  * I2C
 340  */
 341
 342 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 343 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 344 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 345 #define I2C_MUX_CH_DEFAULT      0x8
 346
 347 #define I2C_MUX_CH_VOL_MONITOR 0xa
 348
 349 /* Voltage monitor on channel 2*/
 350 #define I2C_VOL_MONITOR_ADDR           0x40
 351 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 352 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 353 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 354
 355 /* The lowest and highest voltage allowed for T208xQDS */
 356 #define VDD_MV_MIN                      819
 357 #define VDD_MV_MAX                      1212
 358
 359 /*
 360  * RapidIO
 361  */
 362 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 363 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 364 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 365 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 366 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 367 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 368 /*
 369  * for slave u-boot IMAGE instored in master memory space,
 370  * PHYS must be aligned based on the SIZE
 371  */
 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 376 /*
 377  * for slave UCODE and ENV instored in master memory space,
 378  * PHYS must be aligned based on the SIZE
 379  */
 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 383
 384 /* slave core release by master*/
 385 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 386 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 387
 388 /*
 389  * SRIO_PCIE_BOOT - SLAVE
 390  */
 391 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 393 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 394                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 395 #endif
 396
 397 /*
 398  * eSPI - Enhanced SPI
 399  */
 400
 401 /*
 402  * General PCI
 403  * Memory space is mapped 1-1, but I/O space must start from 0.
 404  */
 405 #define CONFIG_PCIE1            /* PCIE controller 1 */
 406 #define CONFIG_PCIE2            /* PCIE controller 2 */
 407 #define CONFIG_PCIE3            /* PCIE controller 3 */
 408 #define CONFIG_PCIE4            /* PCIE controller 4 */
 409 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 410 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 411 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 412 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 413 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 414
 415 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 416 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 417 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 418 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 419 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 420
 421 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 422 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 423 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 424 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 425 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 426
 427 /* controller 4, Base address 203000 */
 428 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 429 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 430 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 431
 432 #ifdef CONFIG_PCI
 433 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 434 #endif
 435
 436 /* Qman/Bman */
 437 #ifndef CONFIG_NOBQFMAN
 438 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 439 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 440 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 441 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 442 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 443 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 444 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 445 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 446 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 447                                         CONFIG_SYS_BMAN_CENA_SIZE)
 448 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 449 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 450 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 451 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 452 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 453 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 454 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 455 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 456 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 457 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 458 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 459                                         CONFIG_SYS_QMAN_CENA_SIZE)
 460 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 461 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 462
 463 #define CONFIG_SYS_DPAA_FMAN
 464 #define CONFIG_SYS_DPAA_PME
 465 #define CONFIG_SYS_PMAN
 466 #define CONFIG_SYS_DPAA_DCE
 467 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 468 #define CONFIG_SYS_INTERLAKEN
 469
 470 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 471 #endif /* CONFIG_NOBQFMAN */
 472
 473 #ifdef CONFIG_SYS_DPAA_FMAN
 474 #define RGMII_PHY1_ADDR 0x1
 475 #define RGMII_PHY2_ADDR 0x2
 476 #define FM1_10GEC1_PHY_ADDR       0x3
 477 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 478 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 479 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 480 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 481 #endif
 482
 483 #ifdef CONFIG_FMAN_ENET
 484 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 485 #endif
 486
 487 /*
 488  * SATA
 489  */
 490 #ifdef CONFIG_FSL_SATA_V2
 491 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 492 #define CONFIG_SATA1
 493 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 494 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 495 #define CONFIG_SATA2
 496 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 497 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 498 #define CONFIG_LBA48
 499 #endif
 500
 501 /*
 502  * USB
 503  */
 504 #ifdef CONFIG_USB_EHCI_HCD
 505 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 506 #define CONFIG_HAS_FSL_DR_USB
 507 #endif
 508
 509 /*
 510  * SDHC
 511  */
 512 #ifdef CONFIG_MMC
 513 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 514 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 515 #endif
 516
 517 /*
 518  * Dynamic MTD Partition support with mtdparts
 519  */
 520
 521 /*
 522  * Environment
 523  */
 524 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 525 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 526
 527 /*
 528  * Miscellaneous configurable options
 529  */
 530
 531 /*
 532  * For booting Linux, the board info and command line data
 533  * have to be in the first 64 MB of memory, since this is
 534  * the maximum mapped by the Linux kernel during initialization.
 535  */
 536 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 537 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 538
 539 /*
 540  * Environment Configuration
 541  */
 542 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 543 #define CONFIG_BOOTFILE  "uImage"
 544 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 545
 546 #define __USB_PHY_TYPE          utmi
 547
 548 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 549         "hwconfig=fsl_ddr:"                                     \
 550         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 551         "bank_intlv=auto;"                                      \
 552         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 553         "netdev=eth0\0"                                         \
 554         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 555         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 556         "tftpflash=tftpboot $loadaddr $uboot && "               \
 557         "protect off $ubootaddr +$filesize && "                 \
 558         "erase $ubootaddr +$filesize && "                       \
 559         "cp.b $loadaddr $ubootaddr $filesize && "               \
 560         "protect on $ubootaddr +$filesize && "                  \
 561         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 562         "consoledev=ttyS0\0"                                    \
 563         "ramdiskaddr=2000000\0"                                 \
 564         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 565         "fdtaddr=1e00000\0"                                     \
 566         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 567         "bdev=sda3\0"
 568
 569 /*
 570  * For emulation this causes u-boot to jump to the start of the
 571  * proof point app code automatically
 572  */
 573 #define PROOF_POINTS                            \
 574         "setenv bootargs root=/dev/$bdev rw "           \
 575         "console=$consoledev,$baudrate $othbootargs;"   \
 576         "cpu 1 release 0x29000000 - - -;"               \
 577         "cpu 2 release 0x29000000 - - -;"               \
 578         "cpu 3 release 0x29000000 - - -;"               \
 579         "cpu 4 release 0x29000000 - - -;"               \
 580         "cpu 5 release 0x29000000 - - -;"               \
 581         "cpu 6 release 0x29000000 - - -;"               \
 582         "cpu 7 release 0x29000000 - - -;"               \
 583         "go 0x29000000"
 584
 585 #define HVBOOT                          \
 586         "setenv bootargs config-addr=0x60000000; "      \
 587         "bootm 0x01000000 - 0x00f00000"
 588
 589 #define ALU                             \
 590         "setenv bootargs root=/dev/$bdev rw "           \
 591         "console=$consoledev,$baudrate $othbootargs;"   \
 592         "cpu 1 release 0x01000000 - - -;"               \
 593         "cpu 2 release 0x01000000 - - -;"               \
 594         "cpu 3 release 0x01000000 - - -;"               \
 595         "cpu 4 release 0x01000000 - - -;"               \
 596         "cpu 5 release 0x01000000 - - -;"               \
 597         "cpu 6 release 0x01000000 - - -;"               \
 598         "cpu 7 release 0x01000000 - - -;"               \
 599         "go 0x01000000"
 600
 601 #include <asm/fsl_secure_boot.h>
 602
 603 #endif  /* __T208xQDS_H */