include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_MTD_RAW_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #if defined(CONFIG_ARCH_T2080)
  51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_SPIFLASH
  56 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  57 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #if defined(CONFIG_ARCH_T2080)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  67 #endif
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_ARCH_T2080)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  81 #endif
  82 #endif
  83
  84 #endif /* CONFIG_RAMBOOT_PBL */
  85
  86 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  88 /* Set 1M boot space */
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  91                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  93 #endif
  94
  95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  96 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  97 #endif
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_SYS_CACHE_STASHING
 103 #define CONFIG_BTB              /* toggle branch predition */
 104 #ifdef CONFIG_DDR_ECC
 105 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 106 #endif
 107
 108 #ifndef __ASSEMBLY__
 109 unsigned long get_board_sys_clk(void);
 110 #endif
 111
 112 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 113
 114 /*
 115  * Config the L3 Cache as L3 SRAM
 116  */
 117 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 118 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 119 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 120 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 121 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 122 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 123 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 124
 125 #define CONFIG_SYS_DCSRBAR      0xf0000000
 126 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 127
 128 /* EEPROM */
 129 #define CONFIG_SYS_I2C_EEPROM_NXID
 130 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 131
 132 /*
 133  * DDR Setup
 134  */
 135 #define CONFIG_VERY_BIG_RAM
 136 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 137 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 138 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 139 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 140 #define CONFIG_SYS_SPD_BUS_NUM  0
 141 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 142 #define SPD_EEPROM_ADDRESS1     0x51
 143 #define SPD_EEPROM_ADDRESS2     0x52
 144 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 145 #define CTRL_INTLV_PREFERED     cacheline
 146
 147 /*
 148  * IFC Definitions
 149  */
 150 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 151 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 152 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 153 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 154                                 + 0x8000000) | \
 155                                 CSPR_PORT_SIZE_16 | \
 156                                 CSPR_MSEL_NOR | \
 157                                 CSPR_V)
 158 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 159 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 160                                 CSPR_PORT_SIZE_16 | \
 161                                 CSPR_MSEL_NOR | \
 162                                 CSPR_V)
 163 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 164 /* NOR Flash Timing Params */
 165 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 166
 167 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 168                                 FTIM0_NOR_TEADC(0x5) | \
 169                                 FTIM0_NOR_TEAHC(0x5))
 170 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 171                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 172                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 173 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 174                                 FTIM2_NOR_TCH(0x4) | \
 175                                 FTIM2_NOR_TWPH(0x0E) | \
 176                                 FTIM2_NOR_TWP(0x1c))
 177 #define CONFIG_SYS_NOR_FTIM3    0x0
 178
 179 #define CONFIG_SYS_FLASH_QUIET_TEST
 180 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 184 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 185 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 186
 187 #define CONFIG_SYS_FLASH_EMPTY_INFO
 188 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 189                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 190
 191 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 192 #define QIXIS_BASE                      0xffdf0000
 193 #define QIXIS_LBMAP_SWITCH              6
 194 #define QIXIS_LBMAP_MASK                0x0f
 195 #define QIXIS_LBMAP_SHIFT               0
 196 #define QIXIS_LBMAP_DFLTBANK            0x00
 197 #define QIXIS_LBMAP_ALTBANK             0x04
 198 #define QIXIS_LBMAP_NAND                0x09
 199 #define QIXIS_LBMAP_SD                  0x00
 200 #define QIXIS_RCW_SRC_NAND              0x104
 201 #define QIXIS_RCW_SRC_SD                0x040
 202 #define QIXIS_RST_CTL_RESET             0x83
 203 #define QIXIS_RST_FORCE_MEM             0x1
 204 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 205 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 206 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 207 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 208
 209 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 210 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 211                                 | CSPR_PORT_SIZE_8 \
 212                                 | CSPR_MSEL_GPCM \
 213                                 | CSPR_V)
 214 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 215 #define CONFIG_SYS_CSOR3        0x0
 216 /* QIXIS Timing parameters for IFC CS3 */
 217 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 218                                         FTIM0_GPCM_TEADC(0x0e) | \
 219                                         FTIM0_GPCM_TEAHC(0x0e))
 220 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 221                                         FTIM1_GPCM_TRAD(0x3f))
 222 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 223                                         FTIM2_GPCM_TCH(0x8) | \
 224                                         FTIM2_GPCM_TWP(0x1f))
 225 #define CONFIG_SYS_CS3_FTIM3            0x0
 226
 227 /* NAND Flash on IFC */
 228 #define CONFIG_NAND_FSL_IFC
 229 #define CONFIG_SYS_NAND_BASE            0xff800000
 230 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 231
 232 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 233 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 234                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 235                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 236                                 | CSPR_V)
 237 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 238
 239 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 240                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 241                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 242                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 243                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 244                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 245                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 246
 247 #define CONFIG_SYS_NAND_ONFI_DETECTION
 248
 249 /* ONFI NAND Flash mode0 Timing Params */
 250 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 251                                         FTIM0_NAND_TWP(0x18)    | \
 252                                         FTIM0_NAND_TWCHT(0x07)  | \
 253                                         FTIM0_NAND_TWH(0x0a))
 254 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 255                                         FTIM1_NAND_TWBE(0x39)   | \
 256                                         FTIM1_NAND_TRR(0x0e)    | \
 257                                         FTIM1_NAND_TRP(0x18))
 258 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 259                                         FTIM2_NAND_TREH(0x0a)   | \
 260                                         FTIM2_NAND_TWHRE(0x1e))
 261 #define CONFIG_SYS_NAND_FTIM3           0x0
 262
 263 #define CONFIG_SYS_NAND_DDR_LAW         11
 264 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 265 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 266 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 267
 268 #if defined(CONFIG_MTD_RAW_NAND)
 269 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 270 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 277 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 278 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 279 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 280 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 281 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 282 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 283 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 284 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 285 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 286 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 287 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 288 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 289 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 290 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 291 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 292 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 293 #else
 294 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 295 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 296 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 297 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 298 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 299 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 300 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 301 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 302 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 303 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 304 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 305 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 306 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 307 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 308 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 309 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 310 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 311 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 312 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 313 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 314 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 315 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 316 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 317 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 318 #endif
 319
 320 #if defined(CONFIG_RAMBOOT_PBL)
 321 #define CONFIG_SYS_RAMBOOT
 322 #endif
 323
 324 #ifdef CONFIG_SPL_BUILD
 325 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 326 #else
 327 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 328 #endif
 329
 330 #define CONFIG_HWCONFIG
 331
 332 /* define to use L1 as initial stack */
 333 #define CONFIG_L1_INIT_RAM
 334 #define CONFIG_SYS_INIT_RAM_LOCK
 335 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 336 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 337 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 338 /* The assembler doesn't like typecast */
 339 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 340                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 341                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 342 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 343 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 344                                                 GENERATED_GBL_DATA_SIZE)
 345 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 346 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 347 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 348
 349 /*
 350  * Serial Port
 351  */
 352 #define CONFIG_SYS_NS16550_SERIAL
 353 #define CONFIG_SYS_NS16550_REG_SIZE     1
 354 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 355 #define CONFIG_SYS_BAUDRATE_TABLE       \
 356         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 359 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 360 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 361
 362 /*
 363  * I2C
 364  */
 365
 366 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 367 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 368 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 369 #define I2C_MUX_CH_DEFAULT      0x8
 370
 371 #define I2C_MUX_CH_VOL_MONITOR 0xa
 372
 373 /* Voltage monitor on channel 2*/
 374 #define I2C_VOL_MONITOR_ADDR           0x40
 375 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 376 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 377 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 378
 379 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 380 #ifndef CONFIG_SPL_BUILD
 381 #define CONFIG_VID
 382 #endif
 383 #define CONFIG_VOL_MONITOR_IR36021_SET
 384 #define CONFIG_VOL_MONITOR_IR36021_READ
 385 /* The lowest and highest voltage allowed for T208xQDS */
 386 #define VDD_MV_MIN                      819
 387 #define VDD_MV_MAX                      1212
 388
 389 /*
 390  * RapidIO
 391  */
 392 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 393 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 394 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 395 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 396 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 397 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 398 /*
 399  * for slave u-boot IMAGE instored in master memory space,
 400  * PHYS must be aligned based on the SIZE
 401  */
 402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 404 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 405 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 406 /*
 407  * for slave UCODE and ENV instored in master memory space,
 408  * PHYS must be aligned based on the SIZE
 409  */
 410 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 411 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 412 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 413
 414 /* slave core release by master*/
 415 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 416 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 417
 418 /*
 419  * SRIO_PCIE_BOOT - SLAVE
 420  */
 421 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 422 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 423 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 424                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 425 #endif
 426
 427 /*
 428  * eSPI - Enhanced SPI
 429  */
 430
 431 /*
 432  * General PCI
 433  * Memory space is mapped 1-1, but I/O space must start from 0.
 434  */
 435 #define CONFIG_PCIE1            /* PCIE controller 1 */
 436 #define CONFIG_PCIE2            /* PCIE controller 2 */
 437 #define CONFIG_PCIE3            /* PCIE controller 3 */
 438 #define CONFIG_PCIE4            /* PCIE controller 4 */
 439 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 440 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 441 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 442 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 443 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 444 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 445
 446 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 447 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 448 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 449 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 450 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 451
 452 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 453 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 454 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 455 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 456 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 457
 458 /* controller 4, Base address 203000 */
 459 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 460 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 461 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 462
 463 #ifdef CONFIG_PCI
 464 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 465 #endif
 466
 467 /* Qman/Bman */
 468 #ifndef CONFIG_NOBQFMAN
 469 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 470 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 471 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 472 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 473 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 474 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 475 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 476 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 477 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 478                                         CONFIG_SYS_BMAN_CENA_SIZE)
 479 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 480 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 481 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 482 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 483 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 484 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 485 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 486 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 487 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 488 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 489 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 490                                         CONFIG_SYS_QMAN_CENA_SIZE)
 491 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 492 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 493
 494 #define CONFIG_SYS_DPAA_FMAN
 495 #define CONFIG_SYS_DPAA_PME
 496 #define CONFIG_SYS_PMAN
 497 #define CONFIG_SYS_DPAA_DCE
 498 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 499 #define CONFIG_SYS_INTERLAKEN
 500
 501 /* Default address of microcode for the Linux Fman driver */
 502 #if defined(CONFIG_SPIFLASH)
 503 /*
 504  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 505  * env, so we got 0x110000.
 506  */
 507 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 508 #elif defined(CONFIG_SDCARD)
 509 /*
 510  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 511  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 512  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 513  */
 514 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 515 #elif defined(CONFIG_MTD_RAW_NAND)
 516 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 517 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 518 /*
 519  * Slave has no ucode locally, it can fetch this from remote. When implementing
 520  * in two corenet boards, slave's ucode could be stored in master's memory
 521  * space, the address can be mapped from slave TLB->slave LAW->
 522  * slave SRIO or PCIE outbound window->master inbound window->
 523  * master LAW->the ucode address in master's memory space.
 524  */
 525 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 526 #else
 527 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 528 #endif
 529 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 530 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 531 #endif /* CONFIG_NOBQFMAN */
 532
 533 #ifdef CONFIG_SYS_DPAA_FMAN
 534 #define RGMII_PHY1_ADDR 0x1
 535 #define RGMII_PHY2_ADDR 0x2
 536 #define FM1_10GEC1_PHY_ADDR       0x3
 537 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 538 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 539 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 540 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 541 #endif
 542
 543 #ifdef CONFIG_FMAN_ENET
 544 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 545 #endif
 546
 547 /*
 548  * SATA
 549  */
 550 #ifdef CONFIG_FSL_SATA_V2
 551 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 552 #define CONFIG_SATA1
 553 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 554 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 555 #define CONFIG_SATA2
 556 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 557 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 558 #define CONFIG_LBA48
 559 #endif
 560
 561 /*
 562  * USB
 563  */
 564 #ifdef CONFIG_USB_EHCI_HCD
 565 #define CONFIG_USB_EHCI_FSL
 566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 567 #define CONFIG_HAS_FSL_DR_USB
 568 #endif
 569
 570 /*
 571  * SDHC
 572  */
 573 #ifdef CONFIG_MMC
 574 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 575 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 576 #endif
 577
 578 /*
 579  * Dynamic MTD Partition support with mtdparts
 580  */
 581
 582 /*
 583  * Environment
 584  */
 585 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 586 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 587
 588 /*
 589  * Miscellaneous configurable options
 590  */
 591 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 592
 593 /*
 594  * For booting Linux, the board info and command line data
 595  * have to be in the first 64 MB of memory, since this is
 596  * the maximum mapped by the Linux kernel during initialization.
 597  */
 598 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 599 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 600
 601 #ifdef CONFIG_CMD_KGDB
 602 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 603 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 604 #endif
 605
 606 /*
 607  * Environment Configuration
 608  */
 609 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 610 #define CONFIG_BOOTFILE  "uImage"
 611 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 612
 613 /* default location for tftp and bootm */
 614 #define CONFIG_LOADADDR         1000000
 615 #define __USB_PHY_TYPE          utmi
 616
 617 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 618         "hwconfig=fsl_ddr:"                                     \
 619         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 620         "bank_intlv=auto;"                                      \
 621         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 622         "netdev=eth0\0"                                         \
 623         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 624         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 625         "tftpflash=tftpboot $loadaddr $uboot && "               \
 626         "protect off $ubootaddr +$filesize && "                 \
 627         "erase $ubootaddr +$filesize && "                       \
 628         "cp.b $loadaddr $ubootaddr $filesize && "               \
 629         "protect on $ubootaddr +$filesize && "                  \
 630         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 631         "consoledev=ttyS0\0"                                    \
 632         "ramdiskaddr=2000000\0"                                 \
 633         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 634         "fdtaddr=1e00000\0"                                     \
 635         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 636         "bdev=sda3\0"
 637
 638 /*
 639  * For emulation this causes u-boot to jump to the start of the
 640  * proof point app code automatically
 641  */
 642 #define PROOF_POINTS                            \
 643         "setenv bootargs root=/dev/$bdev rw "           \
 644         "console=$consoledev,$baudrate $othbootargs;"   \
 645         "cpu 1 release 0x29000000 - - -;"               \
 646         "cpu 2 release 0x29000000 - - -;"               \
 647         "cpu 3 release 0x29000000 - - -;"               \
 648         "cpu 4 release 0x29000000 - - -;"               \
 649         "cpu 5 release 0x29000000 - - -;"               \
 650         "cpu 6 release 0x29000000 - - -;"               \
 651         "cpu 7 release 0x29000000 - - -;"               \
 652         "go 0x29000000"
 653
 654 #define HVBOOT                          \
 655         "setenv bootargs config-addr=0x60000000; "      \
 656         "bootm 0x01000000 - 0x00f00000"
 657
 658 #define ALU                             \
 659         "setenv bootargs root=/dev/$bdev rw "           \
 660         "console=$consoledev,$baudrate $othbootargs;"   \
 661         "cpu 1 release 0x01000000 - - -;"               \
 662         "cpu 2 release 0x01000000 - - -;"               \
 663         "cpu 3 release 0x01000000 - - -;"               \
 664         "cpu 4 release 0x01000000 - - -;"               \
 665         "cpu 5 release 0x01000000 - - -;"               \
 666         "cpu 6 release 0x01000000 - - -;"               \
 667         "cpu 7 release 0x01000000 - - -;"               \
 668         "go 0x01000000"
 669
 670 #define LINUXBOOTCOMMAND                                \
 671         "setenv bootargs root=/dev/ram rw "             \
 672         "console=$consoledev,$baudrate $othbootargs;"   \
 673         "setenv ramdiskaddr 0x02000000;"                \
 674         "setenv fdtaddr 0x00c00000;"                    \
 675         "setenv loadaddr 0x1000000;"                    \
 676         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 677
 678 #define HDBOOT                                  \
 679         "setenv bootargs root=/dev/$bdev rw "           \
 680         "console=$consoledev,$baudrate $othbootargs;"   \
 681         "tftp $loadaddr $bootfile;"                     \
 682         "tftp $fdtaddr $fdtfile;"                       \
 683         "bootm $loadaddr - $fdtaddr"
 684
 685 #define NFSBOOTCOMMAND                  \
 686         "setenv bootargs root=/dev/nfs rw "     \
 687         "nfsroot=$serverip:$rootpath "          \
 688         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 689         "console=$consoledev,$baudrate $othbootargs;"   \
 690         "tftp $loadaddr $bootfile;"             \
 691         "tftp $fdtaddr $fdtfile;"               \
 692         "bootm $loadaddr - $fdtaddr"
 693
 694 #define RAMBOOTCOMMAND                          \
 695         "setenv bootargs root=/dev/ram rw "             \
 696         "console=$consoledev,$baudrate $othbootargs;"   \
 697         "tftp $ramdiskaddr $ramdiskfile;"               \
 698         "tftp $loadaddr $bootfile;"                     \
 699         "tftp $fdtaddr $fdtfile;"                       \
 700         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 701
 702 #define CONFIG_BOOTCOMMAND              LINUXBOOTCOMMAND
 703
 704 #include <asm/fsl_secure_boot.h>
 705
 706 #endif  /* __T208xQDS_H */