include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_MTD_RAW_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #if defined(CONFIG_ARCH_T2080)
  51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_SPIFLASH
  56 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  57 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #if defined(CONFIG_ARCH_T2080)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  67 #endif
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_ARCH_T2080)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  81 #endif
  82 #endif
  83
  84 #endif /* CONFIG_RAMBOOT_PBL */
  85
  86 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  88 /* Set 1M boot space */
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  91                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  93 #endif
  94
  95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  96 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  97 #endif
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_SYS_CACHE_STASHING
 103 #define CONFIG_BTB              /* toggle branch predition */
 104 #define CONFIG_DDR_ECC
 105 #ifdef CONFIG_DDR_ECC
 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 107 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 108 #endif
 109
 110 #ifndef __ASSEMBLY__
 111 unsigned long get_board_sys_clk(void);
 112 unsigned long get_board_ddr_clk(void);
 113 #endif
 114
 115 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 116 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 117
 118 /*
 119  * Config the L3 Cache as L3 SRAM
 120  */
 121 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 122 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 123 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 124 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 125 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 126 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 127 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 128
 129 #define CONFIG_SYS_DCSRBAR      0xf0000000
 130 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 131
 132 /* EEPROM */
 133 #define CONFIG_SYS_I2C_EEPROM_NXID
 134 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 135
 136 /*
 137  * DDR Setup
 138  */
 139 #define CONFIG_VERY_BIG_RAM
 140 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 141 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 142 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 143 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 144 #define CONFIG_DDR_SPD
 145 #define CONFIG_SYS_SPD_BUS_NUM  0
 146 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 147 #define SPD_EEPROM_ADDRESS1     0x51
 148 #define SPD_EEPROM_ADDRESS2     0x52
 149 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 150 #define CTRL_INTLV_PREFERED     cacheline
 151
 152 /*
 153  * IFC Definitions
 154  */
 155 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 156 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 157 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 158 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 159                                 + 0x8000000) | \
 160                                 CSPR_PORT_SIZE_16 | \
 161                                 CSPR_MSEL_NOR | \
 162                                 CSPR_V)
 163 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 164 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 165                                 CSPR_PORT_SIZE_16 | \
 166                                 CSPR_MSEL_NOR | \
 167                                 CSPR_V)
 168 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 169 /* NOR Flash Timing Params */
 170 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 171
 172 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 173                                 FTIM0_NOR_TEADC(0x5) | \
 174                                 FTIM0_NOR_TEAHC(0x5))
 175 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 176                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 177                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 178 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 179                                 FTIM2_NOR_TCH(0x4) | \
 180                                 FTIM2_NOR_TWPH(0x0E) | \
 181                                 FTIM2_NOR_TWP(0x1c))
 182 #define CONFIG_SYS_NOR_FTIM3    0x0
 183
 184 #define CONFIG_SYS_FLASH_QUIET_TEST
 185 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 186
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 188 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 189 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 190 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 191
 192 #define CONFIG_SYS_FLASH_EMPTY_INFO
 193 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 194                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 195
 196 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 197 #define QIXIS_BASE                      0xffdf0000
 198 #define QIXIS_LBMAP_SWITCH              6
 199 #define QIXIS_LBMAP_MASK                0x0f
 200 #define QIXIS_LBMAP_SHIFT               0
 201 #define QIXIS_LBMAP_DFLTBANK            0x00
 202 #define QIXIS_LBMAP_ALTBANK             0x04
 203 #define QIXIS_LBMAP_NAND                0x09
 204 #define QIXIS_LBMAP_SD                  0x00
 205 #define QIXIS_RCW_SRC_NAND              0x104
 206 #define QIXIS_RCW_SRC_SD                0x040
 207 #define QIXIS_RST_CTL_RESET             0x83
 208 #define QIXIS_RST_FORCE_MEM             0x1
 209 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 210 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 211 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 212 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 213
 214 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 215 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 216                                 | CSPR_PORT_SIZE_8 \
 217                                 | CSPR_MSEL_GPCM \
 218                                 | CSPR_V)
 219 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 220 #define CONFIG_SYS_CSOR3        0x0
 221 /* QIXIS Timing parameters for IFC CS3 */
 222 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 223                                         FTIM0_GPCM_TEADC(0x0e) | \
 224                                         FTIM0_GPCM_TEAHC(0x0e))
 225 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 226                                         FTIM1_GPCM_TRAD(0x3f))
 227 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 228                                         FTIM2_GPCM_TCH(0x8) | \
 229                                         FTIM2_GPCM_TWP(0x1f))
 230 #define CONFIG_SYS_CS3_FTIM3            0x0
 231
 232 /* NAND Flash on IFC */
 233 #define CONFIG_NAND_FSL_IFC
 234 #define CONFIG_SYS_NAND_BASE            0xff800000
 235 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 236
 237 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 238 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 239                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 240                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 241                                 | CSPR_V)
 242 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 243
 244 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 245                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 246                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 247                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 248                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 249                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 250                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 251
 252 #define CONFIG_SYS_NAND_ONFI_DETECTION
 253
 254 /* ONFI NAND Flash mode0 Timing Params */
 255 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 256                                         FTIM0_NAND_TWP(0x18)    | \
 257                                         FTIM0_NAND_TWCHT(0x07)  | \
 258                                         FTIM0_NAND_TWH(0x0a))
 259 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 260                                         FTIM1_NAND_TWBE(0x39)   | \
 261                                         FTIM1_NAND_TRR(0x0e)    | \
 262                                         FTIM1_NAND_TRP(0x18))
 263 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 264                                         FTIM2_NAND_TREH(0x0a)   | \
 265                                         FTIM2_NAND_TWHRE(0x1e))
 266 #define CONFIG_SYS_NAND_FTIM3           0x0
 267
 268 #define CONFIG_SYS_NAND_DDR_LAW         11
 269 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 270 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 271 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 272
 273 #if defined(CONFIG_MTD_RAW_NAND)
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 282 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 283 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 284 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 285 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 286 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 287 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 288 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 289 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 290 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 291 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 292 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 293 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 294 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 295 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 296 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 297 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 298 #else
 299 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 300 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 301 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 302 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 303 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 304 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 305 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 306 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 307 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 308 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 309 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 310 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 311 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 312 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 313 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 314 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 315 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 316 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 317 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 318 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 319 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 320 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 321 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 322 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 323 #endif
 324
 325 #if defined(CONFIG_RAMBOOT_PBL)
 326 #define CONFIG_SYS_RAMBOOT
 327 #endif
 328
 329 #ifdef CONFIG_SPL_BUILD
 330 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 331 #else
 332 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 333 #endif
 334
 335 #define CONFIG_HWCONFIG
 336
 337 /* define to use L1 as initial stack */
 338 #define CONFIG_L1_INIT_RAM
 339 #define CONFIG_SYS_INIT_RAM_LOCK
 340 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 342 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 343 /* The assembler doesn't like typecast */
 344 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 345                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 346                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 347 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 348 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 349                                                 GENERATED_GBL_DATA_SIZE)
 350 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 351 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 352 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 353
 354 /*
 355  * Serial Port
 356  */
 357 #define CONFIG_SYS_NS16550_SERIAL
 358 #define CONFIG_SYS_NS16550_REG_SIZE     1
 359 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 360 #define CONFIG_SYS_BAUDRATE_TABLE       \
 361         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 362 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 363 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 364 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 365 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 366
 367 /*
 368  * I2C
 369  */
 370 #if !CONFIG_IS_ENABLED(DM_I2C)
 371 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 372 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 373 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 374 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 375 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 376 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 377 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 378 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 379 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 380 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 381 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 382 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 383 #endif
 384
 385 #define CONFIG_SYS_I2C_FSL
 386
 387 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 388 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 389 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 390 #define I2C_MUX_CH_DEFAULT      0x8
 391
 392 #define I2C_MUX_CH_VOL_MONITOR 0xa
 393
 394 /* Voltage monitor on channel 2*/
 395 #define I2C_VOL_MONITOR_ADDR           0x40
 396 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 397 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 398 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 399
 400 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 401 #ifndef CONFIG_SPL_BUILD
 402 #define CONFIG_VID
 403 #endif
 404 #define CONFIG_VOL_MONITOR_IR36021_SET
 405 #define CONFIG_VOL_MONITOR_IR36021_READ
 406 /* The lowest and highest voltage allowed for T208xQDS */
 407 #define VDD_MV_MIN                      819
 408 #define VDD_MV_MAX                      1212
 409
 410 /*
 411  * RapidIO
 412  */
 413 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 414 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 415 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 416 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 417 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 418 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 419 /*
 420  * for slave u-boot IMAGE instored in master memory space,
 421  * PHYS must be aligned based on the SIZE
 422  */
 423 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 424 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 425 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 427 /*
 428  * for slave UCODE and ENV instored in master memory space,
 429  * PHYS must be aligned based on the SIZE
 430  */
 431 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 432 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 433 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 434
 435 /* slave core release by master*/
 436 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 437 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 438
 439 /*
 440  * SRIO_PCIE_BOOT - SLAVE
 441  */
 442 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 443 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 444 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 445                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 446 #endif
 447
 448 /*
 449  * eSPI - Enhanced SPI
 450  */
 451
 452 /*
 453  * General PCI
 454  * Memory space is mapped 1-1, but I/O space must start from 0.
 455  */
 456 #define CONFIG_PCIE1            /* PCIE controller 1 */
 457 #define CONFIG_PCIE2            /* PCIE controller 2 */
 458 #define CONFIG_PCIE3            /* PCIE controller 3 */
 459 #define CONFIG_PCIE4            /* PCIE controller 4 */
 460 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 461 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 462 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 463 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 464 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 465 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 466
 467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 468 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 469 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 470 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 471 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 472
 473 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 474 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 475 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 476 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 477 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 478
 479 /* controller 4, Base address 203000 */
 480 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 481 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 482 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 483
 484 #ifdef CONFIG_PCI
 485 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 486 #endif
 487
 488 /* Qman/Bman */
 489 #ifndef CONFIG_NOBQFMAN
 490 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 491 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 492 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 493 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 494 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 495 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 496 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 497 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 498 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 499                                         CONFIG_SYS_BMAN_CENA_SIZE)
 500 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 501 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 502 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 503 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 504 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 505 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 506 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 507 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 508 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 509 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 510 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 511                                         CONFIG_SYS_QMAN_CENA_SIZE)
 512 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 513 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 514
 515 #define CONFIG_SYS_DPAA_FMAN
 516 #define CONFIG_SYS_DPAA_PME
 517 #define CONFIG_SYS_PMAN
 518 #define CONFIG_SYS_DPAA_DCE
 519 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 520 #define CONFIG_SYS_INTERLAKEN
 521
 522 /* Default address of microcode for the Linux Fman driver */
 523 #if defined(CONFIG_SPIFLASH)
 524 /*
 525  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 526  * env, so we got 0x110000.
 527  */
 528 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 529 #elif defined(CONFIG_SDCARD)
 530 /*
 531  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 532  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 533  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 534  */
 535 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 536 #elif defined(CONFIG_MTD_RAW_NAND)
 537 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 538 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 539 /*
 540  * Slave has no ucode locally, it can fetch this from remote. When implementing
 541  * in two corenet boards, slave's ucode could be stored in master's memory
 542  * space, the address can be mapped from slave TLB->slave LAW->
 543  * slave SRIO or PCIE outbound window->master inbound window->
 544  * master LAW->the ucode address in master's memory space.
 545  */
 546 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 547 #else
 548 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 549 #endif
 550 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 551 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 552 #endif /* CONFIG_NOBQFMAN */
 553
 554 #ifdef CONFIG_SYS_DPAA_FMAN
 555 #define RGMII_PHY1_ADDR 0x1
 556 #define RGMII_PHY2_ADDR 0x2
 557 #define FM1_10GEC1_PHY_ADDR       0x3
 558 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 559 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 560 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 561 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 562 #endif
 563
 564 #ifdef CONFIG_FMAN_ENET
 565 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 566 #endif
 567
 568 /*
 569  * SATA
 570  */
 571 #ifdef CONFIG_FSL_SATA_V2
 572 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 573 #define CONFIG_SATA1
 574 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 575 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 576 #define CONFIG_SATA2
 577 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 578 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 579 #define CONFIG_LBA48
 580 #endif
 581
 582 /*
 583  * USB
 584  */
 585 #ifdef CONFIG_USB_EHCI_HCD
 586 #define CONFIG_USB_EHCI_FSL
 587 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 588 #define CONFIG_HAS_FSL_DR_USB
 589 #endif
 590
 591 /*
 592  * SDHC
 593  */
 594 #ifdef CONFIG_MMC
 595 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 596 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 597 #endif
 598
 599 /*
 600  * Dynamic MTD Partition support with mtdparts
 601  */
 602
 603 /*
 604  * Environment
 605  */
 606 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 607 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 608
 609 /*
 610  * Miscellaneous configurable options
 611  */
 612 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 613
 614 /*
 615  * For booting Linux, the board info and command line data
 616  * have to be in the first 64 MB of memory, since this is
 617  * the maximum mapped by the Linux kernel during initialization.
 618  */
 619 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 620 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 621
 622 #ifdef CONFIG_CMD_KGDB
 623 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 624 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 625 #endif
 626
 627 /*
 628  * Environment Configuration
 629  */
 630 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 631 #define CONFIG_BOOTFILE  "uImage"
 632 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 633
 634 /* default location for tftp and bootm */
 635 #define CONFIG_LOADADDR         1000000
 636 #define __USB_PHY_TYPE          utmi
 637
 638 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 639         "hwconfig=fsl_ddr:"                                     \
 640         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 641         "bank_intlv=auto;"                                      \
 642         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 643         "netdev=eth0\0"                                         \
 644         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 645         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 646         "tftpflash=tftpboot $loadaddr $uboot && "               \
 647         "protect off $ubootaddr +$filesize && "                 \
 648         "erase $ubootaddr +$filesize && "                       \
 649         "cp.b $loadaddr $ubootaddr $filesize && "               \
 650         "protect on $ubootaddr +$filesize && "                  \
 651         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 652         "consoledev=ttyS0\0"                                    \
 653         "ramdiskaddr=2000000\0"                                 \
 654         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 655         "fdtaddr=1e00000\0"                                     \
 656         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 657         "bdev=sda3\0"
 658
 659 /*
 660  * For emulation this causes u-boot to jump to the start of the
 661  * proof point app code automatically
 662  */
 663 #define CONFIG_PROOF_POINTS                             \
 664         "setenv bootargs root=/dev/$bdev rw "           \
 665         "console=$consoledev,$baudrate $othbootargs;"   \
 666         "cpu 1 release 0x29000000 - - -;"               \
 667         "cpu 2 release 0x29000000 - - -;"               \
 668         "cpu 3 release 0x29000000 - - -;"               \
 669         "cpu 4 release 0x29000000 - - -;"               \
 670         "cpu 5 release 0x29000000 - - -;"               \
 671         "cpu 6 release 0x29000000 - - -;"               \
 672         "cpu 7 release 0x29000000 - - -;"               \
 673         "go 0x29000000"
 674
 675 #define CONFIG_HVBOOT                           \
 676         "setenv bootargs config-addr=0x60000000; "      \
 677         "bootm 0x01000000 - 0x00f00000"
 678
 679 #define CONFIG_ALU                              \
 680         "setenv bootargs root=/dev/$bdev rw "           \
 681         "console=$consoledev,$baudrate $othbootargs;"   \
 682         "cpu 1 release 0x01000000 - - -;"               \
 683         "cpu 2 release 0x01000000 - - -;"               \
 684         "cpu 3 release 0x01000000 - - -;"               \
 685         "cpu 4 release 0x01000000 - - -;"               \
 686         "cpu 5 release 0x01000000 - - -;"               \
 687         "cpu 6 release 0x01000000 - - -;"               \
 688         "cpu 7 release 0x01000000 - - -;"               \
 689         "go 0x01000000"
 690
 691 #define CONFIG_LINUX                            \
 692         "setenv bootargs root=/dev/ram rw "             \
 693         "console=$consoledev,$baudrate $othbootargs;"   \
 694         "setenv ramdiskaddr 0x02000000;"                \
 695         "setenv fdtaddr 0x00c00000;"                    \
 696         "setenv loadaddr 0x1000000;"                    \
 697         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 698
 699 #define CONFIG_HDBOOT                                   \
 700         "setenv bootargs root=/dev/$bdev rw "           \
 701         "console=$consoledev,$baudrate $othbootargs;"   \
 702         "tftp $loadaddr $bootfile;"                     \
 703         "tftp $fdtaddr $fdtfile;"                       \
 704         "bootm $loadaddr - $fdtaddr"
 705
 706 #define CONFIG_NFSBOOTCOMMAND                   \
 707         "setenv bootargs root=/dev/nfs rw "     \
 708         "nfsroot=$serverip:$rootpath "          \
 709         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 710         "console=$consoledev,$baudrate $othbootargs;"   \
 711         "tftp $loadaddr $bootfile;"             \
 712         "tftp $fdtaddr $fdtfile;"               \
 713         "bootm $loadaddr - $fdtaddr"
 714
 715 #define CONFIG_RAMBOOTCOMMAND                           \
 716         "setenv bootargs root=/dev/ram rw "             \
 717         "console=$consoledev,$baudrate $othbootargs;"   \
 718         "tftp $ramdiskaddr $ramdiskfile;"               \
 719         "tftp $loadaddr $bootfile;"                     \
 720         "tftp $fdtaddr $fdtfile;"                       \
 721         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 722
 723 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 724
 725 #include <asm/fsl_secure_boot.h>
 726
 727 #endif  /* __T208xQDS_H */