include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * T104x RDB board configuration file
  11  */
  12 #include <asm/config_mpc85xx.h>
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15
  16 #ifndef CONFIG_SECURE_BOOT
  17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  18 #else
  19 #define CONFIG_SYS_FSL_PBL_PBI \
  20                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  21 #endif
  22
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  25 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  26 #define CONFIG_SPL_PAD_TO               0x40000
  27 #define CONFIG_SPL_MAX_SIZE             0x28000
  28 #ifdef CONFIG_SPL_BUILD
  29 #define CONFIG_SPL_SKIP_RELOCATE
  30 #define CONFIG_SPL_COMMON_INIT_DDR
  31 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  32 #endif
  33 #define RESET_VECTOR_OFFSET             0x27FFC
  34 #define BOOT_PAGE_OFFSET                0x27000
  35
  36 #ifdef CONFIG_NAND
  37 #ifdef CONFIG_SECURE_BOOT
  38 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  39 /*
  40  * HDR would be appended at end of image and copied to DDR along
  41  * with U-Boot image.
  42  */
  43 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  44                                          CONFIG_U_BOOT_HDR_SIZE)
  45 #else
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #endif
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  52 #ifdef CONFIG_TARGET_T1040RDB
  53 #define CONFIG_SYS_FSL_PBL_RCW \
  54 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  55 #endif
  56 #ifdef CONFIG_TARGET_T1042RDB_PI
  57 #define CONFIG_SYS_FSL_PBL_RCW \
  58 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  59 #endif
  60 #ifdef CONFIG_TARGET_T1042RDB
  61 #define CONFIG_SYS_FSL_PBL_RCW \
  62 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  63 #endif
  64 #ifdef CONFIG_TARGET_T1040D4RDB
  65 #define CONFIG_SYS_FSL_PBL_RCW \
  66 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  67 #endif
  68 #ifdef CONFIG_TARGET_T1042D4RDB
  69 #define CONFIG_SYS_FSL_PBL_RCW \
  70 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  71 #endif
  72 #define CONFIG_SPL_NAND_BOOT
  73 #endif
  74
  75 #ifdef CONFIG_SPIFLASH
  76 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  77 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  82 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  83 #ifndef CONFIG_SPL_BUILD
  84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  85 #endif
  86 #ifdef CONFIG_TARGET_T1040RDB
  87 #define CONFIG_SYS_FSL_PBL_RCW \
  88 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  89 #endif
  90 #ifdef CONFIG_TARGET_T1042RDB_PI
  91 #define CONFIG_SYS_FSL_PBL_RCW \
  92 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  93 #endif
  94 #ifdef CONFIG_TARGET_T1042RDB
  95 #define CONFIG_SYS_FSL_PBL_RCW \
  96 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  97 #endif
  98 #ifdef CONFIG_TARGET_T1040D4RDB
  99 #define CONFIG_SYS_FSL_PBL_RCW \
 100 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 101 #endif
 102 #ifdef CONFIG_TARGET_T1042D4RDB
 103 #define CONFIG_SYS_FSL_PBL_RCW \
 104 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 105 #endif
 106 #define CONFIG_SPL_SPI_BOOT
 107 #endif
 108
 109 #ifdef CONFIG_SDCARD
 110 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 111 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 112 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 113 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 114 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 115 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 116 #ifndef CONFIG_SPL_BUILD
 117 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 118 #endif
 119 #ifdef CONFIG_TARGET_T1040RDB
 120 #define CONFIG_SYS_FSL_PBL_RCW \
 121 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 122 #endif
 123 #ifdef CONFIG_TARGET_T1042RDB_PI
 124 #define CONFIG_SYS_FSL_PBL_RCW \
 125 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 126 #endif
 127 #ifdef CONFIG_TARGET_T1042RDB
 128 #define CONFIG_SYS_FSL_PBL_RCW \
 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 130 #endif
 131 #ifdef CONFIG_TARGET_T1040D4RDB
 132 #define CONFIG_SYS_FSL_PBL_RCW \
 133 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 134 #endif
 135 #ifdef CONFIG_TARGET_T1042D4RDB
 136 #define CONFIG_SYS_FSL_PBL_RCW \
 137 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 138 #endif
 139 #define CONFIG_SPL_MMC_BOOT
 140 #endif
 141
 142 #endif
 143
 144 /* High Level Configuration Options */
 145 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 146
 147 /* support deep sleep */
 148 #define CONFIG_DEEP_SLEEP
 149
 150 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 151 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 152 #endif
 153
 154 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 155 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 156 #define CONFIG_PCI_INDIRECT_BRIDGE
 157 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 158 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 159 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 160 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 161
 162 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 163 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 164
 165 #define CONFIG_ENV_OVERWRITE
 166
 167 #ifdef CONFIG_MTD_NOR_FLASH
 168 #define CONFIG_FLASH_CFI_DRIVER
 169 #define CONFIG_SYS_FLASH_CFI
 170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 171 #endif
 172
 173 #if defined(CONFIG_SPIFLASH)
 174 #define CONFIG_SYS_EXTRA_ENV_RELOC
 175 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 176 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 177 #define CONFIG_ENV_SECT_SIZE            0x10000
 178 #elif defined(CONFIG_SDCARD)
 179 #define CONFIG_SYS_EXTRA_ENV_RELOC
 180 #define CONFIG_SYS_MMC_ENV_DEV          0
 181 #define CONFIG_ENV_SIZE                 0x2000
 182 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 183 #elif defined(CONFIG_NAND)
 184 #ifdef CONFIG_SECURE_BOOT
 185 #define CONFIG_RAMBOOT_NAND
 186 #define CONFIG_BOOTSCRIPT_COPY_RAM
 187 #endif
 188 #define CONFIG_SYS_EXTRA_ENV_RELOC
 189 #define CONFIG_ENV_SIZE                 0x2000
 190 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 191 #else
 192 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 193 #define CONFIG_ENV_SIZE         0x2000
 194 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 195 #endif
 196
 197 #define CONFIG_SYS_CLK_FREQ     100000000
 198 #define CONFIG_DDR_CLK_FREQ     66666666
 199
 200 /*
 201  * These can be toggled for performance analysis, otherwise use default.
 202  */
 203 #define CONFIG_SYS_CACHE_STASHING
 204 #define CONFIG_BACKSIDE_L2_CACHE
 205 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 206 #define CONFIG_BTB                      /* toggle branch predition */
 207 #define CONFIG_DDR_ECC
 208 #ifdef CONFIG_DDR_ECC
 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 210 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 211 #endif
 212
 213 #define CONFIG_ENABLE_36BIT_PHYS
 214
 215 #define CONFIG_ADDR_MAP
 216 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 217
 218 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 219 #define CONFIG_SYS_MEMTEST_END          0x00400000
 220
 221 /*
 222  *  Config the L3 Cache as L3 SRAM
 223  */
 224 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 225 /*
 226  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 227  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 228  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 229  */
 230 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 231 #define CONFIG_SYS_L3_SIZE              256 << 10
 232 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 233 #ifdef CONFIG_RAMBOOT_PBL
 234 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 235 #endif
 236 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 237 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 238 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 239
 240 #define CONFIG_SYS_DCSRBAR              0xf0000000
 241 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 242
 243 /*
 244  * DDR Setup
 245  */
 246 #define CONFIG_VERY_BIG_RAM
 247 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 248 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 249
 250 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 251 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 252
 253 #define CONFIG_DDR_SPD
 254
 255 #define CONFIG_SYS_SPD_BUS_NUM  0
 256 #define SPD_EEPROM_ADDRESS      0x51
 257
 258 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 259
 260 /*
 261  * IFC Definitions
 262  */
 263 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 264 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 265
 266 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 267 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 268                                 CSPR_PORT_SIZE_16 | \
 269                                 CSPR_MSEL_NOR | \
 270                                 CSPR_V)
 271 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 272
 273 /*
 274  * TDM Definition
 275  */
 276 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 277
 278 /* NOR Flash Timing Params */
 279 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 280 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 281                                 FTIM0_NOR_TEADC(0x5) | \
 282                                 FTIM0_NOR_TEAHC(0x5))
 283 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 284                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 285                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 286 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 287                                 FTIM2_NOR_TCH(0x4) | \
 288                                 FTIM2_NOR_TWPH(0x0E) | \
 289                                 FTIM2_NOR_TWP(0x1c))
 290 #define CONFIG_SYS_NOR_FTIM3    0x0
 291
 292 #define CONFIG_SYS_FLASH_QUIET_TEST
 293 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 294
 295 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 296 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 297 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 298 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 299
 300 #define CONFIG_SYS_FLASH_EMPTY_INFO
 301 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 302
 303 /* CPLD on IFC */
 304 #define CPLD_LBMAP_MASK                 0x3F
 305 #define CPLD_BANK_SEL_MASK              0x07
 306 #define CPLD_BANK_OVERRIDE              0x40
 307 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 308 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 309 #define CPLD_LBMAP_RESET                0xFF
 310 #define CPLD_LBMAP_SHIFT                0x03
 311
 312 #if defined(CONFIG_TARGET_T1042RDB_PI)
 313 #define CPLD_DIU_SEL_DFP                0x80
 314 #elif defined(CONFIG_TARGET_T1042D4RDB)
 315 #define CPLD_DIU_SEL_DFP                0xc0
 316 #endif
 317
 318 #if defined(CONFIG_TARGET_T1040D4RDB)
 319 #define CPLD_INT_MASK_ALL               0xFF
 320 #define CPLD_INT_MASK_THERM             0x80
 321 #define CPLD_INT_MASK_DVI_DFP           0x40
 322 #define CPLD_INT_MASK_QSGMII1           0x20
 323 #define CPLD_INT_MASK_QSGMII2           0x10
 324 #define CPLD_INT_MASK_SGMI1             0x08
 325 #define CPLD_INT_MASK_SGMI2             0x04
 326 #define CPLD_INT_MASK_TDMR1             0x02
 327 #define CPLD_INT_MASK_TDMR2             0x01
 328 #endif
 329
 330 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 331 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 332 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 333 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 334                                 | CSPR_PORT_SIZE_8 \
 335                                 | CSPR_MSEL_GPCM \
 336                                 | CSPR_V)
 337 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 338 #define CONFIG_SYS_CSOR2        0x0
 339 /* CPLD Timing parameters for IFC CS2 */
 340 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 341                                         FTIM0_GPCM_TEADC(0x0e) | \
 342                                         FTIM0_GPCM_TEAHC(0x0e))
 343 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 344                                         FTIM1_GPCM_TRAD(0x1f))
 345 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 346                                         FTIM2_GPCM_TCH(0x8) | \
 347                                         FTIM2_GPCM_TWP(0x1f))
 348 #define CONFIG_SYS_CS2_FTIM3            0x0
 349
 350 /* NAND Flash on IFC */
 351 #define CONFIG_NAND_FSL_IFC
 352 #define CONFIG_SYS_NAND_BASE            0xff800000
 353 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 354
 355 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 356 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 357                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 358                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 359                                 | CSPR_V)
 360 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 361
 362 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 363                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 364                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 365                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 366                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 367                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 368                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 369
 370 #define CONFIG_SYS_NAND_ONFI_DETECTION
 371
 372 /* ONFI NAND Flash mode0 Timing Params */
 373 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 374                                         FTIM0_NAND_TWP(0x18)   | \
 375                                         FTIM0_NAND_TWCHT(0x07) | \
 376                                         FTIM0_NAND_TWH(0x0a))
 377 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 378                                         FTIM1_NAND_TWBE(0x39)  | \
 379                                         FTIM1_NAND_TRR(0x0e)   | \
 380                                         FTIM1_NAND_TRP(0x18))
 381 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 382                                         FTIM2_NAND_TREH(0x0a) | \
 383                                         FTIM2_NAND_TWHRE(0x1e))
 384 #define CONFIG_SYS_NAND_FTIM3           0x0
 385
 386 #define CONFIG_SYS_NAND_DDR_LAW         11
 387 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 388 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 389
 390 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 391
 392 #if defined(CONFIG_NAND)
 393 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 394 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 395 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 396 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 397 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 398 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 399 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 400 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 401 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 402 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 403 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 404 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 405 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 406 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 407 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 408 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 409 #else
 410 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 411 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 412 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 413 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 414 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 415 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 416 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 417 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 418 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 419 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 420 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 421 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 422 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 423 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 424 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 425 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 426 #endif
 427
 428 #ifdef CONFIG_SPL_BUILD
 429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 430 #else
 431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 432 #endif
 433
 434 #if defined(CONFIG_RAMBOOT_PBL)
 435 #define CONFIG_SYS_RAMBOOT
 436 #endif
 437
 438 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 439 #if defined(CONFIG_NAND)
 440 #define CONFIG_A008044_WORKAROUND
 441 #endif
 442 #endif
 443
 444 #define CONFIG_MISC_INIT_R
 445
 446 #define CONFIG_HWCONFIG
 447
 448 /* define to use L1 as initial stack */
 449 #define CONFIG_L1_INIT_RAM
 450 #define CONFIG_SYS_INIT_RAM_LOCK
 451 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 454 /* The assembler doesn't like typecast */
 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 456         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 457           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 458 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 459
 460 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 461                                         GENERATED_GBL_DATA_SIZE)
 462 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 463
 464 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 465 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 466
 467 /* Serial Port - controlled on board with jumper J8
 468  * open - index 2
 469  * shorted - index 1
 470  */
 471 #define CONFIG_SYS_NS16550_SERIAL
 472 #define CONFIG_SYS_NS16550_REG_SIZE     1
 473 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 474
 475 #define CONFIG_SYS_BAUDRATE_TABLE       \
 476         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 477
 478 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 479 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 480 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 481 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 482
 483 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 484 /* Video */
 485 #define CONFIG_FSL_DIU_FB
 486
 487 #ifdef CONFIG_FSL_DIU_FB
 488 #define CONFIG_FSL_DIU_CH7301
 489 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 490 #define CONFIG_VIDEO_LOGO
 491 #define CONFIG_VIDEO_BMP_LOGO
 492 #endif
 493 #endif
 494
 495 /* I2C */
 496 #define CONFIG_SYS_I2C
 497 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 498 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 499 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 500 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 501 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 502 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 503 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 504 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 505 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 506 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 507 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 508 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 509 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 510
 511 /* I2C bus multiplexer */
 512 #define I2C_MUX_PCA_ADDR                0x70
 513 #define I2C_MUX_CH_DEFAULT      0x8
 514
 515 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 516         defined(CONFIG_TARGET_T1040D4RDB)       || \
 517         defined(CONFIG_TARGET_T1042D4RDB)
 518 /* LDI/DVI Encoder for display */
 519 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 520 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 521
 522 /*
 523  * RTC configuration
 524  */
 525 #define RTC
 526 #define CONFIG_RTC_DS1337               1
 527 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 528
 529 /*DVI encoder*/
 530 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 531 #endif
 532
 533 /*
 534  * eSPI - Enhanced SPI
 535  */
 536 #define CONFIG_SPI_FLASH_BAR
 537 #define CONFIG_SF_DEFAULT_SPEED         10000000
 538 #define CONFIG_SF_DEFAULT_MODE          0
 539 #define CONFIG_ENV_SPI_BUS              0
 540 #define CONFIG_ENV_SPI_CS               0
 541 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 542 #define CONFIG_ENV_SPI_MODE             0
 543
 544 /*
 545  * General PCI
 546  * Memory space is mapped 1-1, but I/O space must start from 0.
 547  */
 548
 549 #ifdef CONFIG_PCI
 550 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 551 #ifdef CONFIG_PCIE1
 552 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 553 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 554 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 555 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 556 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 557 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 558 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 559 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 560 #endif
 561
 562 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 563 #ifdef CONFIG_PCIE2
 564 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 565 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 566 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 567 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 568 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 569 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 570 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 571 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 572 #endif
 573
 574 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 575 #ifdef CONFIG_PCIE3
 576 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 577 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 578 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 579 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 580 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 581 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 582 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 583 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 584 #endif
 585
 586 /* controller 4, Base address 203000 */
 587 #ifdef CONFIG_PCIE4
 588 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 589 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 590 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 591 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 592 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 593 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 594 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 595 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 596 #endif
 597
 598 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 599 #endif  /* CONFIG_PCI */
 600
 601 /* SATA */
 602 #define CONFIG_FSL_SATA_V2
 603 #ifdef CONFIG_FSL_SATA_V2
 604 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 605 #define CONFIG_SATA1
 606 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 607 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 608
 609 #define CONFIG_LBA48
 610 #endif
 611
 612 /*
 613 * USB
 614 */
 615 #define CONFIG_HAS_FSL_DR_USB
 616
 617 #ifdef CONFIG_HAS_FSL_DR_USB
 618 #ifdef CONFIG_USB_EHCI_HCD
 619 #define CONFIG_USB_EHCI_FSL
 620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 621 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 622 #endif
 623 #endif
 624
 625 #ifdef CONFIG_MMC
 626 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 627 #endif
 628
 629 /* Qman/Bman */
 630 #ifndef CONFIG_NOBQFMAN
 631 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 632 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 633 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 634 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 635 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 636 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 637 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 638 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 639 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 640                                         CONFIG_SYS_BMAN_CENA_SIZE)
 641 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 642 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 643 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 644 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 645 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 646 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 647 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 648 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 649 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 650 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 651 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 652                                         CONFIG_SYS_QMAN_CENA_SIZE)
 653 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 654 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 655
 656 #define CONFIG_SYS_DPAA_FMAN
 657 #define CONFIG_SYS_DPAA_PME
 658
 659 #define CONFIG_QE
 660 #define CONFIG_U_QE
 661
 662 /* Default address of microcode for the Linux Fman driver */
 663 #if defined(CONFIG_SPIFLASH)
 664 /*
 665  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 666  * env, so we got 0x110000.
 667  */
 668 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 669 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 670 #elif defined(CONFIG_SDCARD)
 671 /*
 672  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 673  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 674  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 675  */
 676 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 677 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 678 #elif defined(CONFIG_NAND)
 679 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 680 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 681 #else
 682 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 683 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 684 #endif
 685
 686 #if defined(CONFIG_SPIFLASH)
 687 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 688 #elif defined(CONFIG_SDCARD)
 689 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 690 #elif defined(CONFIG_NAND)
 691 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 692 #else
 693 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 694 #endif
 695
 696 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 697 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 698 #endif /* CONFIG_NOBQFMAN */
 699
 700 #ifdef CONFIG_SYS_DPAA_FMAN
 701 #define CONFIG_FMAN_ENET
 702 #define CONFIG_PHY_VITESSE
 703 #define CONFIG_PHY_REALTEK
 704 #endif
 705
 706 #ifdef CONFIG_FMAN_ENET
 707 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 708 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 709 #elif defined(CONFIG_TARGET_T1040D4RDB)
 710 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 711 #elif defined(CONFIG_TARGET_T1042D4RDB)
 712 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 713 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 714 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 715 #endif
 716
 717 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 718 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 719 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 720 #else
 721 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 722 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 723 #endif
 724
 725 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 726 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 727 #define CONFIG_VSC9953
 728 #ifdef CONFIG_TARGET_T1040RDB
 729 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 730 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 731 #else
 732 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 733 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 734 #endif
 735 #endif
 736
 737 #define CONFIG_MII              /* MII PHY management */
 738 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 739 #endif
 740
 741 /*
 742  * Environment
 743  */
 744 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 745 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 746
 747 /*
 748  * Miscellaneous configurable options
 749  */
 750 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 751
 752 /*
 753  * For booting Linux, the board info and command line data
 754  * have to be in the first 64 MB of memory, since this is
 755  * the maximum mapped by the Linux kernel during initialization.
 756  */
 757 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 758 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 759
 760 #ifdef CONFIG_CMD_KGDB
 761 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 762 #endif
 763
 764 /*
 765  * Dynamic MTD Partition support with mtdparts
 766  */
 767 #ifdef CONFIG_MTD_NOR_FLASH
 768 #define CONFIG_FLASH_CFI_MTD
 769 #endif
 770
 771 /*
 772  * Environment Configuration
 773  */
 774 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 775 #define CONFIG_BOOTFILE         "uImage"
 776 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 777
 778 /* default location for tftp and bootm */
 779 #define CONFIG_LOADADDR         1000000
 780
 781 #define __USB_PHY_TYPE  utmi
 782 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 783
 784 #ifdef CONFIG_TARGET_T1040RDB
 785 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 786 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 787 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 788 #elif defined(CONFIG_TARGET_T1042RDB)
 789 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 790 #elif defined(CONFIG_TARGET_T1040D4RDB)
 791 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 792 #elif defined(CONFIG_TARGET_T1042D4RDB)
 793 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 794 #endif
 795
 796 #ifdef CONFIG_FSL_DIU_FB
 797 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 798 #else
 799 #define DIU_ENVIRONMENT
 800 #endif
 801
 802 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 803         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 804         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 805         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 806         "netdev=eth0\0"                                         \
 807         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 808         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 809         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 810         "tftpflash=tftpboot $loadaddr $uboot && "               \
 811         "protect off $ubootaddr +$filesize && "                 \
 812         "erase $ubootaddr +$filesize && "                       \
 813         "cp.b $loadaddr $ubootaddr $filesize && "               \
 814         "protect on $ubootaddr +$filesize && "                  \
 815         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 816         "consoledev=ttyS0\0"                                    \
 817         "ramdiskaddr=2000000\0"                                 \
 818         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 819         "fdtaddr=1e00000\0"                                     \
 820         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 821         "bdev=sda3\0"
 822
 823 #define CONFIG_LINUX                       \
 824         "setenv bootargs root=/dev/ram rw "            \
 825         "console=$consoledev,$baudrate $othbootargs;"  \
 826         "setenv ramdiskaddr 0x02000000;"               \
 827         "setenv fdtaddr 0x00c00000;"                   \
 828         "setenv loadaddr 0x1000000;"                   \
 829         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 830
 831 #define CONFIG_HDBOOT                                   \
 832         "setenv bootargs root=/dev/$bdev rw "           \
 833         "console=$consoledev,$baudrate $othbootargs;"   \
 834         "tftp $loadaddr $bootfile;"                     \
 835         "tftp $fdtaddr $fdtfile;"                       \
 836         "bootm $loadaddr - $fdtaddr"
 837
 838 #define CONFIG_NFSBOOTCOMMAND                   \
 839         "setenv bootargs root=/dev/nfs rw "     \
 840         "nfsroot=$serverip:$rootpath "          \
 841         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 842         "console=$consoledev,$baudrate $othbootargs;"   \
 843         "tftp $loadaddr $bootfile;"             \
 844         "tftp $fdtaddr $fdtfile;"               \
 845         "bootm $loadaddr - $fdtaddr"
 846
 847 #define CONFIG_RAMBOOTCOMMAND                           \
 848         "setenv bootargs root=/dev/ram rw "             \
 849         "console=$consoledev,$baudrate $othbootargs;"   \
 850         "tftp $ramdiskaddr $ramdiskfile;"               \
 851         "tftp $loadaddr $bootfile;"                     \
 852         "tftp $fdtaddr $fdtfile;"                       \
 853         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 854
 855 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 856
 857 #include <asm/fsl_secure_boot.h>
 858
 859 #endif  /* __CONFIG_H */