include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define RESET_VECTOR_OFFSET             0x27FFC
  19 #define BOOT_PAGE_OFFSET                0x27000
  20
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #ifdef CONFIG_NXP_ESBC
  23 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  24 /*
  25  * HDR would be appended at end of image and copied to DDR along
  26  * with U-Boot image.
  27  */
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  29                                          CONFIG_U_BOOT_HDR_SIZE)
  30 #else
  31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  32 #endif
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  35 #endif
  36
  37 #ifdef CONFIG_SPIFLASH
  38 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  43 #endif
  44
  45 #ifdef CONFIG_SDCARD
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  47 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  48 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  49 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  50 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  51 #endif
  52
  53 #endif
  54
  55 /* High Level Configuration Options */
  56 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  65 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  66 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  67 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_SYS_CACHE_STASHING
  73 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  76 #endif
  77
  78 /*
  79  *  Config the L3 Cache as L3 SRAM
  80  */
  81 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  82 /*
  83  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  84  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  85  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  86  */
  87 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
  88 #define CONFIG_SYS_L3_SIZE              256 << 10
  89 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  90
  91 #define CONFIG_SYS_DCSRBAR              0xf0000000
  92 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  93
  94 /*
  95  * DDR Setup
  96  */
  97 #define CONFIG_VERY_BIG_RAM
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 100
 101 #define SPD_EEPROM_ADDRESS      0x51
 102
 103 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 104
 105 /*
 106  * IFC Definitions
 107  */
 108 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 109 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 110
 111 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 112 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 113                                 CSPR_PORT_SIZE_16 | \
 114                                 CSPR_MSEL_NOR | \
 115                                 CSPR_V)
 116 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 117
 118 /*
 119  * TDM Definition
 120  */
 121 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 122
 123 /* NOR Flash Timing Params */
 124 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 125 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 126                                 FTIM0_NOR_TEADC(0x5) | \
 127                                 FTIM0_NOR_TEAHC(0x5))
 128 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 129                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 130                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 131 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 132                                 FTIM2_NOR_TCH(0x4) | \
 133                                 FTIM2_NOR_TWPH(0x0E) | \
 134                                 FTIM2_NOR_TWP(0x1c))
 135 #define CONFIG_SYS_NOR_FTIM3    0x0
 136
 137 #define CONFIG_SYS_FLASH_QUIET_TEST
 138 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 139
 140 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 143
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO
 145 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 146
 147 /* CPLD on IFC */
 148 #define CPLD_LBMAP_MASK                 0x3F
 149 #define CPLD_BANK_SEL_MASK              0x07
 150 #define CPLD_BANK_OVERRIDE              0x40
 151 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 152 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 153 #define CPLD_LBMAP_RESET                0xFF
 154 #define CPLD_LBMAP_SHIFT                0x03
 155
 156 #if defined(CONFIG_TARGET_T1042RDB_PI)
 157 #define CPLD_DIU_SEL_DFP                0x80
 158 #elif defined(CONFIG_TARGET_T1042D4RDB)
 159 #define CPLD_DIU_SEL_DFP                0xc0
 160 #endif
 161
 162 #if defined(CONFIG_TARGET_T1040D4RDB)
 163 #define CPLD_INT_MASK_ALL               0xFF
 164 #define CPLD_INT_MASK_THERM             0x80
 165 #define CPLD_INT_MASK_DVI_DFP           0x40
 166 #define CPLD_INT_MASK_QSGMII1           0x20
 167 #define CPLD_INT_MASK_QSGMII2           0x10
 168 #define CPLD_INT_MASK_SGMI1             0x08
 169 #define CPLD_INT_MASK_SGMI2             0x04
 170 #define CPLD_INT_MASK_TDMR1             0x02
 171 #define CPLD_INT_MASK_TDMR2             0x01
 172 #endif
 173
 174 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 175 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 176 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 177 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 178                                 | CSPR_PORT_SIZE_8 \
 179                                 | CSPR_MSEL_GPCM \
 180                                 | CSPR_V)
 181 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 182 #define CONFIG_SYS_CSOR2        0x0
 183 /* CPLD Timing parameters for IFC CS2 */
 184 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 185                                         FTIM0_GPCM_TEADC(0x0e) | \
 186                                         FTIM0_GPCM_TEAHC(0x0e))
 187 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 188                                         FTIM1_GPCM_TRAD(0x1f))
 189 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 190                                         FTIM2_GPCM_TCH(0x8) | \
 191                                         FTIM2_GPCM_TWP(0x1f))
 192 #define CONFIG_SYS_CS2_FTIM3            0x0
 193
 194 /* NAND Flash on IFC */
 195 #define CONFIG_SYS_NAND_BASE            0xff800000
 196 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 197
 198 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 199 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 200                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 201                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 202                                 | CSPR_V)
 203 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 204
 205 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 206                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 207                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 208                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 209                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 210                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 211                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 212
 213 /* ONFI NAND Flash mode0 Timing Params */
 214 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 215                                         FTIM0_NAND_TWP(0x18)   | \
 216                                         FTIM0_NAND_TWCHT(0x07) | \
 217                                         FTIM0_NAND_TWH(0x0a))
 218 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 219                                         FTIM1_NAND_TWBE(0x39)  | \
 220                                         FTIM1_NAND_TRR(0x0e)   | \
 221                                         FTIM1_NAND_TRP(0x18))
 222 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 223                                         FTIM2_NAND_TREH(0x0a) | \
 224                                         FTIM2_NAND_TWHRE(0x1e))
 225 #define CONFIG_SYS_NAND_FTIM3           0x0
 226
 227 #define CONFIG_SYS_NAND_DDR_LAW         11
 228 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 230
 231 #if defined(CONFIG_MTD_RAW_NAND)
 232 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 233 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 234 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 235 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 236 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 237 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 238 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 239 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 240 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 241 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 242 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 243 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 244 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 245 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 246 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 247 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 248 #else
 249 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 250 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 251 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 258 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 259 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 260 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 261 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 262 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 263 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 264 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 265 #endif
 266
 267 #if defined(CONFIG_RAMBOOT_PBL)
 268 #define CONFIG_SYS_RAMBOOT
 269 #endif
 270
 271 #define CONFIG_HWCONFIG
 272
 273 /* define to use L1 as initial stack */
 274 #define CONFIG_L1_INIT_RAM
 275 #define CONFIG_SYS_INIT_RAM_LOCK
 276 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 279 /* The assembler doesn't like typecast */
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 281         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 282           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 283 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 284
 285 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 286
 287 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 288
 289 /* Serial Port - controlled on board with jumper J8
 290  * open - index 2
 291  * shorted - index 1
 292  */
 293 #define CONFIG_SYS_NS16550_SERIAL
 294 #define CONFIG_SYS_NS16550_REG_SIZE     1
 295 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 296
 297 #define CONFIG_SYS_BAUDRATE_TABLE       \
 298         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 299
 300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 302 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 303 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 304
 305 /* I2C bus multiplexer */
 306 #define I2C_MUX_PCA_ADDR                0x70
 307 #define I2C_MUX_CH_DEFAULT      0x8
 308
 309 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 310         defined(CONFIG_TARGET_T1040D4RDB)       || \
 311         defined(CONFIG_TARGET_T1042D4RDB)
 312 /* LDI/DVI Encoder for display */
 313 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 314 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 315 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 316
 317 /*
 318  * RTC configuration
 319  */
 320 #define RTC
 321 #define CONFIG_RTC_DS1337               1
 322 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 323
 324 /*DVI encoder*/
 325 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 326 #endif
 327
 328 /*
 329  * eSPI - Enhanced SPI
 330  */
 331
 332 /*
 333  * General PCI
 334  * Memory space is mapped 1-1, but I/O space must start from 0.
 335  */
 336
 337 #ifdef CONFIG_PCI
 338 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 339 #ifdef CONFIG_PCIE1
 340 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 341 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 342 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 343 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 344 #endif
 345
 346 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 347 #ifdef CONFIG_PCIE2
 348 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 349 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 350 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 351 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 352 #endif
 353
 354 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 355 #ifdef CONFIG_PCIE3
 356 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 357 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 358 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 359 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 360 #endif
 361
 362 /* controller 4, Base address 203000 */
 363 #ifdef CONFIG_PCIE4
 364 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 365 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 366 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 367 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 368 #endif
 369
 370 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 371 #endif  /* CONFIG_PCI */
 372
 373 /*
 374 * USB
 375 */
 376
 377 #ifdef CONFIG_MMC
 378 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 379 #endif
 380
 381 /* Qman/Bman */
 382 #ifndef CONFIG_NOBQFMAN
 383 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 384 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 385 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 386 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 387 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 388 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 389 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 390 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 391 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 392                                         CONFIG_SYS_BMAN_CENA_SIZE)
 393 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 394 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 395 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 396 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 397 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 398 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 399 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 400 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 401 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 402 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 403 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 404                                         CONFIG_SYS_QMAN_CENA_SIZE)
 405 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 406 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 407
 408 #define CONFIG_SYS_DPAA_FMAN
 409 #define CONFIG_SYS_DPAA_PME
 410
 411 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 412 #endif /* CONFIG_NOBQFMAN */
 413
 414 #ifdef CONFIG_FMAN_ENET
 415 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 416 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 417 #elif defined(CONFIG_TARGET_T1040D4RDB)
 418 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 419 #elif defined(CONFIG_TARGET_T1042D4RDB)
 420 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 421 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 422 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 423 #endif
 424
 425 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 426 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 427 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 428 #else
 429 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 430 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 431 #endif
 432
 433 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 434 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 435 #define CONFIG_VSC9953
 436 #ifdef CONFIG_TARGET_T1040RDB
 437 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 438 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 439 #else
 440 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 441 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 442 #endif
 443 #endif
 444 #endif
 445
 446 /*
 447  * Environment
 448  */
 449 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 450 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 451
 452 /*
 453  * Miscellaneous configurable options
 454  */
 455
 456 /*
 457  * For booting Linux, the board info and command line data
 458  * have to be in the first 64 MB of memory, since this is
 459  * the maximum mapped by the Linux kernel during initialization.
 460  */
 461 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 462 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 463
 464 /*
 465  * Dynamic MTD Partition support with mtdparts
 466  */
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 472 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 473
 474 #define __USB_PHY_TYPE  utmi
 475 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 476
 477 #ifdef CONFIG_TARGET_T1040RDB
 478 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 479 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 480 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 481 #elif defined(CONFIG_TARGET_T1042RDB)
 482 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 483 #elif defined(CONFIG_TARGET_T1040D4RDB)
 484 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 485 #elif defined(CONFIG_TARGET_T1042D4RDB)
 486 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 487 #endif
 488
 489 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 490         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 491         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 492         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 493         "netdev=eth0\0"                                         \
 494         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 495         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 496         "tftpflash=tftpboot $loadaddr $uboot && "               \
 497         "protect off $ubootaddr +$filesize && "                 \
 498         "erase $ubootaddr +$filesize && "                       \
 499         "cp.b $loadaddr $ubootaddr $filesize && "               \
 500         "protect on $ubootaddr +$filesize && "                  \
 501         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 502         "consoledev=ttyS0\0"                                    \
 503         "ramdiskaddr=2000000\0"                                 \
 504         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 505         "fdtaddr=1e00000\0"                                     \
 506         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 507         "bdev=sda3\0"
 508
 509 #include <asm/fsl_secure_boot.h>
 510
 511 #endif  /* __CONFIG_H */