1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define RESET_VECTOR_OFFSET 0x27FFC
19 #define BOOT_PAGE_OFFSET 0x27000
21 #ifdef CONFIG_MTD_RAW_NAND
22 #ifdef CONFIG_NXP_ESBC
23 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
25 * HDR would be appended at end of image and copied to DDR along
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
29 CONFIG_U_BOOT_HDR_SIZE)
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
33 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
34 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
37 #ifdef CONFIG_SPIFLASH
38 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
46 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
47 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
49 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
50 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
55 /* High Level Configuration Options */
57 #ifndef CONFIG_RESET_VECTOR_ADDRESS
58 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
61 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 * These can be toggled for performance analysis, otherwise use default.
66 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
68 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
72 * Config the L3 Cache as L3 SRAM
74 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
76 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
77 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
78 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
80 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
81 #define CONFIG_SYS_L3_SIZE 256 << 10
82 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
90 #define CONFIG_VERY_BIG_RAM
91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
94 #define SPD_EEPROM_ADDRESS 0x51
96 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
101 #define CONFIG_SYS_FLASH_BASE 0xe8000000
102 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
104 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
105 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
106 CSPR_PORT_SIZE_16 | \
109 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
114 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
116 /* NOR Flash Timing Params */
117 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
118 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
119 FTIM0_NOR_TEADC(0x5) | \
120 FTIM0_NOR_TEAHC(0x5))
121 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
122 FTIM1_NOR_TRAD_NOR(0x1A) |\
123 FTIM1_NOR_TSEQRAD_NOR(0x13))
124 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
125 FTIM2_NOR_TCH(0x4) | \
126 FTIM2_NOR_TWPH(0x0E) | \
128 #define CONFIG_SYS_NOR_FTIM3 0x0
130 #define CONFIG_SYS_FLASH_QUIET_TEST
131 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
133 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
135 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
138 #define CPLD_LBMAP_MASK 0x3F
139 #define CPLD_BANK_SEL_MASK 0x07
140 #define CPLD_BANK_OVERRIDE 0x40
141 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
142 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
143 #define CPLD_LBMAP_RESET 0xFF
144 #define CPLD_LBMAP_SHIFT 0x03
146 #if defined(CONFIG_TARGET_T1042RDB_PI)
147 #define CPLD_DIU_SEL_DFP 0x80
148 #elif defined(CONFIG_TARGET_T1042D4RDB)
149 #define CPLD_DIU_SEL_DFP 0xc0
152 #if defined(CONFIG_TARGET_T1040D4RDB)
153 #define CPLD_INT_MASK_ALL 0xFF
154 #define CPLD_INT_MASK_THERM 0x80
155 #define CPLD_INT_MASK_DVI_DFP 0x40
156 #define CPLD_INT_MASK_QSGMII1 0x20
157 #define CPLD_INT_MASK_QSGMII2 0x10
158 #define CPLD_INT_MASK_SGMI1 0x08
159 #define CPLD_INT_MASK_SGMI2 0x04
160 #define CPLD_INT_MASK_TDMR1 0x02
161 #define CPLD_INT_MASK_TDMR2 0x01
164 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
165 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
166 #define CONFIG_SYS_CSPR2_EXT (0xf)
167 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
171 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
172 #define CONFIG_SYS_CSOR2 0x0
173 /* CPLD Timing parameters for IFC CS2 */
174 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
175 FTIM0_GPCM_TEADC(0x0e) | \
176 FTIM0_GPCM_TEAHC(0x0e))
177 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
178 FTIM1_GPCM_TRAD(0x1f))
179 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
180 FTIM2_GPCM_TCH(0x8) | \
181 FTIM2_GPCM_TWP(0x1f))
182 #define CONFIG_SYS_CS2_FTIM3 0x0
184 /* NAND Flash on IFC */
185 #define CONFIG_SYS_NAND_BASE 0xff800000
186 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
188 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
189 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
191 | CSPR_MSEL_NAND /* MSEL = NAND */ \
193 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
195 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
196 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
197 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
198 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
199 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
200 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
201 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
203 /* ONFI NAND Flash mode0 Timing Params */
204 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
205 FTIM0_NAND_TWP(0x18) | \
206 FTIM0_NAND_TWCHT(0x07) | \
207 FTIM0_NAND_TWH(0x0a))
208 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
209 FTIM1_NAND_TWBE(0x39) | \
210 FTIM1_NAND_TRR(0x0e) | \
211 FTIM1_NAND_TRP(0x18))
212 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
213 FTIM2_NAND_TREH(0x0a) | \
214 FTIM2_NAND_TWHRE(0x1e))
215 #define CONFIG_SYS_NAND_FTIM3 0x0
217 #define CONFIG_SYS_NAND_DDR_LAW 11
218 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
219 #define CONFIG_SYS_MAX_NAND_DEVICE 1
221 #if defined(CONFIG_MTD_RAW_NAND)
222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
230 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
231 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
232 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
239 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
240 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
249 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
250 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
251 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
252 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
253 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
254 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
257 #define CONFIG_HWCONFIG
259 /* define to use L1 as initial stack */
260 #define CONFIG_L1_INIT_RAM
261 #define CONFIG_SYS_INIT_RAM_LOCK
262 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
265 /* The assembler doesn't like typecast */
266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
267 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
268 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
269 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
271 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
273 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
275 /* Serial Port - controlled on board with jumper J8
279 #define CONFIG_SYS_NS16550_SERIAL
280 #define CONFIG_SYS_NS16550_REG_SIZE 1
281 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
283 #define CONFIG_SYS_BAUDRATE_TABLE \
284 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
286 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
287 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
288 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
289 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
291 /* I2C bus multiplexer */
292 #define I2C_MUX_PCA_ADDR 0x70
293 #define I2C_MUX_CH_DEFAULT 0x8
295 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
296 defined(CONFIG_TARGET_T1040D4RDB) || \
297 defined(CONFIG_TARGET_T1042D4RDB)
298 /* LDI/DVI Encoder for display */
299 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
300 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
301 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
307 #define CONFIG_RTC_DS1337 1
308 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
311 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
315 * eSPI - Enhanced SPI
320 * Memory space is mapped 1-1, but I/O space must start from 0.
324 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
326 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
327 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
328 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
329 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
332 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
334 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
335 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
336 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
337 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
340 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
342 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
343 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
344 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
345 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
348 /* controller 4, Base address 203000 */
350 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
351 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
352 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
353 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
355 #endif /* CONFIG_PCI */
362 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
366 #ifndef CONFIG_NOBQFMAN
367 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
368 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
369 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
370 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
371 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
372 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
373 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
374 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
375 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
376 CONFIG_SYS_BMAN_CENA_SIZE)
377 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
378 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
379 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
380 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
381 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
382 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
383 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
384 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
385 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
386 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
387 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
388 CONFIG_SYS_QMAN_CENA_SIZE)
389 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
390 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
392 #define CONFIG_SYS_DPAA_FMAN
393 #define CONFIG_SYS_DPAA_PME
395 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
396 #endif /* CONFIG_NOBQFMAN */
398 #ifdef CONFIG_FMAN_ENET
399 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
400 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
401 #elif defined(CONFIG_TARGET_T1040D4RDB)
402 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
403 #elif defined(CONFIG_TARGET_T1042D4RDB)
404 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
405 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
406 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
409 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
410 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
411 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
413 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
414 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
417 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
418 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
419 #define CONFIG_VSC9953
420 #ifdef CONFIG_TARGET_T1040RDB
421 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
422 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
424 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
425 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
433 #define CONFIG_LOADS_ECHO /* echo on for serial download */
434 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
437 * Miscellaneous configurable options
441 * For booting Linux, the board info and command line data
442 * have to be in the first 64 MB of memory, since this is
443 * the maximum mapped by the Linux kernel during initialization.
445 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
448 * Dynamic MTD Partition support with mtdparts
452 * Environment Configuration
454 #define CONFIG_ROOTPATH "/opt/nfsroot"
455 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
457 #define __USB_PHY_TYPE utmi
458 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
460 #ifdef CONFIG_TARGET_T1040RDB
461 #define FDTFILE "t1040rdb/t1040rdb.dtb"
462 #elif defined(CONFIG_TARGET_T1042RDB_PI)
463 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
464 #elif defined(CONFIG_TARGET_T1042RDB)
465 #define FDTFILE "t1042rdb/t1042rdb.dtb"
466 #elif defined(CONFIG_TARGET_T1040D4RDB)
467 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
468 #elif defined(CONFIG_TARGET_T1042D4RDB)
469 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
472 #define CONFIG_EXTRA_ENV_SETTINGS \
473 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
474 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
475 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
477 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
478 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
479 "tftpflash=tftpboot $loadaddr $uboot && " \
480 "protect off $ubootaddr +$filesize && " \
481 "erase $ubootaddr +$filesize && " \
482 "cp.b $loadaddr $ubootaddr $filesize && " \
483 "protect on $ubootaddr +$filesize && " \
484 "cmp.b $loadaddr $ubootaddr $filesize\0" \
485 "consoledev=ttyS0\0" \
486 "ramdiskaddr=2000000\0" \
487 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
488 "fdtaddr=1e00000\0" \
489 "fdtfile=" __stringify(FDTFILE) "\0" \
492 #include <asm/fsl_secure_boot.h>
494 #endif /* __CONFIG_H */