include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define RESET_VECTOR_OFFSET             0x27FFC
  19 #define BOOT_PAGE_OFFSET                0x27000
  20
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #ifdef CONFIG_NXP_ESBC
  23 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  24 /*
  25  * HDR would be appended at end of image and copied to DDR along
  26  * with U-Boot image.
  27  */
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  29                                          CONFIG_U_BOOT_HDR_SIZE)
  30 #else
  31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  32 #endif
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  35 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_SPIFLASH
  41 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  46 #ifndef CONFIG_SPL_BUILD
  47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48 #endif
  49 #endif
  50
  51 #ifdef CONFIG_SDCARD
  52 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  53 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  54 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  55 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  56 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  57 #ifndef CONFIG_SPL_BUILD
  58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  59 #endif
  60 #endif
  61
  62 #endif
  63
  64 /* High Level Configuration Options */
  65 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  66
  67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  68 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  69 #endif
  70
  71 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  72 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  73 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  74 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  75 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  76 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  77
  78 #if defined(CONFIG_SPIFLASH)
  79 #elif defined(CONFIG_MTD_RAW_NAND)
  80 #ifdef CONFIG_NXP_ESBC
  81 #define CONFIG_RAMBOOT_NAND
  82 #define CONFIG_BOOTSCRIPT_COPY_RAM
  83 #endif
  84 #endif
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  91 #ifdef CONFIG_DDR_ECC
  92 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  93 #endif
  94
  95 #define CONFIG_ENABLE_36BIT_PHYS
  96
  97 /*
  98  *  Config the L3 Cache as L3 SRAM
  99  */
 100 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 101 /*
 102  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 103  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 104  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 105  */
 106 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 107 #define CONFIG_SYS_L3_SIZE              256 << 10
 108 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 109
 110 #define CONFIG_SYS_DCSRBAR              0xf0000000
 111 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 112
 113 /*
 114  * DDR Setup
 115  */
 116 #define CONFIG_VERY_BIG_RAM
 117 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 118 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 119
 120 #define CONFIG_SYS_SPD_BUS_NUM  0
 121 #define SPD_EEPROM_ADDRESS      0x51
 122
 123 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 129 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 130
 131 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 132 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 133                                 CSPR_PORT_SIZE_16 | \
 134                                 CSPR_MSEL_NOR | \
 135                                 CSPR_V)
 136 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 137
 138 /*
 139  * TDM Definition
 140  */
 141 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 142
 143 /* NOR Flash Timing Params */
 144 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 145 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 146                                 FTIM0_NOR_TEADC(0x5) | \
 147                                 FTIM0_NOR_TEAHC(0x5))
 148 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 149                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 150                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 151 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 152                                 FTIM2_NOR_TCH(0x4) | \
 153                                 FTIM2_NOR_TWPH(0x0E) | \
 154                                 FTIM2_NOR_TWP(0x1c))
 155 #define CONFIG_SYS_NOR_FTIM3    0x0
 156
 157 #define CONFIG_SYS_FLASH_QUIET_TEST
 158 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 159
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 166
 167 /* CPLD on IFC */
 168 #define CPLD_LBMAP_MASK                 0x3F
 169 #define CPLD_BANK_SEL_MASK              0x07
 170 #define CPLD_BANK_OVERRIDE              0x40
 171 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 172 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 173 #define CPLD_LBMAP_RESET                0xFF
 174 #define CPLD_LBMAP_SHIFT                0x03
 175
 176 #if defined(CONFIG_TARGET_T1042RDB_PI)
 177 #define CPLD_DIU_SEL_DFP                0x80
 178 #elif defined(CONFIG_TARGET_T1042D4RDB)
 179 #define CPLD_DIU_SEL_DFP                0xc0
 180 #endif
 181
 182 #if defined(CONFIG_TARGET_T1040D4RDB)
 183 #define CPLD_INT_MASK_ALL               0xFF
 184 #define CPLD_INT_MASK_THERM             0x80
 185 #define CPLD_INT_MASK_DVI_DFP           0x40
 186 #define CPLD_INT_MASK_QSGMII1           0x20
 187 #define CPLD_INT_MASK_QSGMII2           0x10
 188 #define CPLD_INT_MASK_SGMI1             0x08
 189 #define CPLD_INT_MASK_SGMI2             0x04
 190 #define CPLD_INT_MASK_TDMR1             0x02
 191 #define CPLD_INT_MASK_TDMR2             0x01
 192 #endif
 193
 194 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 195 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 196 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 197 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 198                                 | CSPR_PORT_SIZE_8 \
 199                                 | CSPR_MSEL_GPCM \
 200                                 | CSPR_V)
 201 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 202 #define CONFIG_SYS_CSOR2        0x0
 203 /* CPLD Timing parameters for IFC CS2 */
 204 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 205                                         FTIM0_GPCM_TEADC(0x0e) | \
 206                                         FTIM0_GPCM_TEAHC(0x0e))
 207 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 208                                         FTIM1_GPCM_TRAD(0x1f))
 209 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 210                                         FTIM2_GPCM_TCH(0x8) | \
 211                                         FTIM2_GPCM_TWP(0x1f))
 212 #define CONFIG_SYS_CS2_FTIM3            0x0
 213
 214 /* NAND Flash on IFC */
 215 #define CONFIG_SYS_NAND_BASE            0xff800000
 216 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 217
 218 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 219 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 220                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 221                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 222                                 | CSPR_V)
 223 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 224
 225 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 226                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 227                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 228                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 229                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 230                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 231                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 232
 233 /* ONFI NAND Flash mode0 Timing Params */
 234 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 235                                         FTIM0_NAND_TWP(0x18)   | \
 236                                         FTIM0_NAND_TWCHT(0x07) | \
 237                                         FTIM0_NAND_TWH(0x0a))
 238 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 239                                         FTIM1_NAND_TWBE(0x39)  | \
 240                                         FTIM1_NAND_TRR(0x0e)   | \
 241                                         FTIM1_NAND_TRP(0x18))
 242 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 243                                         FTIM2_NAND_TREH(0x0a) | \
 244                                         FTIM2_NAND_TWHRE(0x1e))
 245 #define CONFIG_SYS_NAND_FTIM3           0x0
 246
 247 #define CONFIG_SYS_NAND_DDR_LAW         11
 248 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 249 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 250
 251 #if defined(CONFIG_MTD_RAW_NAND)
 252 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 253 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 254 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 255 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 256 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 257 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 258 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 259 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 260 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 261 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 262 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 263 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 264 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 265 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 266 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 267 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 268 #else
 269 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 270 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 278 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 279 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 280 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 281 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 282 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 283 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 284 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 285 #endif
 286
 287 #if defined(CONFIG_RAMBOOT_PBL)
 288 #define CONFIG_SYS_RAMBOOT
 289 #endif
 290
 291 #define CONFIG_HWCONFIG
 292
 293 /* define to use L1 as initial stack */
 294 #define CONFIG_L1_INIT_RAM
 295 #define CONFIG_SYS_INIT_RAM_LOCK
 296 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 299 /* The assembler doesn't like typecast */
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 301         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 302           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 303 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 304
 305 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 306
 307 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 308
 309 /* Serial Port - controlled on board with jumper J8
 310  * open - index 2
 311  * shorted - index 1
 312  */
 313 #define CONFIG_SYS_NS16550_SERIAL
 314 #define CONFIG_SYS_NS16550_REG_SIZE     1
 315 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 316
 317 #define CONFIG_SYS_BAUDRATE_TABLE       \
 318         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 319
 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 322 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 323 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 324
 325 /* I2C bus multiplexer */
 326 #define I2C_MUX_PCA_ADDR                0x70
 327 #define I2C_MUX_CH_DEFAULT      0x8
 328
 329 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 330         defined(CONFIG_TARGET_T1040D4RDB)       || \
 331         defined(CONFIG_TARGET_T1042D4RDB)
 332 /* LDI/DVI Encoder for display */
 333 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 334 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 335 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 336
 337 /*
 338  * RTC configuration
 339  */
 340 #define RTC
 341 #define CONFIG_RTC_DS1337               1
 342 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 343
 344 /*DVI encoder*/
 345 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 346 #endif
 347
 348 /*
 349  * eSPI - Enhanced SPI
 350  */
 351
 352 /*
 353  * General PCI
 354  * Memory space is mapped 1-1, but I/O space must start from 0.
 355  */
 356
 357 #ifdef CONFIG_PCI
 358 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 359 #ifdef CONFIG_PCIE1
 360 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 361 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 362 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 363 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 364 #endif
 365
 366 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 367 #ifdef CONFIG_PCIE2
 368 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 369 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 370 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 371 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 372 #endif
 373
 374 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 375 #ifdef CONFIG_PCIE3
 376 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 377 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 378 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 379 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 380 #endif
 381
 382 /* controller 4, Base address 203000 */
 383 #ifdef CONFIG_PCIE4
 384 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 385 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 386 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 387 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 388 #endif
 389
 390 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 391 #endif  /* CONFIG_PCI */
 392
 393 /* SATA */
 394 #define CONFIG_FSL_SATA_V2
 395 #ifdef CONFIG_FSL_SATA_V2
 396 #define CONFIG_SATA1
 397 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 398 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 399
 400 #define CONFIG_LBA48
 401 #endif
 402
 403 /*
 404 * USB
 405 */
 406 #define CONFIG_HAS_FSL_DR_USB
 407
 408 #ifdef CONFIG_HAS_FSL_DR_USB
 409 #ifdef CONFIG_USB_EHCI_HCD
 410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 411 #endif
 412 #endif
 413
 414 #ifdef CONFIG_MMC
 415 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 416 #endif
 417
 418 /* Qman/Bman */
 419 #ifndef CONFIG_NOBQFMAN
 420 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 421 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 422 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 423 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 424 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 425 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 426 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 427 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 428 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 429                                         CONFIG_SYS_BMAN_CENA_SIZE)
 430 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 431 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 432 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 433 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 434 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 435 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 436 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 437 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 438 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 439 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 440 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 441                                         CONFIG_SYS_QMAN_CENA_SIZE)
 442 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 443 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 444
 445 #define CONFIG_SYS_DPAA_FMAN
 446 #define CONFIG_SYS_DPAA_PME
 447
 448 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 449 #endif /* CONFIG_NOBQFMAN */
 450
 451 #ifdef CONFIG_FMAN_ENET
 452 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 453 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 454 #elif defined(CONFIG_TARGET_T1040D4RDB)
 455 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 456 #elif defined(CONFIG_TARGET_T1042D4RDB)
 457 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 458 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 459 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 460 #endif
 461
 462 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 463 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 464 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 465 #else
 466 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 467 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 468 #endif
 469
 470 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 471 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 472 #define CONFIG_VSC9953
 473 #ifdef CONFIG_TARGET_T1040RDB
 474 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 475 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 476 #else
 477 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 478 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 479 #endif
 480 #endif
 481 #endif
 482
 483 /*
 484  * Environment
 485  */
 486 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 487 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 488
 489 /*
 490  * Miscellaneous configurable options
 491  */
 492
 493 /*
 494  * For booting Linux, the board info and command line data
 495  * have to be in the first 64 MB of memory, since this is
 496  * the maximum mapped by the Linux kernel during initialization.
 497  */
 498 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 499 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 500
 501 /*
 502  * Dynamic MTD Partition support with mtdparts
 503  */
 504
 505 /*
 506  * Environment Configuration
 507  */
 508 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 509 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 510
 511 #define __USB_PHY_TYPE  utmi
 512 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 513
 514 #ifdef CONFIG_TARGET_T1040RDB
 515 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 516 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 517 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 518 #elif defined(CONFIG_TARGET_T1042RDB)
 519 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 520 #elif defined(CONFIG_TARGET_T1040D4RDB)
 521 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 522 #elif defined(CONFIG_TARGET_T1042D4RDB)
 523 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 524 #endif
 525
 526 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 527         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 528         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 529         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 530         "netdev=eth0\0"                                         \
 531         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 532         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 533         "tftpflash=tftpboot $loadaddr $uboot && "               \
 534         "protect off $ubootaddr +$filesize && "                 \
 535         "erase $ubootaddr +$filesize && "                       \
 536         "cp.b $loadaddr $ubootaddr $filesize && "               \
 537         "protect on $ubootaddr +$filesize && "                  \
 538         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 539         "consoledev=ttyS0\0"                                    \
 540         "ramdiskaddr=2000000\0"                                 \
 541         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 542         "fdtaddr=1e00000\0"                                     \
 543         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 544         "bdev=sda3\0"
 545
 546 #include <asm/fsl_secure_boot.h>
 547
 548 #endif  /* __CONFIG_H */