include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_PAD_TO               0x40000
  20 #define CONFIG_SPL_MAX_SIZE             0x28000
  21 #ifdef CONFIG_SPL_BUILD
  22 #define CONFIG_SPL_SKIP_RELOCATE
  23 #define CONFIG_SPL_COMMON_INIT_DDR
  24 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  25 #endif
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef CONFIG_MTD_RAW_NAND
  30 #ifdef CONFIG_NXP_ESBC
  31 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  32 /*
  33  * HDR would be appended at end of image and copied to DDR along
  34  * with U-Boot image.
  35  */
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  37                                          CONFIG_U_BOOT_HDR_SIZE)
  38 #else
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #endif
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  43 #endif
  44
  45 #ifdef CONFIG_SPIFLASH
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  47 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  52 #ifndef CONFIG_SPL_BUILD
  53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54 #endif
  55 #endif
  56
  57 #ifdef CONFIG_SDCARD
  58 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  59 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  60 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  61 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  62 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  63 #ifndef CONFIG_SPL_BUILD
  64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65 #endif
  66 #endif
  67
  68 #endif
  69
  70 /* High Level Configuration Options */
  71 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  72
  73 /* support deep sleep */
  74 #define CONFIG_DEEP_SLEEP
  75
  76 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  77 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  78 #endif
  79
  80 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  81 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  82 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  83 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  84 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  85 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  86
  87 #if defined(CONFIG_SPIFLASH)
  88 #elif defined(CONFIG_MTD_RAW_NAND)
  89 #ifdef CONFIG_NXP_ESBC
  90 #define CONFIG_RAMBOOT_NAND
  91 #define CONFIG_BOOTSCRIPT_COPY_RAM
  92 #endif
  93 #endif
  94
  95 /*
  96  * These can be toggled for performance analysis, otherwise use default.
  97  */
  98 #define CONFIG_SYS_CACHE_STASHING
  99 #define CONFIG_BACKSIDE_L2_CACHE
 100 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 101 #define CONFIG_BTB                      /* toggle branch predition */
 102 #ifdef CONFIG_DDR_ECC
 103 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 104 #endif
 105
 106 #define CONFIG_ENABLE_36BIT_PHYS
 107
 108 /*
 109  *  Config the L3 Cache as L3 SRAM
 110  */
 111 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 112 /*
 113  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 114  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 115  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 116  */
 117 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 118 #define CONFIG_SYS_L3_SIZE              256 << 10
 119 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 120 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 121 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 122 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 123 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 124
 125 #define CONFIG_SYS_DCSRBAR              0xf0000000
 126 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 127
 128 /*
 129  * DDR Setup
 130  */
 131 #define CONFIG_VERY_BIG_RAM
 132 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 133 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 134
 135 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 136 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 137
 138 #define CONFIG_SYS_SPD_BUS_NUM  0
 139 #define SPD_EEPROM_ADDRESS      0x51
 140
 141 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 142
 143 /*
 144  * IFC Definitions
 145  */
 146 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 147 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 148
 149 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 150 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 151                                 CSPR_PORT_SIZE_16 | \
 152                                 CSPR_MSEL_NOR | \
 153                                 CSPR_V)
 154 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 155
 156 /*
 157  * TDM Definition
 158  */
 159 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 160
 161 /* NOR Flash Timing Params */
 162 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 163 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 164                                 FTIM0_NOR_TEADC(0x5) | \
 165                                 FTIM0_NOR_TEAHC(0x5))
 166 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 167                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 168                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 169 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 170                                 FTIM2_NOR_TCH(0x4) | \
 171                                 FTIM2_NOR_TWPH(0x0E) | \
 172                                 FTIM2_NOR_TWP(0x1c))
 173 #define CONFIG_SYS_NOR_FTIM3    0x0
 174
 175 #define CONFIG_SYS_FLASH_QUIET_TEST
 176 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 177
 178 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 179 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 180 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 181
 182 #define CONFIG_SYS_FLASH_EMPTY_INFO
 183 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 184
 185 /* CPLD on IFC */
 186 #define CPLD_LBMAP_MASK                 0x3F
 187 #define CPLD_BANK_SEL_MASK              0x07
 188 #define CPLD_BANK_OVERRIDE              0x40
 189 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 190 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 191 #define CPLD_LBMAP_RESET                0xFF
 192 #define CPLD_LBMAP_SHIFT                0x03
 193
 194 #if defined(CONFIG_TARGET_T1042RDB_PI)
 195 #define CPLD_DIU_SEL_DFP                0x80
 196 #elif defined(CONFIG_TARGET_T1042D4RDB)
 197 #define CPLD_DIU_SEL_DFP                0xc0
 198 #endif
 199
 200 #if defined(CONFIG_TARGET_T1040D4RDB)
 201 #define CPLD_INT_MASK_ALL               0xFF
 202 #define CPLD_INT_MASK_THERM             0x80
 203 #define CPLD_INT_MASK_DVI_DFP           0x40
 204 #define CPLD_INT_MASK_QSGMII1           0x20
 205 #define CPLD_INT_MASK_QSGMII2           0x10
 206 #define CPLD_INT_MASK_SGMI1             0x08
 207 #define CPLD_INT_MASK_SGMI2             0x04
 208 #define CPLD_INT_MASK_TDMR1             0x02
 209 #define CPLD_INT_MASK_TDMR2             0x01
 210 #endif
 211
 212 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 213 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 214 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 215 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 216                                 | CSPR_PORT_SIZE_8 \
 217                                 | CSPR_MSEL_GPCM \
 218                                 | CSPR_V)
 219 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 220 #define CONFIG_SYS_CSOR2        0x0
 221 /* CPLD Timing parameters for IFC CS2 */
 222 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 223                                         FTIM0_GPCM_TEADC(0x0e) | \
 224                                         FTIM0_GPCM_TEAHC(0x0e))
 225 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 226                                         FTIM1_GPCM_TRAD(0x1f))
 227 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 228                                         FTIM2_GPCM_TCH(0x8) | \
 229                                         FTIM2_GPCM_TWP(0x1f))
 230 #define CONFIG_SYS_CS2_FTIM3            0x0
 231
 232 /* NAND Flash on IFC */
 233 #define CONFIG_SYS_NAND_BASE            0xff800000
 234 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 235
 236 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 237 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 238                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 239                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 240                                 | CSPR_V)
 241 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 242
 243 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 244                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 245                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 246                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 247                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 248                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 249                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 250
 251 /* ONFI NAND Flash mode0 Timing Params */
 252 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 253                                         FTIM0_NAND_TWP(0x18)   | \
 254                                         FTIM0_NAND_TWCHT(0x07) | \
 255                                         FTIM0_NAND_TWH(0x0a))
 256 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 257                                         FTIM1_NAND_TWBE(0x39)  | \
 258                                         FTIM1_NAND_TRR(0x0e)   | \
 259                                         FTIM1_NAND_TRP(0x18))
 260 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 261                                         FTIM2_NAND_TREH(0x0a) | \
 262                                         FTIM2_NAND_TWHRE(0x1e))
 263 #define CONFIG_SYS_NAND_FTIM3           0x0
 264
 265 #define CONFIG_SYS_NAND_DDR_LAW         11
 266 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 267 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 268
 269 #if defined(CONFIG_MTD_RAW_NAND)
 270 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 271 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 272 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 273 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 274 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 275 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 276 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 277 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 278 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 279 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 280 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 281 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 282 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 283 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 284 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 285 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 286 #else
 287 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 288 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 289 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 290 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 291 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 292 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 293 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 294 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 295 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 296 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 297 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 298 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 299 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 300 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 301 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 302 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 303 #endif
 304
 305 #ifdef CONFIG_SPL_BUILD
 306 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 307 #else
 308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 309 #endif
 310
 311 #if defined(CONFIG_RAMBOOT_PBL)
 312 #define CONFIG_SYS_RAMBOOT
 313 #endif
 314
 315 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 316 #if defined(CONFIG_MTD_RAW_NAND)
 317 #define CONFIG_A008044_WORKAROUND
 318 #endif
 319 #endif
 320
 321 #define CONFIG_HWCONFIG
 322
 323 /* define to use L1 as initial stack */
 324 #define CONFIG_L1_INIT_RAM
 325 #define CONFIG_SYS_INIT_RAM_LOCK
 326 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 328 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 329 /* The assembler doesn't like typecast */
 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 331         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 332           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 333 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 334
 335 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 336                                         GENERATED_GBL_DATA_SIZE)
 337 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 338
 339 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 340
 341 /* Serial Port - controlled on board with jumper J8
 342  * open - index 2
 343  * shorted - index 1
 344  */
 345 #define CONFIG_SYS_NS16550_SERIAL
 346 #define CONFIG_SYS_NS16550_REG_SIZE     1
 347 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 348
 349 #define CONFIG_SYS_BAUDRATE_TABLE       \
 350         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 351
 352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 354 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 355 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 356
 357 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 358 /* Video */
 359 #define CONFIG_FSL_DIU_FB
 360
 361 #ifdef CONFIG_FSL_DIU_FB
 362 #define CONFIG_FSL_DIU_CH7301
 363 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 364 #define CONFIG_VIDEO_BMP_LOGO
 365 #endif
 366 #endif
 367
 368 /* I2C */
 369
 370 /* I2C bus multiplexer */
 371 #define I2C_MUX_PCA_ADDR                0x70
 372 #define I2C_MUX_CH_DEFAULT      0x8
 373
 374 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 375         defined(CONFIG_TARGET_T1040D4RDB)       || \
 376         defined(CONFIG_TARGET_T1042D4RDB)
 377 /* LDI/DVI Encoder for display */
 378 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 379 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 380 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 381
 382 /*
 383  * RTC configuration
 384  */
 385 #define RTC
 386 #define CONFIG_RTC_DS1337               1
 387 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 388
 389 /*DVI encoder*/
 390 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 391 #endif
 392
 393 /*
 394  * eSPI - Enhanced SPI
 395  */
 396
 397 /*
 398  * General PCI
 399  * Memory space is mapped 1-1, but I/O space must start from 0.
 400  */
 401
 402 #ifdef CONFIG_PCI
 403 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 404 #ifdef CONFIG_PCIE1
 405 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 406 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 407 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 408 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 409 #endif
 410
 411 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 412 #ifdef CONFIG_PCIE2
 413 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 414 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 415 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 416 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 417 #endif
 418
 419 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 420 #ifdef CONFIG_PCIE3
 421 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 422 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 423 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 424 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 425 #endif
 426
 427 /* controller 4, Base address 203000 */
 428 #ifdef CONFIG_PCIE4
 429 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 430 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 431 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 432 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 433 #endif
 434
 435 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 436 #endif  /* CONFIG_PCI */
 437
 438 /* SATA */
 439 #define CONFIG_FSL_SATA_V2
 440 #ifdef CONFIG_FSL_SATA_V2
 441 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 442 #define CONFIG_SATA1
 443 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 444 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 445
 446 #define CONFIG_LBA48
 447 #endif
 448
 449 /*
 450 * USB
 451 */
 452 #define CONFIG_HAS_FSL_DR_USB
 453
 454 #ifdef CONFIG_HAS_FSL_DR_USB
 455 #ifdef CONFIG_USB_EHCI_HCD
 456 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 457 #endif
 458 #endif
 459
 460 #ifdef CONFIG_MMC
 461 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 462 #endif
 463
 464 /* Qman/Bman */
 465 #ifndef CONFIG_NOBQFMAN
 466 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 467 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 468 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 469 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 470 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 471 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 472 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 473 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 474 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 475                                         CONFIG_SYS_BMAN_CENA_SIZE)
 476 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 477 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 478 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 479 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 480 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 481 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 482 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 483 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 484 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 485 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 486 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 487                                         CONFIG_SYS_QMAN_CENA_SIZE)
 488 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 489 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 490
 491 #define CONFIG_SYS_DPAA_FMAN
 492 #define CONFIG_SYS_DPAA_PME
 493
 494 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 495 #endif /* CONFIG_NOBQFMAN */
 496
 497 #ifdef CONFIG_FMAN_ENET
 498 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 499 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 500 #elif defined(CONFIG_TARGET_T1040D4RDB)
 501 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 502 #elif defined(CONFIG_TARGET_T1042D4RDB)
 503 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 504 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 505 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 506 #endif
 507
 508 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 509 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 510 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 511 #else
 512 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 513 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 514 #endif
 515
 516 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 517 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 518 #define CONFIG_VSC9953
 519 #ifdef CONFIG_TARGET_T1040RDB
 520 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 521 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 522 #else
 523 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 524 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 525 #endif
 526 #endif
 527
 528 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 529 #endif
 530
 531 /*
 532  * Environment
 533  */
 534 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 535 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 536
 537 /*
 538  * Miscellaneous configurable options
 539  */
 540
 541 /*
 542  * For booting Linux, the board info and command line data
 543  * have to be in the first 64 MB of memory, since this is
 544  * the maximum mapped by the Linux kernel during initialization.
 545  */
 546 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 547 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 548
 549 /*
 550  * Dynamic MTD Partition support with mtdparts
 551  */
 552
 553 /*
 554  * Environment Configuration
 555  */
 556 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 557 #define CONFIG_BOOTFILE         "uImage"
 558 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 559
 560 #define __USB_PHY_TYPE  utmi
 561 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 562
 563 #ifdef CONFIG_TARGET_T1040RDB
 564 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 565 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 566 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 567 #elif defined(CONFIG_TARGET_T1042RDB)
 568 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 569 #elif defined(CONFIG_TARGET_T1040D4RDB)
 570 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 571 #elif defined(CONFIG_TARGET_T1042D4RDB)
 572 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 573 #endif
 574
 575 #ifdef CONFIG_FSL_DIU_FB
 576 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 577 #else
 578 #define DIU_ENVIRONMENT
 579 #endif
 580
 581 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 582         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 583         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 584         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 585         "netdev=eth0\0"                                         \
 586         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 587         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 588         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 589         "tftpflash=tftpboot $loadaddr $uboot && "               \
 590         "protect off $ubootaddr +$filesize && "                 \
 591         "erase $ubootaddr +$filesize && "                       \
 592         "cp.b $loadaddr $ubootaddr $filesize && "               \
 593         "protect on $ubootaddr +$filesize && "                  \
 594         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 595         "consoledev=ttyS0\0"                                    \
 596         "ramdiskaddr=2000000\0"                                 \
 597         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 598         "fdtaddr=1e00000\0"                                     \
 599         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 600         "bdev=sda3\0"
 601
 602 #include <asm/fsl_secure_boot.h>
 603
 604 #endif  /* __CONFIG_H */