include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define RESET_VECTOR_OFFSET             0x27FFC
  19 #define BOOT_PAGE_OFFSET                0x27000
  20
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #ifdef CONFIG_NXP_ESBC
  23 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  24 /*
  25  * HDR would be appended at end of image and copied to DDR along
  26  * with U-Boot image.
  27  */
  28 #define CFG_SYS_NAND_U_BOOT_SIZE        ((768 << 10) + \
  29                                          CONFIG_U_BOOT_HDR_SIZE)
  30 #else
  31 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  32 #endif
  33 #define CFG_SYS_NAND_U_BOOT_DST 0x30000000
  34 #define CFG_SYS_NAND_U_BOOT_START       0x30000000
  35 #endif
  36
  37 #ifdef CONFIG_SPIFLASH
  38 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  39 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (768 << 10)
  40 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x30000000)
  41 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x30000000)
  42 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (256 << 10)
  43 #endif
  44
  45 #ifdef CONFIG_SDCARD
  46 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  47 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  48 #define CFG_SYS_MMC_U_BOOT_DST  (0x30000000)
  49 #define CFG_SYS_MMC_U_BOOT_START        (0x30000000)
  50 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  51 #endif
  52
  53 #endif
  54
  55 /* High Level Configuration Options */
  56
  57 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  58 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  59 #endif
  60
  61 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #define CFG_SYS_INIT_L2CSR0             L2CSR0_L2E
  67 #ifdef CONFIG_DDR_ECC
  68 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  69 #endif
  70
  71 /*
  72  *  Config the L3 Cache as L3 SRAM
  73  */
  74 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  75 /*
  76  * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
  77  * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
  78  * (CFG_SYS_INIT_L3_VADDR) will be different.
  79  */
  80 #define CFG_SYS_INIT_L3_VADDR   0xFFFC0000
  81 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  82
  83 #define CFG_SYS_DCSRBAR         0xf0000000
  84 #define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
  85
  86 /*
  87  * DDR Setup
  88  */
  89 #define CONFIG_VERY_BIG_RAM
  90 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  91 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  92
  93 #define SPD_EEPROM_ADDRESS      0x51
  94
  95 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
  96
  97 /*
  98  * IFC Definitions
  99  */
 100 #define CFG_SYS_FLASH_BASE      0xe8000000
 101 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
 102
 103 #define CFG_SYS_NOR_CSPR_EXT    (0xf)
 104 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 105                                 CSPR_PORT_SIZE_16 | \
 106                                 CSPR_MSEL_NOR | \
 107                                 CSPR_V)
 108 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 109
 110 /*
 111  * TDM Definition
 112  */
 113 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 114
 115 /* NOR Flash Timing Params */
 116 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 117 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 118                                 FTIM0_NOR_TEADC(0x5) | \
 119                                 FTIM0_NOR_TEAHC(0x5))
 120 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 121                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 122                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 123 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 124                                 FTIM2_NOR_TCH(0x4) | \
 125                                 FTIM2_NOR_TWPH(0x0E) | \
 126                                 FTIM2_NOR_TWP(0x1c))
 127 #define CFG_SYS_NOR_FTIM3       0x0
 128
 129 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 130
 131 /* CPLD on IFC */
 132 #define CPLD_LBMAP_MASK                 0x3F
 133 #define CPLD_BANK_SEL_MASK              0x07
 134 #define CPLD_BANK_OVERRIDE              0x40
 135 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 136 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 137 #define CPLD_LBMAP_RESET                0xFF
 138 #define CPLD_LBMAP_SHIFT                0x03
 139
 140 #if defined(CONFIG_TARGET_T1042RDB_PI)
 141 #define CPLD_DIU_SEL_DFP                0x80
 142 #elif defined(CONFIG_TARGET_T1042D4RDB)
 143 #define CPLD_DIU_SEL_DFP                0xc0
 144 #endif
 145
 146 #if defined(CONFIG_TARGET_T1040D4RDB)
 147 #define CPLD_INT_MASK_ALL               0xFF
 148 #define CPLD_INT_MASK_THERM             0x80
 149 #define CPLD_INT_MASK_DVI_DFP           0x40
 150 #define CPLD_INT_MASK_QSGMII1           0x20
 151 #define CPLD_INT_MASK_QSGMII2           0x10
 152 #define CPLD_INT_MASK_SGMI1             0x08
 153 #define CPLD_INT_MASK_SGMI2             0x04
 154 #define CPLD_INT_MASK_TDMR1             0x02
 155 #define CPLD_INT_MASK_TDMR2             0x01
 156 #endif
 157
 158 #define CFG_SYS_CPLD_BASE       0xffdf0000
 159 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 160 #define CFG_SYS_CSPR2_EXT       (0xf)
 161 #define CFG_SYS_CSPR2   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8 \
 163                                 | CSPR_MSEL_GPCM \
 164                                 | CSPR_V)
 165 #define CFG_SYS_AMASK2  IFC_AMASK(64*1024)
 166 #define CFG_SYS_CSOR2   0x0
 167 /* CPLD Timing parameters for IFC CS2 */
 168 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 169                                         FTIM0_GPCM_TEADC(0x0e) | \
 170                                         FTIM0_GPCM_TEAHC(0x0e))
 171 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 172                                         FTIM1_GPCM_TRAD(0x1f))
 173 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 174                                         FTIM2_GPCM_TCH(0x8) | \
 175                                         FTIM2_GPCM_TWP(0x1f))
 176 #define CFG_SYS_CS2_FTIM3               0x0
 177
 178 /* NAND Flash on IFC */
 179 #define CFG_SYS_NAND_BASE               0xff800000
 180 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 181
 182 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 183 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 184                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 185                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 186                                 | CSPR_V)
 187 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 188
 189 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 190                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 191                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 192                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 193                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 194                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 195                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 196
 197 /* ONFI NAND Flash mode0 Timing Params */
 198 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 199                                         FTIM0_NAND_TWP(0x18)   | \
 200                                         FTIM0_NAND_TWCHT(0x07) | \
 201                                         FTIM0_NAND_TWH(0x0a))
 202 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 203                                         FTIM1_NAND_TWBE(0x39)  | \
 204                                         FTIM1_NAND_TRR(0x0e)   | \
 205                                         FTIM1_NAND_TRP(0x18))
 206 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
 207                                         FTIM2_NAND_TREH(0x0a) | \
 208                                         FTIM2_NAND_TWHRE(0x1e))
 209 #define CFG_SYS_NAND_FTIM3              0x0
 210
 211 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 212
 213 #if defined(CONFIG_MTD_RAW_NAND)
 214 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 215 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 216 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 217 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 218 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 219 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 220 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 221 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 222 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR_CSPR_EXT
 223 #define CFG_SYS_CSPR1           CFG_SYS_NOR_CSPR
 224 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 225 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 226 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 227 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 228 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 229 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 230 #else
 231 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR_CSPR_EXT
 232 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 233 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 234 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 235 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 236 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 237 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 238 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 239 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 240 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 241 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 242 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 243 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 244 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 245 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 246 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 247 #endif
 248
 249 /* define to use L1 as initial stack */
 250 #define CONFIG_L1_INIT_RAM
 251 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
 252 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 253 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 254 /* The assembler doesn't like typecast */
 255 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 256         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 257           CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 258 #define CFG_SYS_INIT_RAM_SIZE           0x00004000
 259
 260 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 261
 262 /* Serial Port - controlled on board with jumper J8
 263  * open - index 2
 264  * shorted - index 1
 265  */
 266 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 267
 268 #define CFG_SYS_BAUDRATE_TABLE  \
 269         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 270
 271 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x11C500)
 272 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x11C600)
 273 #define CFG_SYS_NS16550_COM3    (CFG_SYS_CCSRBAR+0x11D500)
 274 #define CFG_SYS_NS16550_COM4    (CFG_SYS_CCSRBAR+0x11D600)
 275
 276 /* I2C bus multiplexer */
 277 #define I2C_MUX_PCA_ADDR                0x70
 278 #define I2C_MUX_CH_DEFAULT      0x8
 279
 280 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 281         defined(CONFIG_TARGET_T1040D4RDB)       || \
 282         defined(CONFIG_TARGET_T1042D4RDB)
 283 /*
 284  * RTC configuration
 285  */
 286 #define CFG_SYS_I2C_RTC_ADDR         0x68
 287
 288 /*DVI encoder*/
 289 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 290 #endif
 291
 292 /*
 293  * eSPI - Enhanced SPI
 294  */
 295
 296 /*
 297  * General PCI
 298  * Memory space is mapped 1-1, but I/O space must start from 0.
 299  */
 300
 301 #ifdef CONFIG_PCI
 302 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 303 #ifdef CONFIG_PCIE1
 304 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 305 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 306 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 307 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 308 #endif
 309
 310 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 311 #ifdef CONFIG_PCIE2
 312 #define CFG_SYS_PCIE2_MEM_VIRT  0x90000000
 313 #define CFG_SYS_PCIE2_MEM_PHYS  0xc10000000ull
 314 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 315 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 316 #endif
 317
 318 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 319 #ifdef CONFIG_PCIE3
 320 #define CFG_SYS_PCIE3_MEM_VIRT  0xa0000000
 321 #define CFG_SYS_PCIE3_MEM_PHYS  0xc20000000ull
 322 #endif
 323
 324 /* controller 4, Base address 203000 */
 325 #ifdef CONFIG_PCIE4
 326 #define CFG_SYS_PCIE4_MEM_VIRT  0xb0000000
 327 #define CFG_SYS_PCIE4_MEM_PHYS  0xc30000000ull
 328 #endif
 329 #endif  /* CONFIG_PCI */
 330
 331 /*
 332 * USB
 333 */
 334
 335 #ifdef CONFIG_MMC
 336 #define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 337 #endif
 338
 339 /* Qman/Bman */
 340 #ifndef CONFIG_NOBQFMAN
 341 #define CFG_SYS_BMAN_NUM_PORTALS        10
 342 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 343 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 344 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 345 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 346 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 347 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 348 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 349 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 350                                         CFG_SYS_BMAN_CENA_SIZE)
 351 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 352 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 353 #define CFG_SYS_QMAN_NUM_PORTALS        10
 354 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 355 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 356 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 357 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 358 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 359 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 360                                         CFG_SYS_QMAN_CENA_SIZE)
 361 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 362 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 363 #endif /* CONFIG_NOBQFMAN */
 364
 365 #ifdef CONFIG_FMAN_ENET
 366 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 367 #define CFG_SYS_SGMII1_PHY_ADDR             0x03
 368 #elif defined(CONFIG_TARGET_T1040D4RDB)
 369 #define CFG_SYS_SGMII1_PHY_ADDR             0x01
 370 #elif defined(CONFIG_TARGET_T1042D4RDB)
 371 #define CFG_SYS_SGMII1_PHY_ADDR             0x02
 372 #define CFG_SYS_SGMII2_PHY_ADDR             0x03
 373 #define CFG_SYS_SGMII3_PHY_ADDR             0x01
 374 #endif
 375
 376 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 377 #define CFG_SYS_RGMII1_PHY_ADDR             0x04
 378 #define CFG_SYS_RGMII2_PHY_ADDR             0x05
 379 #else
 380 #define CFG_SYS_RGMII1_PHY_ADDR             0x01
 381 #define CFG_SYS_RGMII2_PHY_ADDR             0x02
 382 #endif
 383
 384 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 385 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 386 #ifdef CONFIG_TARGET_T1040RDB
 387 #define CFG_SYS_FM1_QSGMII11_PHY_ADDR   0x04
 388 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR   0x08
 389 #else
 390 #define CFG_SYS_FM1_QSGMII11_PHY_ADDR   0x08
 391 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR   0x0c
 392 #endif
 393 #endif
 394 #endif
 395
 396 /*
 397  * Miscellaneous configurable options
 398  */
 399
 400 /*
 401  * For booting Linux, the board info and command line data
 402  * have to be in the first 64 MB of memory, since this is
 403  * the maximum mapped by the Linux kernel during initialization.
 404  */
 405 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 406
 407 /*
 408  * Dynamic MTD Partition support with mtdparts
 409  */
 410
 411 /*
 412  * Environment Configuration
 413  */
 414 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 415 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 416
 417 #define __USB_PHY_TYPE  utmi
 418 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 419
 420 #ifdef CONFIG_TARGET_T1040RDB
 421 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 422 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 423 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 424 #elif defined(CONFIG_TARGET_T1042RDB)
 425 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 426 #elif defined(CONFIG_TARGET_T1040D4RDB)
 427 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 428 #elif defined(CONFIG_TARGET_T1042D4RDB)
 429 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 430 #endif
 431
 432 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 433         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 434         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 435         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 436         "netdev=eth0\0"                                         \
 437         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 438         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 439         "tftpflash=tftpboot $loadaddr $uboot && "               \
 440         "protect off $ubootaddr +$filesize && "                 \
 441         "erase $ubootaddr +$filesize && "                       \
 442         "cp.b $loadaddr $ubootaddr $filesize && "               \
 443         "protect on $ubootaddr +$filesize && "                  \
 444         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 445         "consoledev=ttyS0\0"                                    \
 446         "ramdiskaddr=2000000\0"                                 \
 447         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 448         "fdtaddr=1e00000\0"                                     \
 449         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 450         "bdev=sda3\0"
 451
 452 #include <asm/fsl_secure_boot.h>
 453
 454 #endif  /* __CONFIG_H */