include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #include <asm/config_mpc85xx.h>
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16
  17 #ifndef CONFIG_NXP_ESBC
  18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  19 #else
  20 #define CONFIG_SYS_FSL_PBL_PBI \
  21                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  22 #endif
  23
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #ifdef CONFIG_SPL_BUILD
  28 #define CONFIG_SPL_SKIP_RELOCATE
  29 #define CONFIG_SPL_COMMON_INIT_DDR
  30 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  31 #undef CONFIG_DM_I2C
  32 #endif
  33 #define RESET_VECTOR_OFFSET             0x27FFC
  34 #define BOOT_PAGE_OFFSET                0x27000
  35
  36 #ifdef CONFIG_MTD_RAW_NAND
  37 #ifdef CONFIG_NXP_ESBC
  38 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  39 /*
  40  * HDR would be appended at end of image and copied to DDR along
  41  * with U-Boot image.
  42  */
  43 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  44                                          CONFIG_U_BOOT_HDR_SIZE)
  45 #else
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #endif
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #ifdef CONFIG_TARGET_T1040RDB
  52 #define CONFIG_SYS_FSL_PBL_RCW \
  53 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  54 #endif
  55 #ifdef CONFIG_TARGET_T1042RDB_PI
  56 #define CONFIG_SYS_FSL_PBL_RCW \
  57 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  58 #endif
  59 #ifdef CONFIG_TARGET_T1042RDB
  60 #define CONFIG_SYS_FSL_PBL_RCW \
  61 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  62 #endif
  63 #ifdef CONFIG_TARGET_T1040D4RDB
  64 #define CONFIG_SYS_FSL_PBL_RCW \
  65 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  66 #endif
  67 #ifdef CONFIG_TARGET_T1042D4RDB
  68 #define CONFIG_SYS_FSL_PBL_RCW \
  69 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  70 #endif
  71 #endif
  72
  73 #ifdef CONFIG_SPIFLASH
  74 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  75 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  80 #ifndef CONFIG_SPL_BUILD
  81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  82 #endif
  83 #ifdef CONFIG_TARGET_T1040RDB
  84 #define CONFIG_SYS_FSL_PBL_RCW \
  85 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  86 #endif
  87 #ifdef CONFIG_TARGET_T1042RDB_PI
  88 #define CONFIG_SYS_FSL_PBL_RCW \
  89 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  90 #endif
  91 #ifdef CONFIG_TARGET_T1042RDB
  92 #define CONFIG_SYS_FSL_PBL_RCW \
  93 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  94 #endif
  95 #ifdef CONFIG_TARGET_T1040D4RDB
  96 #define CONFIG_SYS_FSL_PBL_RCW \
  97 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  98 #endif
  99 #ifdef CONFIG_TARGET_T1042D4RDB
 100 #define CONFIG_SYS_FSL_PBL_RCW \
 101 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 102 #endif
 103 #endif
 104
 105 #ifdef CONFIG_SDCARD
 106 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 108 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 109 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 111 #ifndef CONFIG_SPL_BUILD
 112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 113 #endif
 114 #ifdef CONFIG_TARGET_T1040RDB
 115 #define CONFIG_SYS_FSL_PBL_RCW \
 116 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 117 #endif
 118 #ifdef CONFIG_TARGET_T1042RDB_PI
 119 #define CONFIG_SYS_FSL_PBL_RCW \
 120 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 121 #endif
 122 #ifdef CONFIG_TARGET_T1042RDB
 123 #define CONFIG_SYS_FSL_PBL_RCW \
 124 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 125 #endif
 126 #ifdef CONFIG_TARGET_T1040D4RDB
 127 #define CONFIG_SYS_FSL_PBL_RCW \
 128 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 129 #endif
 130 #ifdef CONFIG_TARGET_T1042D4RDB
 131 #define CONFIG_SYS_FSL_PBL_RCW \
 132 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 133 #endif
 134 #endif
 135
 136 #endif
 137
 138 /* High Level Configuration Options */
 139 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 140
 141 /* support deep sleep */
 142 #define CONFIG_DEEP_SLEEP
 143
 144 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 145 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 146 #endif
 147
 148 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 149 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 150 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 151 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 152 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 153 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 154
 155 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 156
 157 #define CONFIG_ENV_OVERWRITE
 158
 159 #if defined(CONFIG_SPIFLASH)
 160 #elif defined(CONFIG_SDCARD)
 161 #define CONFIG_SYS_MMC_ENV_DEV          0
 162 #elif defined(CONFIG_MTD_RAW_NAND)
 163 #ifdef CONFIG_NXP_ESBC
 164 #define CONFIG_RAMBOOT_NAND
 165 #define CONFIG_BOOTSCRIPT_COPY_RAM
 166 #endif
 167 #endif
 168
 169 #define CONFIG_SYS_CLK_FREQ     100000000
 170 #define CONFIG_DDR_CLK_FREQ     66666666
 171
 172 /*
 173  * These can be toggled for performance analysis, otherwise use default.
 174  */
 175 #define CONFIG_SYS_CACHE_STASHING
 176 #define CONFIG_BACKSIDE_L2_CACHE
 177 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 178 #define CONFIG_BTB                      /* toggle branch predition */
 179 #define CONFIG_DDR_ECC
 180 #ifdef CONFIG_DDR_ECC
 181 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 182 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 183 #endif
 184
 185 #define CONFIG_ENABLE_36BIT_PHYS
 186
 187 #define CONFIG_ADDR_MAP
 188 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 189
 190 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 191 #define CONFIG_SYS_MEMTEST_END          0x00400000
 192
 193 /*
 194  *  Config the L3 Cache as L3 SRAM
 195  */
 196 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 197 /*
 198  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 199  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 200  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 201  */
 202 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 203 #define CONFIG_SYS_L3_SIZE              256 << 10
 204 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 205 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 206 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 207 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 208 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 209
 210 #define CONFIG_SYS_DCSRBAR              0xf0000000
 211 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 212
 213 /*
 214  * DDR Setup
 215  */
 216 #define CONFIG_VERY_BIG_RAM
 217 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 218 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 219
 220 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 221 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 222
 223 #define CONFIG_DDR_SPD
 224
 225 #define CONFIG_SYS_SPD_BUS_NUM  0
 226 #define SPD_EEPROM_ADDRESS      0x51
 227
 228 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 229
 230 /*
 231  * IFC Definitions
 232  */
 233 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 234 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 235
 236 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 237 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 238                                 CSPR_PORT_SIZE_16 | \
 239                                 CSPR_MSEL_NOR | \
 240                                 CSPR_V)
 241 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 242
 243 /*
 244  * TDM Definition
 245  */
 246 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 247
 248 /* NOR Flash Timing Params */
 249 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 250 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 251                                 FTIM0_NOR_TEADC(0x5) | \
 252                                 FTIM0_NOR_TEAHC(0x5))
 253 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 254                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 255                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 256 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 257                                 FTIM2_NOR_TCH(0x4) | \
 258                                 FTIM2_NOR_TWPH(0x0E) | \
 259                                 FTIM2_NOR_TWP(0x1c))
 260 #define CONFIG_SYS_NOR_FTIM3    0x0
 261
 262 #define CONFIG_SYS_FLASH_QUIET_TEST
 263 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 264
 265 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 266 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 267 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 268 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 269
 270 #define CONFIG_SYS_FLASH_EMPTY_INFO
 271 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 272
 273 /* CPLD on IFC */
 274 #define CPLD_LBMAP_MASK                 0x3F
 275 #define CPLD_BANK_SEL_MASK              0x07
 276 #define CPLD_BANK_OVERRIDE              0x40
 277 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 278 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 279 #define CPLD_LBMAP_RESET                0xFF
 280 #define CPLD_LBMAP_SHIFT                0x03
 281
 282 #if defined(CONFIG_TARGET_T1042RDB_PI)
 283 #define CPLD_DIU_SEL_DFP                0x80
 284 #elif defined(CONFIG_TARGET_T1042D4RDB)
 285 #define CPLD_DIU_SEL_DFP                0xc0
 286 #endif
 287
 288 #if defined(CONFIG_TARGET_T1040D4RDB)
 289 #define CPLD_INT_MASK_ALL               0xFF
 290 #define CPLD_INT_MASK_THERM             0x80
 291 #define CPLD_INT_MASK_DVI_DFP           0x40
 292 #define CPLD_INT_MASK_QSGMII1           0x20
 293 #define CPLD_INT_MASK_QSGMII2           0x10
 294 #define CPLD_INT_MASK_SGMI1             0x08
 295 #define CPLD_INT_MASK_SGMI2             0x04
 296 #define CPLD_INT_MASK_TDMR1             0x02
 297 #define CPLD_INT_MASK_TDMR2             0x01
 298 #endif
 299
 300 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 301 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 302 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 303 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 304                                 | CSPR_PORT_SIZE_8 \
 305                                 | CSPR_MSEL_GPCM \
 306                                 | CSPR_V)
 307 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 308 #define CONFIG_SYS_CSOR2        0x0
 309 /* CPLD Timing parameters for IFC CS2 */
 310 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 311                                         FTIM0_GPCM_TEADC(0x0e) | \
 312                                         FTIM0_GPCM_TEAHC(0x0e))
 313 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 314                                         FTIM1_GPCM_TRAD(0x1f))
 315 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 316                                         FTIM2_GPCM_TCH(0x8) | \
 317                                         FTIM2_GPCM_TWP(0x1f))
 318 #define CONFIG_SYS_CS2_FTIM3            0x0
 319
 320 /* NAND Flash on IFC */
 321 #define CONFIG_NAND_FSL_IFC
 322 #define CONFIG_SYS_NAND_BASE            0xff800000
 323 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 324
 325 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 326 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 327                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 328                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 329                                 | CSPR_V)
 330 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 331
 332 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 333                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 334                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 335                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 336                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 337                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 338                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 339
 340 #define CONFIG_SYS_NAND_ONFI_DETECTION
 341
 342 /* ONFI NAND Flash mode0 Timing Params */
 343 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 344                                         FTIM0_NAND_TWP(0x18)   | \
 345                                         FTIM0_NAND_TWCHT(0x07) | \
 346                                         FTIM0_NAND_TWH(0x0a))
 347 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 348                                         FTIM1_NAND_TWBE(0x39)  | \
 349                                         FTIM1_NAND_TRR(0x0e)   | \
 350                                         FTIM1_NAND_TRP(0x18))
 351 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 352                                         FTIM2_NAND_TREH(0x0a) | \
 353                                         FTIM2_NAND_TWHRE(0x1e))
 354 #define CONFIG_SYS_NAND_FTIM3           0x0
 355
 356 #define CONFIG_SYS_NAND_DDR_LAW         11
 357 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 358 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 359
 360 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 361
 362 #if defined(CONFIG_MTD_RAW_NAND)
 363 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 364 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 365 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 366 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 367 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 368 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 369 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 370 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 371 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 372 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 373 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 374 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 375 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 376 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 377 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 378 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 379 #else
 380 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 381 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 382 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 383 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 384 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 385 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 386 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 387 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 388 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 389 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 390 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 391 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 392 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 393 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 394 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 395 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 396 #endif
 397
 398 #ifdef CONFIG_SPL_BUILD
 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 400 #else
 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 402 #endif
 403
 404 #if defined(CONFIG_RAMBOOT_PBL)
 405 #define CONFIG_SYS_RAMBOOT
 406 #endif
 407
 408 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 409 #if defined(CONFIG_MTD_RAW_NAND)
 410 #define CONFIG_A008044_WORKAROUND
 411 #endif
 412 #endif
 413
 414 #define CONFIG_HWCONFIG
 415
 416 /* define to use L1 as initial stack */
 417 #define CONFIG_L1_INIT_RAM
 418 #define CONFIG_SYS_INIT_RAM_LOCK
 419 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 422 /* The assembler doesn't like typecast */
 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 424         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 425           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 426 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 427
 428 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 429                                         GENERATED_GBL_DATA_SIZE)
 430 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 431
 432 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 433 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 434
 435 /* Serial Port - controlled on board with jumper J8
 436  * open - index 2
 437  * shorted - index 1
 438  */
 439 #define CONFIG_SYS_NS16550_SERIAL
 440 #define CONFIG_SYS_NS16550_REG_SIZE     1
 441 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 442
 443 #define CONFIG_SYS_BAUDRATE_TABLE       \
 444         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 445
 446 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 447 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 448 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 449 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 450
 451 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 452 /* Video */
 453 #define CONFIG_FSL_DIU_FB
 454
 455 #ifdef CONFIG_FSL_DIU_FB
 456 #define CONFIG_FSL_DIU_CH7301
 457 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 458 #define CONFIG_VIDEO_LOGO
 459 #define CONFIG_VIDEO_BMP_LOGO
 460 #endif
 461 #endif
 462
 463 /* I2C */
 464 #ifndef CONFIG_DM_I2C
 465 #define CONFIG_SYS_I2C
 466 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 467 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 468 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 469 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 470 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 471 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 472 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 473 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 474 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 475 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 476 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 477 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 478 #else
 479 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 480 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 481 #endif
 482
 483 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 484 /* I2C bus multiplexer */
 485 #define I2C_MUX_PCA_ADDR                0x70
 486 #define I2C_MUX_CH_DEFAULT      0x8
 487
 488 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 489         defined(CONFIG_TARGET_T1040D4RDB)       || \
 490         defined(CONFIG_TARGET_T1042D4RDB)
 491 /* LDI/DVI Encoder for display */
 492 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 493 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 494 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 495
 496 /*
 497  * RTC configuration
 498  */
 499 #define RTC
 500 #define CONFIG_RTC_DS1337               1
 501 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 502
 503 /*DVI encoder*/
 504 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 505 #endif
 506
 507 /*
 508  * eSPI - Enhanced SPI
 509  */
 510
 511 /*
 512  * General PCI
 513  * Memory space is mapped 1-1, but I/O space must start from 0.
 514  */
 515
 516 #ifdef CONFIG_PCI
 517 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 518 #ifdef CONFIG_PCIE1
 519 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 520 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 521 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 522 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 523 #endif
 524
 525 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 526 #ifdef CONFIG_PCIE2
 527 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 528 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 529 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 530 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 531 #endif
 532
 533 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 534 #ifdef CONFIG_PCIE3
 535 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 536 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 537 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 538 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 539 #endif
 540
 541 /* controller 4, Base address 203000 */
 542 #ifdef CONFIG_PCIE4
 543 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 544 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 545 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 546 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 547 #endif
 548
 549 #if !defined(CONFIG_DM_PCI)
 550 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 551 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 552 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 553 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 554 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 555 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 556 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 557 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 558 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 559 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 560 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 561 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 562 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 563 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 564 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 565 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 566 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 567 #define CONFIG_PCI_INDIRECT_BRIDGE
 568 #endif
 569 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 570 #endif  /* CONFIG_PCI */
 571
 572 /* SATA */
 573 #define CONFIG_FSL_SATA_V2
 574 #ifdef CONFIG_FSL_SATA_V2
 575 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 576 #define CONFIG_SATA1
 577 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 578 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 579
 580 #define CONFIG_LBA48
 581 #endif
 582
 583 /*
 584 * USB
 585 */
 586 #define CONFIG_HAS_FSL_DR_USB
 587
 588 #ifdef CONFIG_HAS_FSL_DR_USB
 589 #ifdef CONFIG_USB_EHCI_HCD
 590 #define CONFIG_USB_EHCI_FSL
 591 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 592 #endif
 593 #endif
 594
 595 #ifdef CONFIG_MMC
 596 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 597 #endif
 598
 599 /* Qman/Bman */
 600 #ifndef CONFIG_NOBQFMAN
 601 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 602 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 603 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 604 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 605 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 606 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 607 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 608 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 609 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 610                                         CONFIG_SYS_BMAN_CENA_SIZE)
 611 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 612 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 613 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 614 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 615 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 616 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 617 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 618 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 619 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 620 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 621 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 622                                         CONFIG_SYS_QMAN_CENA_SIZE)
 623 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 624 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 625
 626 #define CONFIG_SYS_DPAA_FMAN
 627 #define CONFIG_SYS_DPAA_PME
 628
 629 #define CONFIG_U_QE
 630
 631 /* Default address of microcode for the Linux Fman driver */
 632 #if defined(CONFIG_SPIFLASH)
 633 /*
 634  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 635  * env, so we got 0x110000.
 636  */
 637 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 638 #elif defined(CONFIG_SDCARD)
 639 /*
 640  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 641  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 642  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 643  */
 644 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 645 #elif defined(CONFIG_MTD_RAW_NAND)
 646 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 647 #else
 648 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 649 #endif
 650
 651 #if defined(CONFIG_SPIFLASH)
 652 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 653 #elif defined(CONFIG_SDCARD)
 654 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 655 #elif defined(CONFIG_MTD_RAW_NAND)
 656 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 657 #else
 658 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 659 #endif
 660
 661 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 662 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 663 #endif /* CONFIG_NOBQFMAN */
 664
 665 #ifdef CONFIG_FMAN_ENET
 666 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 667 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 668 #elif defined(CONFIG_TARGET_T1040D4RDB)
 669 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 670 #elif defined(CONFIG_TARGET_T1042D4RDB)
 671 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 672 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 673 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 674 #endif
 675
 676 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 677 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 678 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 679 #else
 680 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 681 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 682 #endif
 683
 684 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 685 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 686 #define CONFIG_VSC9953
 687 #ifdef CONFIG_TARGET_T1040RDB
 688 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 689 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 690 #else
 691 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 692 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 693 #endif
 694 #endif
 695
 696 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 697 #endif
 698
 699 /*
 700  * Environment
 701  */
 702 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 703 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 704
 705 /*
 706  * Miscellaneous configurable options
 707  */
 708 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 709
 710 /*
 711  * For booting Linux, the board info and command line data
 712  * have to be in the first 64 MB of memory, since this is
 713  * the maximum mapped by the Linux kernel during initialization.
 714  */
 715 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 716 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 717
 718 #ifdef CONFIG_CMD_KGDB
 719 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 720 #endif
 721
 722 /*
 723  * Dynamic MTD Partition support with mtdparts
 724  */
 725
 726 /*
 727  * Environment Configuration
 728  */
 729 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 730 #define CONFIG_BOOTFILE         "uImage"
 731 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 732
 733 /* default location for tftp and bootm */
 734 #define CONFIG_LOADADDR         1000000
 735
 736 #define __USB_PHY_TYPE  utmi
 737 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 738
 739 #ifdef CONFIG_TARGET_T1040RDB
 740 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 741 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 742 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 743 #elif defined(CONFIG_TARGET_T1042RDB)
 744 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 745 #elif defined(CONFIG_TARGET_T1040D4RDB)
 746 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 747 #elif defined(CONFIG_TARGET_T1042D4RDB)
 748 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 749 #endif
 750
 751 #ifdef CONFIG_FSL_DIU_FB
 752 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 753 #else
 754 #define DIU_ENVIRONMENT
 755 #endif
 756
 757 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 758         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 759         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 760         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 761         "netdev=eth0\0"                                         \
 762         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 763         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 764         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 765         "tftpflash=tftpboot $loadaddr $uboot && "               \
 766         "protect off $ubootaddr +$filesize && "                 \
 767         "erase $ubootaddr +$filesize && "                       \
 768         "cp.b $loadaddr $ubootaddr $filesize && "               \
 769         "protect on $ubootaddr +$filesize && "                  \
 770         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 771         "consoledev=ttyS0\0"                                    \
 772         "ramdiskaddr=2000000\0"                                 \
 773         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 774         "fdtaddr=1e00000\0"                                     \
 775         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 776         "bdev=sda3\0"
 777
 778 #define CONFIG_LINUX                       \
 779         "setenv bootargs root=/dev/ram rw "            \
 780         "console=$consoledev,$baudrate $othbootargs;"  \
 781         "setenv ramdiskaddr 0x02000000;"               \
 782         "setenv fdtaddr 0x00c00000;"                   \
 783         "setenv loadaddr 0x1000000;"                   \
 784         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 785
 786 #define CONFIG_HDBOOT                                   \
 787         "setenv bootargs root=/dev/$bdev rw "           \
 788         "console=$consoledev,$baudrate $othbootargs;"   \
 789         "tftp $loadaddr $bootfile;"                     \
 790         "tftp $fdtaddr $fdtfile;"                       \
 791         "bootm $loadaddr - $fdtaddr"
 792
 793 #define CONFIG_NFSBOOTCOMMAND                   \
 794         "setenv bootargs root=/dev/nfs rw "     \
 795         "nfsroot=$serverip:$rootpath "          \
 796         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 797         "console=$consoledev,$baudrate $othbootargs;"   \
 798         "tftp $loadaddr $bootfile;"             \
 799         "tftp $fdtaddr $fdtfile;"               \
 800         "bootm $loadaddr - $fdtaddr"
 801
 802 #define CONFIG_RAMBOOTCOMMAND                           \
 803         "setenv bootargs root=/dev/ram rw "             \
 804         "console=$consoledev,$baudrate $othbootargs;"   \
 805         "tftp $ramdiskaddr $ramdiskfile;"               \
 806         "tftp $loadaddr $bootfile;"                     \
 807         "tftp $fdtaddr $fdtfile;"                       \
 808         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 809
 810 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 811
 812 #include <asm/fsl_secure_boot.h>
 813
 814 #endif  /* __CONFIG_H */