1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_PAD_TO 0x40000
20 #define CONFIG_SPL_MAX_SIZE 0x28000
21 #ifdef CONFIG_SPL_BUILD
22 #define CONFIG_SPL_SKIP_RELOCATE
23 #define CONFIG_SPL_COMMON_INIT_DDR
24 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
29 #ifdef CONFIG_MTD_RAW_NAND
30 #ifdef CONFIG_NXP_ESBC
31 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
33 * HDR would be appended at end of image and copied to DDR along
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
37 CONFIG_U_BOOT_HDR_SIZE)
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
42 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
45 #ifdef CONFIG_SPIFLASH
46 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
47 #define CONFIG_SPL_SPI_FLASH_MINIMAL
48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
52 #ifndef CONFIG_SPL_BUILD
53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
59 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
60 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
61 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
62 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
63 #ifndef CONFIG_SPL_BUILD
64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 /* High Level Configuration Options */
71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
73 /* support deep sleep */
74 #define CONFIG_DEEP_SLEEP
76 #ifndef CONFIG_RESET_VECTOR_ADDRESS
77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
81 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
82 #define CONFIG_PCIE1 /* PCIE controller 1 */
83 #define CONFIG_PCIE2 /* PCIE controller 2 */
84 #define CONFIG_PCIE3 /* PCIE controller 3 */
85 #define CONFIG_PCIE4 /* PCIE controller 4 */
87 #if defined(CONFIG_SPIFLASH)
88 #elif defined(CONFIG_MTD_RAW_NAND)
89 #ifdef CONFIG_NXP_ESBC
90 #define CONFIG_RAMBOOT_NAND
91 #define CONFIG_BOOTSCRIPT_COPY_RAM
96 * These can be toggled for performance analysis, otherwise use default.
98 #define CONFIG_SYS_CACHE_STASHING
99 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
100 #ifdef CONFIG_DDR_ECC
101 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
104 #define CONFIG_ENABLE_36BIT_PHYS
107 * Config the L3 Cache as L3 SRAM
109 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
111 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
112 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
113 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
115 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
116 #define CONFIG_SYS_L3_SIZE 256 << 10
117 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
118 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
119 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
120 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
121 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
123 #define CONFIG_SYS_DCSRBAR 0xf0000000
124 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
129 #define CONFIG_VERY_BIG_RAM
130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
133 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
135 #define CONFIG_SYS_SPD_BUS_NUM 0
136 #define SPD_EEPROM_ADDRESS 0x51
138 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
143 #define CONFIG_SYS_FLASH_BASE 0xe8000000
144 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
146 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
147 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
148 CSPR_PORT_SIZE_16 | \
151 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
156 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
158 /* NOR Flash Timing Params */
159 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
160 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
161 FTIM0_NOR_TEADC(0x5) | \
162 FTIM0_NOR_TEAHC(0x5))
163 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
164 FTIM1_NOR_TRAD_NOR(0x1A) |\
165 FTIM1_NOR_TSEQRAD_NOR(0x13))
166 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
167 FTIM2_NOR_TCH(0x4) | \
168 FTIM2_NOR_TWPH(0x0E) | \
170 #define CONFIG_SYS_NOR_FTIM3 0x0
172 #define CONFIG_SYS_FLASH_QUIET_TEST
173 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
175 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
179 #define CONFIG_SYS_FLASH_EMPTY_INFO
180 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
183 #define CPLD_LBMAP_MASK 0x3F
184 #define CPLD_BANK_SEL_MASK 0x07
185 #define CPLD_BANK_OVERRIDE 0x40
186 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
187 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
188 #define CPLD_LBMAP_RESET 0xFF
189 #define CPLD_LBMAP_SHIFT 0x03
191 #if defined(CONFIG_TARGET_T1042RDB_PI)
192 #define CPLD_DIU_SEL_DFP 0x80
193 #elif defined(CONFIG_TARGET_T1042D4RDB)
194 #define CPLD_DIU_SEL_DFP 0xc0
197 #if defined(CONFIG_TARGET_T1040D4RDB)
198 #define CPLD_INT_MASK_ALL 0xFF
199 #define CPLD_INT_MASK_THERM 0x80
200 #define CPLD_INT_MASK_DVI_DFP 0x40
201 #define CPLD_INT_MASK_QSGMII1 0x20
202 #define CPLD_INT_MASK_QSGMII2 0x10
203 #define CPLD_INT_MASK_SGMI1 0x08
204 #define CPLD_INT_MASK_SGMI2 0x04
205 #define CPLD_INT_MASK_TDMR1 0x02
206 #define CPLD_INT_MASK_TDMR2 0x01
209 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
210 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
211 #define CONFIG_SYS_CSPR2_EXT (0xf)
212 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
216 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
217 #define CONFIG_SYS_CSOR2 0x0
218 /* CPLD Timing parameters for IFC CS2 */
219 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
220 FTIM0_GPCM_TEADC(0x0e) | \
221 FTIM0_GPCM_TEAHC(0x0e))
222 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
223 FTIM1_GPCM_TRAD(0x1f))
224 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
225 FTIM2_GPCM_TCH(0x8) | \
226 FTIM2_GPCM_TWP(0x1f))
227 #define CONFIG_SYS_CS2_FTIM3 0x0
229 /* NAND Flash on IFC */
230 #define CONFIG_SYS_NAND_BASE 0xff800000
231 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
233 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
234 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
235 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
236 | CSPR_MSEL_NAND /* MSEL = NAND */ \
238 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
240 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
241 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
242 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
243 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
244 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
245 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
246 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
248 /* ONFI NAND Flash mode0 Timing Params */
249 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
250 FTIM0_NAND_TWP(0x18) | \
251 FTIM0_NAND_TWCHT(0x07) | \
252 FTIM0_NAND_TWH(0x0a))
253 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
254 FTIM1_NAND_TWBE(0x39) | \
255 FTIM1_NAND_TRR(0x0e) | \
256 FTIM1_NAND_TRP(0x18))
257 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
258 FTIM2_NAND_TREH(0x0a) | \
259 FTIM2_NAND_TWHRE(0x1e))
260 #define CONFIG_SYS_NAND_FTIM3 0x0
262 #define CONFIG_SYS_NAND_DDR_LAW 11
263 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
264 #define CONFIG_SYS_MAX_NAND_DEVICE 1
266 #if defined(CONFIG_MTD_RAW_NAND)
267 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
268 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
269 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
270 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
271 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
272 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
273 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
274 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
275 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
276 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
277 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
278 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
279 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
280 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
281 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
282 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
284 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
285 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
286 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
293 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
295 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
296 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
297 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
298 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
299 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
302 #ifdef CONFIG_SPL_BUILD
303 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
308 #if defined(CONFIG_RAMBOOT_PBL)
309 #define CONFIG_SYS_RAMBOOT
312 #define CONFIG_HWCONFIG
314 /* define to use L1 as initial stack */
315 #define CONFIG_L1_INIT_RAM
316 #define CONFIG_SYS_INIT_RAM_LOCK
317 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
320 /* The assembler doesn't like typecast */
321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
322 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
323 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
324 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
326 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
327 GENERATED_GBL_DATA_SIZE)
328 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
330 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
332 /* Serial Port - controlled on board with jumper J8
336 #define CONFIG_SYS_NS16550_SERIAL
337 #define CONFIG_SYS_NS16550_REG_SIZE 1
338 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
340 #define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
345 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
346 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
348 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
350 #define CONFIG_FSL_DIU_FB
352 #ifdef CONFIG_FSL_DIU_FB
353 #define CONFIG_FSL_DIU_CH7301
354 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
355 #define CONFIG_VIDEO_BMP_LOGO
361 /* I2C bus multiplexer */
362 #define I2C_MUX_PCA_ADDR 0x70
363 #define I2C_MUX_CH_DEFAULT 0x8
365 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
366 defined(CONFIG_TARGET_T1040D4RDB) || \
367 defined(CONFIG_TARGET_T1042D4RDB)
368 /* LDI/DVI Encoder for display */
369 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
370 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
371 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
377 #define CONFIG_RTC_DS1337 1
378 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
381 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
385 * eSPI - Enhanced SPI
390 * Memory space is mapped 1-1, but I/O space must start from 0.
394 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
396 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
398 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
399 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
402 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
404 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
405 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
406 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
407 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
410 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
412 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
413 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
414 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
415 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
418 /* controller 4, Base address 203000 */
420 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
421 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
422 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
423 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
426 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
427 #endif /* CONFIG_PCI */
430 #define CONFIG_FSL_SATA_V2
431 #ifdef CONFIG_FSL_SATA_V2
433 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
434 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
442 #define CONFIG_HAS_FSL_DR_USB
444 #ifdef CONFIG_HAS_FSL_DR_USB
445 #ifdef CONFIG_USB_EHCI_HCD
446 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
451 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
455 #ifndef CONFIG_NOBQFMAN
456 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
457 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
458 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
459 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
460 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
461 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
462 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
463 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
464 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
465 CONFIG_SYS_BMAN_CENA_SIZE)
466 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
467 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
468 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
469 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
470 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
471 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
472 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
473 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
474 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
475 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
476 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
477 CONFIG_SYS_QMAN_CENA_SIZE)
478 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
479 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
481 #define CONFIG_SYS_DPAA_FMAN
482 #define CONFIG_SYS_DPAA_PME
484 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
485 #endif /* CONFIG_NOBQFMAN */
487 #ifdef CONFIG_FMAN_ENET
488 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
489 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
490 #elif defined(CONFIG_TARGET_T1040D4RDB)
491 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
492 #elif defined(CONFIG_TARGET_T1042D4RDB)
493 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
494 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
495 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
498 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
499 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
500 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
502 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
503 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
506 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
507 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
508 #define CONFIG_VSC9953
509 #ifdef CONFIG_TARGET_T1040RDB
510 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
511 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
513 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
514 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
522 #define CONFIG_LOADS_ECHO /* echo on for serial download */
523 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
526 * Miscellaneous configurable options
530 * For booting Linux, the board info and command line data
531 * have to be in the first 64 MB of memory, since this is
532 * the maximum mapped by the Linux kernel during initialization.
534 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
535 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
538 * Dynamic MTD Partition support with mtdparts
542 * Environment Configuration
544 #define CONFIG_ROOTPATH "/opt/nfsroot"
545 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
547 #define __USB_PHY_TYPE utmi
548 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
550 #ifdef CONFIG_TARGET_T1040RDB
551 #define FDTFILE "t1040rdb/t1040rdb.dtb"
552 #elif defined(CONFIG_TARGET_T1042RDB_PI)
553 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
554 #elif defined(CONFIG_TARGET_T1042RDB)
555 #define FDTFILE "t1042rdb/t1042rdb.dtb"
556 #elif defined(CONFIG_TARGET_T1040D4RDB)
557 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
558 #elif defined(CONFIG_TARGET_T1042D4RDB)
559 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
562 #ifdef CONFIG_FSL_DIU_FB
563 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
565 #define DIU_ENVIRONMENT
568 #define CONFIG_EXTRA_ENV_SETTINGS \
569 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
570 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
571 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
573 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
574 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
575 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
576 "tftpflash=tftpboot $loadaddr $uboot && " \
577 "protect off $ubootaddr +$filesize && " \
578 "erase $ubootaddr +$filesize && " \
579 "cp.b $loadaddr $ubootaddr $filesize && " \
580 "protect on $ubootaddr +$filesize && " \
581 "cmp.b $loadaddr $ubootaddr $filesize\0" \
582 "consoledev=ttyS0\0" \
583 "ramdiskaddr=2000000\0" \
584 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
585 "fdtaddr=1e00000\0" \
586 "fdtfile=" __stringify(FDTFILE) "\0" \
589 #include <asm/fsl_secure_boot.h>
591 #endif /* __CONFIG_H */