include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * T104x RDB board configuration file
  11  */
  12 #include <asm/config_mpc85xx.h>
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15
  16 #ifndef CONFIG_SECURE_BOOT
  17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  18 #else
  19 #define CONFIG_SYS_FSL_PBL_PBI \
  20                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  21 #endif
  22
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #ifdef CONFIG_SPL_BUILD
  27 #define CONFIG_SPL_SKIP_RELOCATE
  28 #define CONFIG_SPL_COMMON_INIT_DDR
  29 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  30 #endif
  31 #define RESET_VECTOR_OFFSET             0x27FFC
  32 #define BOOT_PAGE_OFFSET                0x27000
  33
  34 #ifdef CONFIG_NAND
  35 #ifdef CONFIG_SECURE_BOOT
  36 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  37 /*
  38  * HDR would be appended at end of image and copied to DDR along
  39  * with U-Boot image.
  40  */
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  42                                          CONFIG_U_BOOT_HDR_SIZE)
  43 #else
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #endif
  46 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  47 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  48 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  49 #ifdef CONFIG_TARGET_T1040RDB
  50 #define CONFIG_SYS_FSL_PBL_RCW \
  51 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  52 #endif
  53 #ifdef CONFIG_TARGET_T1042RDB_PI
  54 #define CONFIG_SYS_FSL_PBL_RCW \
  55 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  56 #endif
  57 #ifdef CONFIG_TARGET_T1042RDB
  58 #define CONFIG_SYS_FSL_PBL_RCW \
  59 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  60 #endif
  61 #ifdef CONFIG_TARGET_T1040D4RDB
  62 #define CONFIG_SYS_FSL_PBL_RCW \
  63 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  64 #endif
  65 #ifdef CONFIG_TARGET_T1042D4RDB
  66 #define CONFIG_SYS_FSL_PBL_RCW \
  67 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  68 #endif
  69 #endif
  70
  71 #ifdef CONFIG_SPIFLASH
  72 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  73 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  78 #ifndef CONFIG_SPL_BUILD
  79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  80 #endif
  81 #ifdef CONFIG_TARGET_T1040RDB
  82 #define CONFIG_SYS_FSL_PBL_RCW \
  83 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  84 #endif
  85 #ifdef CONFIG_TARGET_T1042RDB_PI
  86 #define CONFIG_SYS_FSL_PBL_RCW \
  87 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  88 #endif
  89 #ifdef CONFIG_TARGET_T1042RDB
  90 #define CONFIG_SYS_FSL_PBL_RCW \
  91 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  92 #endif
  93 #ifdef CONFIG_TARGET_T1040D4RDB
  94 #define CONFIG_SYS_FSL_PBL_RCW \
  95 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  96 #endif
  97 #ifdef CONFIG_TARGET_T1042D4RDB
  98 #define CONFIG_SYS_FSL_PBL_RCW \
  99 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 100 #endif
 101 #endif
 102
 103 #ifdef CONFIG_SDCARD
 104 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 105 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 106 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 107 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 108 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 109 #ifndef CONFIG_SPL_BUILD
 110 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 111 #endif
 112 #ifdef CONFIG_TARGET_T1040RDB
 113 #define CONFIG_SYS_FSL_PBL_RCW \
 114 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 115 #endif
 116 #ifdef CONFIG_TARGET_T1042RDB_PI
 117 #define CONFIG_SYS_FSL_PBL_RCW \
 118 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 119 #endif
 120 #ifdef CONFIG_TARGET_T1042RDB
 121 #define CONFIG_SYS_FSL_PBL_RCW \
 122 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 123 #endif
 124 #ifdef CONFIG_TARGET_T1040D4RDB
 125 #define CONFIG_SYS_FSL_PBL_RCW \
 126 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 127 #endif
 128 #ifdef CONFIG_TARGET_T1042D4RDB
 129 #define CONFIG_SYS_FSL_PBL_RCW \
 130 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 131 #endif
 132 #endif
 133
 134 #endif
 135
 136 /* High Level Configuration Options */
 137 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 138
 139 /* support deep sleep */
 140 #define CONFIG_DEEP_SLEEP
 141
 142 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 143 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 144 #endif
 145
 146 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 147 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 148 #define CONFIG_PCI_INDIRECT_BRIDGE
 149 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 150 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 151 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 152 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 153
 154 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 155 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 156
 157 #define CONFIG_ENV_OVERWRITE
 158
 159 #if defined(CONFIG_SPIFLASH)
 160 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 161 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 162 #define CONFIG_ENV_SECT_SIZE            0x10000
 163 #elif defined(CONFIG_SDCARD)
 164 #define CONFIG_SYS_MMC_ENV_DEV          0
 165 #define CONFIG_ENV_SIZE                 0x2000
 166 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 167 #elif defined(CONFIG_NAND)
 168 #ifdef CONFIG_SECURE_BOOT
 169 #define CONFIG_RAMBOOT_NAND
 170 #define CONFIG_BOOTSCRIPT_COPY_RAM
 171 #endif
 172 #define CONFIG_ENV_SIZE                 0x2000
 173 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 174 #else
 175 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 176 #define CONFIG_ENV_SIZE         0x2000
 177 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 178 #endif
 179
 180 #define CONFIG_SYS_CLK_FREQ     100000000
 181 #define CONFIG_DDR_CLK_FREQ     66666666
 182
 183 /*
 184  * These can be toggled for performance analysis, otherwise use default.
 185  */
 186 #define CONFIG_SYS_CACHE_STASHING
 187 #define CONFIG_BACKSIDE_L2_CACHE
 188 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 189 #define CONFIG_BTB                      /* toggle branch predition */
 190 #define CONFIG_DDR_ECC
 191 #ifdef CONFIG_DDR_ECC
 192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 193 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 194 #endif
 195
 196 #define CONFIG_ENABLE_36BIT_PHYS
 197
 198 #define CONFIG_ADDR_MAP
 199 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 200
 201 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 202 #define CONFIG_SYS_MEMTEST_END          0x00400000
 203
 204 /*
 205  *  Config the L3 Cache as L3 SRAM
 206  */
 207 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 208 /*
 209  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 210  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 211  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 212  */
 213 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 214 #define CONFIG_SYS_L3_SIZE              256 << 10
 215 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 216 #ifdef CONFIG_RAMBOOT_PBL
 217 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 218 #endif
 219 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 220 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 221 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 222
 223 #define CONFIG_SYS_DCSRBAR              0xf0000000
 224 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 225
 226 /*
 227  * DDR Setup
 228  */
 229 #define CONFIG_VERY_BIG_RAM
 230 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 231 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 232
 233 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 234 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 235
 236 #define CONFIG_DDR_SPD
 237
 238 #define CONFIG_SYS_SPD_BUS_NUM  0
 239 #define SPD_EEPROM_ADDRESS      0x51
 240
 241 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 242
 243 /*
 244  * IFC Definitions
 245  */
 246 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 247 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 248
 249 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 250 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 251                                 CSPR_PORT_SIZE_16 | \
 252                                 CSPR_MSEL_NOR | \
 253                                 CSPR_V)
 254 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 255
 256 /*
 257  * TDM Definition
 258  */
 259 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 260
 261 /* NOR Flash Timing Params */
 262 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 263 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 264                                 FTIM0_NOR_TEADC(0x5) | \
 265                                 FTIM0_NOR_TEAHC(0x5))
 266 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 267                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 268                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 269 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 270                                 FTIM2_NOR_TCH(0x4) | \
 271                                 FTIM2_NOR_TWPH(0x0E) | \
 272                                 FTIM2_NOR_TWP(0x1c))
 273 #define CONFIG_SYS_NOR_FTIM3    0x0
 274
 275 #define CONFIG_SYS_FLASH_QUIET_TEST
 276 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 277
 278 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 279 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 280 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 281 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 282
 283 #define CONFIG_SYS_FLASH_EMPTY_INFO
 284 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 285
 286 /* CPLD on IFC */
 287 #define CPLD_LBMAP_MASK                 0x3F
 288 #define CPLD_BANK_SEL_MASK              0x07
 289 #define CPLD_BANK_OVERRIDE              0x40
 290 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 291 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 292 #define CPLD_LBMAP_RESET                0xFF
 293 #define CPLD_LBMAP_SHIFT                0x03
 294
 295 #if defined(CONFIG_TARGET_T1042RDB_PI)
 296 #define CPLD_DIU_SEL_DFP                0x80
 297 #elif defined(CONFIG_TARGET_T1042D4RDB)
 298 #define CPLD_DIU_SEL_DFP                0xc0
 299 #endif
 300
 301 #if defined(CONFIG_TARGET_T1040D4RDB)
 302 #define CPLD_INT_MASK_ALL               0xFF
 303 #define CPLD_INT_MASK_THERM             0x80
 304 #define CPLD_INT_MASK_DVI_DFP           0x40
 305 #define CPLD_INT_MASK_QSGMII1           0x20
 306 #define CPLD_INT_MASK_QSGMII2           0x10
 307 #define CPLD_INT_MASK_SGMI1             0x08
 308 #define CPLD_INT_MASK_SGMI2             0x04
 309 #define CPLD_INT_MASK_TDMR1             0x02
 310 #define CPLD_INT_MASK_TDMR2             0x01
 311 #endif
 312
 313 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 314 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 315 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 316 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 317                                 | CSPR_PORT_SIZE_8 \
 318                                 | CSPR_MSEL_GPCM \
 319                                 | CSPR_V)
 320 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 321 #define CONFIG_SYS_CSOR2        0x0
 322 /* CPLD Timing parameters for IFC CS2 */
 323 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 324                                         FTIM0_GPCM_TEADC(0x0e) | \
 325                                         FTIM0_GPCM_TEAHC(0x0e))
 326 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 327                                         FTIM1_GPCM_TRAD(0x1f))
 328 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 329                                         FTIM2_GPCM_TCH(0x8) | \
 330                                         FTIM2_GPCM_TWP(0x1f))
 331 #define CONFIG_SYS_CS2_FTIM3            0x0
 332
 333 /* NAND Flash on IFC */
 334 #define CONFIG_NAND_FSL_IFC
 335 #define CONFIG_SYS_NAND_BASE            0xff800000
 336 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 337
 338 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 339 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 340                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 341                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 342                                 | CSPR_V)
 343 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 344
 345 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 346                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 347                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 348                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 349                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 350                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 351                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 352
 353 #define CONFIG_SYS_NAND_ONFI_DETECTION
 354
 355 /* ONFI NAND Flash mode0 Timing Params */
 356 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 357                                         FTIM0_NAND_TWP(0x18)   | \
 358                                         FTIM0_NAND_TWCHT(0x07) | \
 359                                         FTIM0_NAND_TWH(0x0a))
 360 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 361                                         FTIM1_NAND_TWBE(0x39)  | \
 362                                         FTIM1_NAND_TRR(0x0e)   | \
 363                                         FTIM1_NAND_TRP(0x18))
 364 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 365                                         FTIM2_NAND_TREH(0x0a) | \
 366                                         FTIM2_NAND_TWHRE(0x1e))
 367 #define CONFIG_SYS_NAND_FTIM3           0x0
 368
 369 #define CONFIG_SYS_NAND_DDR_LAW         11
 370 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 371 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 372
 373 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 374
 375 #if defined(CONFIG_NAND)
 376 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 377 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 378 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 379 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 380 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 381 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 382 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 383 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 384 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 385 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 386 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 387 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 388 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 389 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 390 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 391 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 392 #else
 393 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 394 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 395 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 396 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 397 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 398 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 399 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 400 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 401 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 402 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 403 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 404 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 405 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 406 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 407 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 408 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 409 #endif
 410
 411 #ifdef CONFIG_SPL_BUILD
 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 413 #else
 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 415 #endif
 416
 417 #if defined(CONFIG_RAMBOOT_PBL)
 418 #define CONFIG_SYS_RAMBOOT
 419 #endif
 420
 421 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 422 #if defined(CONFIG_NAND)
 423 #define CONFIG_A008044_WORKAROUND
 424 #endif
 425 #endif
 426
 427 #define CONFIG_HWCONFIG
 428
 429 /* define to use L1 as initial stack */
 430 #define CONFIG_L1_INIT_RAM
 431 #define CONFIG_SYS_INIT_RAM_LOCK
 432 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 435 /* The assembler doesn't like typecast */
 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 437         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 438           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 439 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 440
 441 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 442                                         GENERATED_GBL_DATA_SIZE)
 443 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 444
 445 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 446 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 447
 448 /* Serial Port - controlled on board with jumper J8
 449  * open - index 2
 450  * shorted - index 1
 451  */
 452 #define CONFIG_SYS_NS16550_SERIAL
 453 #define CONFIG_SYS_NS16550_REG_SIZE     1
 454 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 455
 456 #define CONFIG_SYS_BAUDRATE_TABLE       \
 457         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 458
 459 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 460 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 461 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 462 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 463
 464 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 465 /* Video */
 466 #define CONFIG_FSL_DIU_FB
 467
 468 #ifdef CONFIG_FSL_DIU_FB
 469 #define CONFIG_FSL_DIU_CH7301
 470 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 471 #define CONFIG_VIDEO_LOGO
 472 #define CONFIG_VIDEO_BMP_LOGO
 473 #endif
 474 #endif
 475
 476 /* I2C */
 477 #define CONFIG_SYS_I2C
 478 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 479 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 480 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 481 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 482 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 483 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 484 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 485 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 486 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 487 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 488 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 489 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 490 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 491
 492 /* I2C bus multiplexer */
 493 #define I2C_MUX_PCA_ADDR                0x70
 494 #define I2C_MUX_CH_DEFAULT      0x8
 495
 496 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 497         defined(CONFIG_TARGET_T1040D4RDB)       || \
 498         defined(CONFIG_TARGET_T1042D4RDB)
 499 /* LDI/DVI Encoder for display */
 500 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 501 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 502
 503 /*
 504  * RTC configuration
 505  */
 506 #define RTC
 507 #define CONFIG_RTC_DS1337               1
 508 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 509
 510 /*DVI encoder*/
 511 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 512 #endif
 513
 514 /*
 515  * eSPI - Enhanced SPI
 516  */
 517
 518 /*
 519  * General PCI
 520  * Memory space is mapped 1-1, but I/O space must start from 0.
 521  */
 522
 523 #ifdef CONFIG_PCI
 524 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 525 #ifdef CONFIG_PCIE1
 526 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 527 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 528 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 529 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 530 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 531 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 532 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 533 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 534 #endif
 535
 536 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 537 #ifdef CONFIG_PCIE2
 538 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 539 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 540 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 541 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 542 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 543 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 544 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 545 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 546 #endif
 547
 548 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 549 #ifdef CONFIG_PCIE3
 550 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 551 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 552 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 553 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 554 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 555 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 556 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 557 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 558 #endif
 559
 560 /* controller 4, Base address 203000 */
 561 #ifdef CONFIG_PCIE4
 562 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 563 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 564 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 565 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 566 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 567 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 568 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 569 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 570 #endif
 571
 572 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 573 #endif  /* CONFIG_PCI */
 574
 575 /* SATA */
 576 #define CONFIG_FSL_SATA_V2
 577 #ifdef CONFIG_FSL_SATA_V2
 578 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 579 #define CONFIG_SATA1
 580 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 581 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 582
 583 #define CONFIG_LBA48
 584 #endif
 585
 586 /*
 587 * USB
 588 */
 589 #define CONFIG_HAS_FSL_DR_USB
 590
 591 #ifdef CONFIG_HAS_FSL_DR_USB
 592 #ifdef CONFIG_USB_EHCI_HCD
 593 #define CONFIG_USB_EHCI_FSL
 594 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 595 #endif
 596 #endif
 597
 598 #ifdef CONFIG_MMC
 599 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 600 #endif
 601
 602 /* Qman/Bman */
 603 #ifndef CONFIG_NOBQFMAN
 604 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 605 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 606 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 607 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 608 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 609 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 610 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 611 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 612 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 613                                         CONFIG_SYS_BMAN_CENA_SIZE)
 614 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 615 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 616 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 617 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 618 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 619 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 620 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 621 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 622 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 623 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 624 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 625                                         CONFIG_SYS_QMAN_CENA_SIZE)
 626 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 627 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 628
 629 #define CONFIG_SYS_DPAA_FMAN
 630 #define CONFIG_SYS_DPAA_PME
 631
 632 #define CONFIG_U_QE
 633
 634 /* Default address of microcode for the Linux Fman driver */
 635 #if defined(CONFIG_SPIFLASH)
 636 /*
 637  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 638  * env, so we got 0x110000.
 639  */
 640 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 641 #elif defined(CONFIG_SDCARD)
 642 /*
 643  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 644  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 645  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 646  */
 647 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 648 #elif defined(CONFIG_NAND)
 649 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 650 #else
 651 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 652 #endif
 653
 654 #if defined(CONFIG_SPIFLASH)
 655 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 656 #elif defined(CONFIG_SDCARD)
 657 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 658 #elif defined(CONFIG_NAND)
 659 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 660 #else
 661 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 662 #endif
 663
 664 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 665 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 666 #endif /* CONFIG_NOBQFMAN */
 667
 668 #ifdef CONFIG_SYS_DPAA_FMAN
 669 #define CONFIG_PHY_VITESSE
 670 #define CONFIG_PHY_REALTEK
 671 #endif
 672
 673 #ifdef CONFIG_FMAN_ENET
 674 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 675 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 676 #elif defined(CONFIG_TARGET_T1040D4RDB)
 677 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 678 #elif defined(CONFIG_TARGET_T1042D4RDB)
 679 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 680 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 681 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 682 #endif
 683
 684 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 685 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 686 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 687 #else
 688 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 689 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 690 #endif
 691
 692 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 693 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 694 #define CONFIG_VSC9953
 695 #ifdef CONFIG_TARGET_T1040RDB
 696 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 697 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 698 #else
 699 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 700 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 701 #endif
 702 #endif
 703
 704 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 705 #endif
 706
 707 /*
 708  * Environment
 709  */
 710 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 711 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 712
 713 /*
 714  * Miscellaneous configurable options
 715  */
 716 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 717
 718 /*
 719  * For booting Linux, the board info and command line data
 720  * have to be in the first 64 MB of memory, since this is
 721  * the maximum mapped by the Linux kernel during initialization.
 722  */
 723 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 724 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 725
 726 #ifdef CONFIG_CMD_KGDB
 727 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 728 #endif
 729
 730 /*
 731  * Dynamic MTD Partition support with mtdparts
 732  */
 733
 734 /*
 735  * Environment Configuration
 736  */
 737 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 738 #define CONFIG_BOOTFILE         "uImage"
 739 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 740
 741 /* default location for tftp and bootm */
 742 #define CONFIG_LOADADDR         1000000
 743
 744 #define __USB_PHY_TYPE  utmi
 745 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 746
 747 #ifdef CONFIG_TARGET_T1040RDB
 748 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 749 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 750 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 751 #elif defined(CONFIG_TARGET_T1042RDB)
 752 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 753 #elif defined(CONFIG_TARGET_T1040D4RDB)
 754 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 755 #elif defined(CONFIG_TARGET_T1042D4RDB)
 756 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 757 #endif
 758
 759 #ifdef CONFIG_FSL_DIU_FB
 760 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 761 #else
 762 #define DIU_ENVIRONMENT
 763 #endif
 764
 765 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 766         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 767         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 768         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 769         "netdev=eth0\0"                                         \
 770         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 771         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 772         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 773         "tftpflash=tftpboot $loadaddr $uboot && "               \
 774         "protect off $ubootaddr +$filesize && "                 \
 775         "erase $ubootaddr +$filesize && "                       \
 776         "cp.b $loadaddr $ubootaddr $filesize && "               \
 777         "protect on $ubootaddr +$filesize && "                  \
 778         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 779         "consoledev=ttyS0\0"                                    \
 780         "ramdiskaddr=2000000\0"                                 \
 781         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 782         "fdtaddr=1e00000\0"                                     \
 783         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 784         "bdev=sda3\0"
 785
 786 #define CONFIG_LINUX                       \
 787         "setenv bootargs root=/dev/ram rw "            \
 788         "console=$consoledev,$baudrate $othbootargs;"  \
 789         "setenv ramdiskaddr 0x02000000;"               \
 790         "setenv fdtaddr 0x00c00000;"                   \
 791         "setenv loadaddr 0x1000000;"                   \
 792         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 793
 794 #define CONFIG_HDBOOT                                   \
 795         "setenv bootargs root=/dev/$bdev rw "           \
 796         "console=$consoledev,$baudrate $othbootargs;"   \
 797         "tftp $loadaddr $bootfile;"                     \
 798         "tftp $fdtaddr $fdtfile;"                       \
 799         "bootm $loadaddr - $fdtaddr"
 800
 801 #define CONFIG_NFSBOOTCOMMAND                   \
 802         "setenv bootargs root=/dev/nfs rw "     \
 803         "nfsroot=$serverip:$rootpath "          \
 804         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 805         "console=$consoledev,$baudrate $othbootargs;"   \
 806         "tftp $loadaddr $bootfile;"             \
 807         "tftp $fdtaddr $fdtfile;"               \
 808         "bootm $loadaddr - $fdtaddr"
 809
 810 #define CONFIG_RAMBOOTCOMMAND                           \
 811         "setenv bootargs root=/dev/ram rw "             \
 812         "console=$consoledev,$baudrate $othbootargs;"   \
 813         "tftp $ramdiskaddr $ramdiskfile;"               \
 814         "tftp $loadaddr $bootfile;"                     \
 815         "tftp $fdtaddr $fdtfile;"                       \
 816         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 817
 818 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 819
 820 #include <asm/fsl_secure_boot.h>
 821
 822 #endif  /* __CONFIG_H */