1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SPL_PAD_TO 0x40000
19 #define CONFIG_SPL_MAX_SIZE 0x28000
20 #ifdef CONFIG_SPL_BUILD
21 #define CONFIG_SPL_COMMON_INIT_DDR
22 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
24 #define RESET_VECTOR_OFFSET 0x27FFC
25 #define BOOT_PAGE_OFFSET 0x27000
27 #ifdef CONFIG_MTD_RAW_NAND
28 #ifdef CONFIG_NXP_ESBC
29 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
31 * HDR would be appended at end of image and copied to DDR along
34 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
35 CONFIG_U_BOOT_HDR_SIZE)
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
41 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
46 #ifdef CONFIG_SPIFLASH
47 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48 #define CONFIG_SPL_SPI_FLASH_MINIMAL
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
53 #ifndef CONFIG_SPL_BUILD
54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
60 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
62 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
63 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
64 #ifndef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
71 /* High Level Configuration Options */
72 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
74 #ifndef CONFIG_RESET_VECTOR_ADDRESS
75 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
78 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
79 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
80 #define CONFIG_PCIE1 /* PCIE controller 1 */
81 #define CONFIG_PCIE2 /* PCIE controller 2 */
82 #define CONFIG_PCIE3 /* PCIE controller 3 */
83 #define CONFIG_PCIE4 /* PCIE controller 4 */
85 #if defined(CONFIG_SPIFLASH)
86 #elif defined(CONFIG_MTD_RAW_NAND)
87 #ifdef CONFIG_NXP_ESBC
88 #define CONFIG_RAMBOOT_NAND
89 #define CONFIG_BOOTSCRIPT_COPY_RAM
94 * These can be toggled for performance analysis, otherwise use default.
96 #define CONFIG_SYS_CACHE_STASHING
97 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
99 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
102 #define CONFIG_ENABLE_36BIT_PHYS
105 * Config the L3 Cache as L3 SRAM
107 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
109 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
110 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
111 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
113 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
114 #define CONFIG_SYS_L3_SIZE 256 << 10
115 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
116 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
117 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
118 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
119 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
121 #define CONFIG_SYS_DCSRBAR 0xf0000000
122 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
127 #define CONFIG_VERY_BIG_RAM
128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
131 #define CONFIG_SYS_SPD_BUS_NUM 0
132 #define SPD_EEPROM_ADDRESS 0x51
134 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
139 #define CONFIG_SYS_FLASH_BASE 0xe8000000
140 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
142 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
143 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
144 CSPR_PORT_SIZE_16 | \
147 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
152 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
154 /* NOR Flash Timing Params */
155 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
156 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
157 FTIM0_NOR_TEADC(0x5) | \
158 FTIM0_NOR_TEAHC(0x5))
159 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
160 FTIM1_NOR_TRAD_NOR(0x1A) |\
161 FTIM1_NOR_TSEQRAD_NOR(0x13))
162 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
163 FTIM2_NOR_TCH(0x4) | \
164 FTIM2_NOR_TWPH(0x0E) | \
166 #define CONFIG_SYS_NOR_FTIM3 0x0
168 #define CONFIG_SYS_FLASH_QUIET_TEST
169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
175 #define CONFIG_SYS_FLASH_EMPTY_INFO
176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
179 #define CPLD_LBMAP_MASK 0x3F
180 #define CPLD_BANK_SEL_MASK 0x07
181 #define CPLD_BANK_OVERRIDE 0x40
182 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
183 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
184 #define CPLD_LBMAP_RESET 0xFF
185 #define CPLD_LBMAP_SHIFT 0x03
187 #if defined(CONFIG_TARGET_T1042RDB_PI)
188 #define CPLD_DIU_SEL_DFP 0x80
189 #elif defined(CONFIG_TARGET_T1042D4RDB)
190 #define CPLD_DIU_SEL_DFP 0xc0
193 #if defined(CONFIG_TARGET_T1040D4RDB)
194 #define CPLD_INT_MASK_ALL 0xFF
195 #define CPLD_INT_MASK_THERM 0x80
196 #define CPLD_INT_MASK_DVI_DFP 0x40
197 #define CPLD_INT_MASK_QSGMII1 0x20
198 #define CPLD_INT_MASK_QSGMII2 0x10
199 #define CPLD_INT_MASK_SGMI1 0x08
200 #define CPLD_INT_MASK_SGMI2 0x04
201 #define CPLD_INT_MASK_TDMR1 0x02
202 #define CPLD_INT_MASK_TDMR2 0x01
205 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
206 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
207 #define CONFIG_SYS_CSPR2_EXT (0xf)
208 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
212 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
213 #define CONFIG_SYS_CSOR2 0x0
214 /* CPLD Timing parameters for IFC CS2 */
215 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
216 FTIM0_GPCM_TEADC(0x0e) | \
217 FTIM0_GPCM_TEAHC(0x0e))
218 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
219 FTIM1_GPCM_TRAD(0x1f))
220 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
221 FTIM2_GPCM_TCH(0x8) | \
222 FTIM2_GPCM_TWP(0x1f))
223 #define CONFIG_SYS_CS2_FTIM3 0x0
225 /* NAND Flash on IFC */
226 #define CONFIG_SYS_NAND_BASE 0xff800000
227 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
229 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
230 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
231 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
232 | CSPR_MSEL_NAND /* MSEL = NAND */ \
234 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
236 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
237 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
238 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
239 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
240 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
241 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
242 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
244 /* ONFI NAND Flash mode0 Timing Params */
245 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
246 FTIM0_NAND_TWP(0x18) | \
247 FTIM0_NAND_TWCHT(0x07) | \
248 FTIM0_NAND_TWH(0x0a))
249 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
250 FTIM1_NAND_TWBE(0x39) | \
251 FTIM1_NAND_TRR(0x0e) | \
252 FTIM1_NAND_TRP(0x18))
253 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
254 FTIM2_NAND_TREH(0x0a) | \
255 FTIM2_NAND_TWHRE(0x1e))
256 #define CONFIG_SYS_NAND_FTIM3 0x0
258 #define CONFIG_SYS_NAND_DDR_LAW 11
259 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
260 #define CONFIG_SYS_MAX_NAND_DEVICE 1
262 #if defined(CONFIG_MTD_RAW_NAND)
263 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
264 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
265 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
266 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
271 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
272 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
273 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
274 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
275 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
276 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
277 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
278 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
281 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
282 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
283 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
284 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
285 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
286 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
287 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
288 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
289 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
290 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
291 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
292 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
293 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
294 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
295 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
298 #if defined(CONFIG_RAMBOOT_PBL)
299 #define CONFIG_SYS_RAMBOOT
302 #define CONFIG_HWCONFIG
304 /* define to use L1 as initial stack */
305 #define CONFIG_L1_INIT_RAM
306 #define CONFIG_SYS_INIT_RAM_LOCK
307 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
310 /* The assembler doesn't like typecast */
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
312 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
313 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
320 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
322 /* Serial Port - controlled on board with jumper J8
326 #define CONFIG_SYS_NS16550_SERIAL
327 #define CONFIG_SYS_NS16550_REG_SIZE 1
328 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
330 #define CONFIG_SYS_BAUDRATE_TABLE \
331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
335 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
336 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
338 /* I2C bus multiplexer */
339 #define I2C_MUX_PCA_ADDR 0x70
340 #define I2C_MUX_CH_DEFAULT 0x8
342 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
343 defined(CONFIG_TARGET_T1040D4RDB) || \
344 defined(CONFIG_TARGET_T1042D4RDB)
345 /* LDI/DVI Encoder for display */
346 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
347 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
348 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
354 #define CONFIG_RTC_DS1337 1
355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
358 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
362 * eSPI - Enhanced SPI
367 * Memory space is mapped 1-1, but I/O space must start from 0.
371 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
373 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
374 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
375 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
379 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
381 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
382 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
383 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
384 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
387 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
389 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
390 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
391 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
392 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
395 /* controller 4, Base address 203000 */
397 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
398 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
399 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
400 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
403 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
404 #endif /* CONFIG_PCI */
407 #define CONFIG_FSL_SATA_V2
408 #ifdef CONFIG_FSL_SATA_V2
410 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
411 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
419 #define CONFIG_HAS_FSL_DR_USB
421 #ifdef CONFIG_HAS_FSL_DR_USB
422 #ifdef CONFIG_USB_EHCI_HCD
423 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
428 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
432 #ifndef CONFIG_NOBQFMAN
433 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
434 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
435 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
436 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
437 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
438 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
439 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
440 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
441 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
442 CONFIG_SYS_BMAN_CENA_SIZE)
443 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
444 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
445 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
446 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
447 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
448 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
449 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
450 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
451 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
452 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
453 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
454 CONFIG_SYS_QMAN_CENA_SIZE)
455 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
456 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
458 #define CONFIG_SYS_DPAA_FMAN
459 #define CONFIG_SYS_DPAA_PME
461 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
462 #endif /* CONFIG_NOBQFMAN */
464 #ifdef CONFIG_FMAN_ENET
465 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
466 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
467 #elif defined(CONFIG_TARGET_T1040D4RDB)
468 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
469 #elif defined(CONFIG_TARGET_T1042D4RDB)
470 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
471 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
472 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
475 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
476 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
477 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
479 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
480 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
483 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
484 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
485 #define CONFIG_VSC9953
486 #ifdef CONFIG_TARGET_T1040RDB
487 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
488 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
490 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
491 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
499 #define CONFIG_LOADS_ECHO /* echo on for serial download */
500 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
503 * Miscellaneous configurable options
507 * For booting Linux, the board info and command line data
508 * have to be in the first 64 MB of memory, since this is
509 * the maximum mapped by the Linux kernel during initialization.
511 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
512 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
515 * Dynamic MTD Partition support with mtdparts
519 * Environment Configuration
521 #define CONFIG_ROOTPATH "/opt/nfsroot"
522 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
524 #define __USB_PHY_TYPE utmi
525 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
527 #ifdef CONFIG_TARGET_T1040RDB
528 #define FDTFILE "t1040rdb/t1040rdb.dtb"
529 #elif defined(CONFIG_TARGET_T1042RDB_PI)
530 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
531 #elif defined(CONFIG_TARGET_T1042RDB)
532 #define FDTFILE "t1042rdb/t1042rdb.dtb"
533 #elif defined(CONFIG_TARGET_T1040D4RDB)
534 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
535 #elif defined(CONFIG_TARGET_T1042D4RDB)
536 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
539 #define CONFIG_EXTRA_ENV_SETTINGS \
540 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
541 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
542 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
544 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
545 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
546 "tftpflash=tftpboot $loadaddr $uboot && " \
547 "protect off $ubootaddr +$filesize && " \
548 "erase $ubootaddr +$filesize && " \
549 "cp.b $loadaddr $ubootaddr $filesize && " \
550 "protect on $ubootaddr +$filesize && " \
551 "cmp.b $loadaddr $ubootaddr $filesize\0" \
552 "consoledev=ttyS0\0" \
553 "ramdiskaddr=2000000\0" \
554 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
555 "fdtaddr=1e00000\0" \
556 "fdtfile=" __stringify(FDTFILE) "\0" \
559 #include <asm/fsl_secure_boot.h>
561 #endif /* __CONFIG_H */