include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #include <asm/config_mpc85xx.h>
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16
  17 #ifndef CONFIG_SECURE_BOOT
  18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  19 #else
  20 #define CONFIG_SYS_FSL_PBL_PBI \
  21                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  22 #endif
  23
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SYS_TEXT_BASE            0x30001000
  27 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #ifdef CONFIG_SPL_BUILD
  31 #define CONFIG_SPL_SKIP_RELOCATE
  32 #define CONFIG_SPL_COMMON_INIT_DDR
  33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  34 #endif
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37
  38 #ifdef CONFIG_NAND
  39 #ifdef CONFIG_SECURE_BOOT
  40 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  41 /*
  42  * HDR would be appended at end of image and copied to DDR along
  43  * with U-Boot image.
  44  */
  45 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  46                                          CONFIG_U_BOOT_HDR_SIZE)
  47 #else
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  49 #endif
  50 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  51 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  53 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  54 #ifdef CONFIG_TARGET_T1040RDB
  55 #define CONFIG_SYS_FSL_PBL_RCW \
  56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  57 #endif
  58 #ifdef CONFIG_TARGET_T1042RDB_PI
  59 #define CONFIG_SYS_FSL_PBL_RCW \
  60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  61 #endif
  62 #ifdef CONFIG_TARGET_T1042RDB
  63 #define CONFIG_SYS_FSL_PBL_RCW \
  64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  65 #endif
  66 #ifdef CONFIG_TARGET_T1040D4RDB
  67 #define CONFIG_SYS_FSL_PBL_RCW \
  68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  69 #endif
  70 #ifdef CONFIG_TARGET_T1042D4RDB
  71 #define CONFIG_SYS_FSL_PBL_RCW \
  72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  73 #endif
  74 #define CONFIG_SPL_NAND_BOOT
  75 #endif
  76
  77 #ifdef CONFIG_SPIFLASH
  78 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  79 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  84 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  85 #ifndef CONFIG_SPL_BUILD
  86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  87 #endif
  88 #ifdef CONFIG_TARGET_T1040RDB
  89 #define CONFIG_SYS_FSL_PBL_RCW \
  90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  91 #endif
  92 #ifdef CONFIG_TARGET_T1042RDB_PI
  93 #define CONFIG_SYS_FSL_PBL_RCW \
  94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  95 #endif
  96 #ifdef CONFIG_TARGET_T1042RDB
  97 #define CONFIG_SYS_FSL_PBL_RCW \
  98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  99 #endif
 100 #ifdef CONFIG_TARGET_T1040D4RDB
 101 #define CONFIG_SYS_FSL_PBL_RCW \
 102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 103 #endif
 104 #ifdef CONFIG_TARGET_T1042D4RDB
 105 #define CONFIG_SYS_FSL_PBL_RCW \
 106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 107 #endif
 108 #define CONFIG_SPL_SPI_BOOT
 109 #endif
 110
 111 #ifdef CONFIG_SDCARD
 112 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 113 #define CONFIG_SPL_MMC_MINIMAL
 114 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 115 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 116 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 117 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 118 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 119 #ifndef CONFIG_SPL_BUILD
 120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 121 #endif
 122 #ifdef CONFIG_TARGET_T1040RDB
 123 #define CONFIG_SYS_FSL_PBL_RCW \
 124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 125 #endif
 126 #ifdef CONFIG_TARGET_T1042RDB_PI
 127 #define CONFIG_SYS_FSL_PBL_RCW \
 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 129 #endif
 130 #ifdef CONFIG_TARGET_T1042RDB
 131 #define CONFIG_SYS_FSL_PBL_RCW \
 132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 133 #endif
 134 #ifdef CONFIG_TARGET_T1040D4RDB
 135 #define CONFIG_SYS_FSL_PBL_RCW \
 136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 137 #endif
 138 #ifdef CONFIG_TARGET_T1042D4RDB
 139 #define CONFIG_SYS_FSL_PBL_RCW \
 140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 141 #endif
 142 #define CONFIG_SPL_MMC_BOOT
 143 #endif
 144
 145 #endif
 146
 147 /* High Level Configuration Options */
 148 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 149 #define CONFIG_MP                       /* support multiple processors */
 150
 151 /* support deep sleep */
 152 #define CONFIG_DEEP_SLEEP
 153
 154 #ifndef CONFIG_SYS_TEXT_BASE
 155 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 156 #endif
 157
 158 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 159 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 160 #endif
 161
 162 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 163 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 164 #define CONFIG_PCI_INDIRECT_BRIDGE
 165 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 166 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 167 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 168 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 169
 170 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 171 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 172
 173 #define CONFIG_ENV_OVERWRITE
 174
 175 #ifdef CONFIG_MTD_NOR_FLASH
 176 #define CONFIG_FLASH_CFI_DRIVER
 177 #define CONFIG_SYS_FLASH_CFI
 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 179 #endif
 180
 181 #if defined(CONFIG_SPIFLASH)
 182 #define CONFIG_SYS_EXTRA_ENV_RELOC
 183 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 184 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 185 #define CONFIG_ENV_SECT_SIZE            0x10000
 186 #elif defined(CONFIG_SDCARD)
 187 #define CONFIG_SYS_EXTRA_ENV_RELOC
 188 #define CONFIG_SYS_MMC_ENV_DEV          0
 189 #define CONFIG_ENV_SIZE                 0x2000
 190 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 191 #elif defined(CONFIG_NAND)
 192 #ifdef CONFIG_SECURE_BOOT
 193 #define CONFIG_RAMBOOT_NAND
 194 #define CONFIG_BOOTSCRIPT_COPY_RAM
 195 #endif
 196 #define CONFIG_SYS_EXTRA_ENV_RELOC
 197 #define CONFIG_ENV_SIZE                 0x2000
 198 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 199 #else
 200 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 201 #define CONFIG_ENV_SIZE         0x2000
 202 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 203 #endif
 204
 205 #define CONFIG_SYS_CLK_FREQ     100000000
 206 #define CONFIG_DDR_CLK_FREQ     66666666
 207
 208 /*
 209  * These can be toggled for performance analysis, otherwise use default.
 210  */
 211 #define CONFIG_SYS_CACHE_STASHING
 212 #define CONFIG_BACKSIDE_L2_CACHE
 213 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 214 #define CONFIG_BTB                      /* toggle branch predition */
 215 #define CONFIG_DDR_ECC
 216 #ifdef CONFIG_DDR_ECC
 217 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 218 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 219 #endif
 220
 221 #define CONFIG_ENABLE_36BIT_PHYS
 222
 223 #define CONFIG_ADDR_MAP
 224 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 225
 226 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 227 #define CONFIG_SYS_MEMTEST_END          0x00400000
 228 #define CONFIG_SYS_ALT_MEMTEST
 229 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 230
 231 /*
 232  *  Config the L3 Cache as L3 SRAM
 233  */
 234 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 235 /*
 236  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 237  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 238  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 239  */
 240 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 241 #define CONFIG_SYS_L3_SIZE              256 << 10
 242 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 243 #ifdef CONFIG_RAMBOOT_PBL
 244 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 245 #endif
 246 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 247 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 248 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 249 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 250
 251 #define CONFIG_SYS_DCSRBAR              0xf0000000
 252 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 253
 254 /*
 255  * DDR Setup
 256  */
 257 #define CONFIG_VERY_BIG_RAM
 258 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 259 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 260
 261 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 262 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 263
 264 #define CONFIG_DDR_SPD
 265
 266 #define CONFIG_SYS_SPD_BUS_NUM  0
 267 #define SPD_EEPROM_ADDRESS      0x51
 268
 269 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 270
 271 /*
 272  * IFC Definitions
 273  */
 274 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 275 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 276
 277 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 278 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 279                                 CSPR_PORT_SIZE_16 | \
 280                                 CSPR_MSEL_NOR | \
 281                                 CSPR_V)
 282 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 283
 284 /*
 285  * TDM Definition
 286  */
 287 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 288
 289 /* NOR Flash Timing Params */
 290 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 291 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 292                                 FTIM0_NOR_TEADC(0x5) | \
 293                                 FTIM0_NOR_TEAHC(0x5))
 294 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 295                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 296                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 297 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 298                                 FTIM2_NOR_TCH(0x4) | \
 299                                 FTIM2_NOR_TWPH(0x0E) | \
 300                                 FTIM2_NOR_TWP(0x1c))
 301 #define CONFIG_SYS_NOR_FTIM3    0x0
 302
 303 #define CONFIG_SYS_FLASH_QUIET_TEST
 304 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 305
 306 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 307 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 308 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 309 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 310
 311 #define CONFIG_SYS_FLASH_EMPTY_INFO
 312 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 313
 314 /* CPLD on IFC */
 315 #define CPLD_LBMAP_MASK                 0x3F
 316 #define CPLD_BANK_SEL_MASK              0x07
 317 #define CPLD_BANK_OVERRIDE              0x40
 318 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 319 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 320 #define CPLD_LBMAP_RESET                0xFF
 321 #define CPLD_LBMAP_SHIFT                0x03
 322
 323 #if defined(CONFIG_TARGET_T1042RDB_PI)
 324 #define CPLD_DIU_SEL_DFP                0x80
 325 #elif defined(CONFIG_TARGET_T1042D4RDB)
 326 #define CPLD_DIU_SEL_DFP                0xc0
 327 #endif
 328
 329 #if defined(CONFIG_TARGET_T1040D4RDB)
 330 #define CPLD_INT_MASK_ALL               0xFF
 331 #define CPLD_INT_MASK_THERM             0x80
 332 #define CPLD_INT_MASK_DVI_DFP           0x40
 333 #define CPLD_INT_MASK_QSGMII1           0x20
 334 #define CPLD_INT_MASK_QSGMII2           0x10
 335 #define CPLD_INT_MASK_SGMI1             0x08
 336 #define CPLD_INT_MASK_SGMI2             0x04
 337 #define CPLD_INT_MASK_TDMR1             0x02
 338 #define CPLD_INT_MASK_TDMR2             0x01
 339 #endif
 340
 341 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 342 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 343 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 344 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 345                                 | CSPR_PORT_SIZE_8 \
 346                                 | CSPR_MSEL_GPCM \
 347                                 | CSPR_V)
 348 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 349 #define CONFIG_SYS_CSOR2        0x0
 350 /* CPLD Timing parameters for IFC CS2 */
 351 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 352                                         FTIM0_GPCM_TEADC(0x0e) | \
 353                                         FTIM0_GPCM_TEAHC(0x0e))
 354 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 355                                         FTIM1_GPCM_TRAD(0x1f))
 356 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 357                                         FTIM2_GPCM_TCH(0x8) | \
 358                                         FTIM2_GPCM_TWP(0x1f))
 359 #define CONFIG_SYS_CS2_FTIM3            0x0
 360
 361 /* NAND Flash on IFC */
 362 #define CONFIG_NAND_FSL_IFC
 363 #define CONFIG_SYS_NAND_BASE            0xff800000
 364 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 365
 366 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 367 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 368                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 369                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 370                                 | CSPR_V)
 371 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 372
 373 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 374                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 375                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 376                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 377                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 378                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 379                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 380
 381 #define CONFIG_SYS_NAND_ONFI_DETECTION
 382
 383 /* ONFI NAND Flash mode0 Timing Params */
 384 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 385                                         FTIM0_NAND_TWP(0x18)   | \
 386                                         FTIM0_NAND_TWCHT(0x07) | \
 387                                         FTIM0_NAND_TWH(0x0a))
 388 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 389                                         FTIM1_NAND_TWBE(0x39)  | \
 390                                         FTIM1_NAND_TRR(0x0e)   | \
 391                                         FTIM1_NAND_TRP(0x18))
 392 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 393                                         FTIM2_NAND_TREH(0x0a) | \
 394                                         FTIM2_NAND_TWHRE(0x1e))
 395 #define CONFIG_SYS_NAND_FTIM3           0x0
 396
 397 #define CONFIG_SYS_NAND_DDR_LAW         11
 398 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 399 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 400 #define CONFIG_CMD_NAND
 401
 402 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 403
 404 #if defined(CONFIG_NAND)
 405 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 406 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 407 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 408 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 409 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 410 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 411 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 412 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 413 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 414 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 415 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 416 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 417 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 418 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 419 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 420 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 421 #else
 422 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 423 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 424 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 425 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 426 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 427 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 428 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 429 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 430 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 431 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 432 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 433 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 434 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 435 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 436 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 437 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 438 #endif
 439
 440 #ifdef CONFIG_SPL_BUILD
 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 442 #else
 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 444 #endif
 445
 446 #if defined(CONFIG_RAMBOOT_PBL)
 447 #define CONFIG_SYS_RAMBOOT
 448 #endif
 449
 450 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 451 #if defined(CONFIG_NAND)
 452 #define CONFIG_A008044_WORKAROUND
 453 #endif
 454 #endif
 455
 456 #define CONFIG_BOARD_EARLY_INIT_R
 457 #define CONFIG_MISC_INIT_R
 458
 459 #define CONFIG_HWCONFIG
 460
 461 /* define to use L1 as initial stack */
 462 #define CONFIG_L1_INIT_RAM
 463 #define CONFIG_SYS_INIT_RAM_LOCK
 464 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 467 /* The assembler doesn't like typecast */
 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 469         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 470           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 471 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 472
 473 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 474                                         GENERATED_GBL_DATA_SIZE)
 475 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 476
 477 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 478 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 479
 480 /* Serial Port - controlled on board with jumper J8
 481  * open - index 2
 482  * shorted - index 1
 483  */
 484 #define CONFIG_CONS_INDEX       1
 485 #define CONFIG_SYS_NS16550_SERIAL
 486 #define CONFIG_SYS_NS16550_REG_SIZE     1
 487 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 488
 489 #define CONFIG_SYS_BAUDRATE_TABLE       \
 490         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 491
 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 494 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 495 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 496
 497 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 498 /* Video */
 499 #define CONFIG_FSL_DIU_FB
 500
 501 #ifdef CONFIG_FSL_DIU_FB
 502 #define CONFIG_FSL_DIU_CH7301
 503 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 504 #define CONFIG_VIDEO_LOGO
 505 #define CONFIG_VIDEO_BMP_LOGO
 506 #endif
 507 #endif
 508
 509 /* I2C */
 510 #define CONFIG_SYS_I2C
 511 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 512 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 513 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 514 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 515 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 516 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 517 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 518 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 519 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 520 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 521 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 522 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 523 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 524
 525 /* I2C bus multiplexer */
 526 #define I2C_MUX_PCA_ADDR                0x70
 527 #define I2C_MUX_CH_DEFAULT      0x8
 528
 529 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 530         defined(CONFIG_TARGET_T1040D4RDB)       || \
 531         defined(CONFIG_TARGET_T1042D4RDB)
 532 /* LDI/DVI Encoder for display */
 533 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 534 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 535
 536 /*
 537  * RTC configuration
 538  */
 539 #define RTC
 540 #define CONFIG_RTC_DS1337               1
 541 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 542
 543 /*DVI encoder*/
 544 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 545 #endif
 546
 547 /*
 548  * eSPI - Enhanced SPI
 549  */
 550 #define CONFIG_SPI_FLASH_BAR
 551 #define CONFIG_SF_DEFAULT_SPEED         10000000
 552 #define CONFIG_SF_DEFAULT_MODE          0
 553 #define CONFIG_ENV_SPI_BUS              0
 554 #define CONFIG_ENV_SPI_CS               0
 555 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 556 #define CONFIG_ENV_SPI_MODE             0
 557
 558 /*
 559  * General PCI
 560  * Memory space is mapped 1-1, but I/O space must start from 0.
 561  */
 562
 563 #ifdef CONFIG_PCI
 564 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 565 #ifdef CONFIG_PCIE1
 566 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 567 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 568 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 569 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 570 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 571 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 572 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 573 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 574 #endif
 575
 576 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 577 #ifdef CONFIG_PCIE2
 578 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 579 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 580 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 581 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 582 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 583 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 584 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 585 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 586 #endif
 587
 588 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 589 #ifdef CONFIG_PCIE3
 590 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 591 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 592 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 593 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 594 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 595 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 596 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 597 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 598 #endif
 599
 600 /* controller 4, Base address 203000 */
 601 #ifdef CONFIG_PCIE4
 602 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 603 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 604 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 605 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 606 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 607 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 608 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 609 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 610 #endif
 611
 612 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 613 #endif  /* CONFIG_PCI */
 614
 615 /* SATA */
 616 #define CONFIG_FSL_SATA_V2
 617 #ifdef CONFIG_FSL_SATA_V2
 618 #define CONFIG_LIBATA
 619 #define CONFIG_FSL_SATA
 620
 621 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 622 #define CONFIG_SATA1
 623 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 624 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 625
 626 #define CONFIG_LBA48
 627 #endif
 628
 629 /*
 630 * USB
 631 */
 632 #define CONFIG_HAS_FSL_DR_USB
 633
 634 #ifdef CONFIG_HAS_FSL_DR_USB
 635 #ifdef CONFIG_USB_EHCI_HCD
 636 #define CONFIG_USB_EHCI_FSL
 637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 638 #endif
 639 #endif
 640
 641 #ifdef CONFIG_MMC
 642 #define CONFIG_FSL_ESDHC
 643 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 644 #endif
 645
 646 /* Qman/Bman */
 647 #ifndef CONFIG_NOBQFMAN
 648 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 649 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 650 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 651 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 652 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 653 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 654 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 655 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 656 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 657 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 658                                         CONFIG_SYS_BMAN_CENA_SIZE)
 659 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 660 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 661 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 662 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 663 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 664 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 665 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 666 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 667 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 668 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 669 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 670                                         CONFIG_SYS_QMAN_CENA_SIZE)
 671 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 672 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 673
 674 #define CONFIG_SYS_DPAA_FMAN
 675 #define CONFIG_SYS_DPAA_PME
 676
 677 #define CONFIG_QE
 678 #define CONFIG_U_QE
 679
 680 /* Default address of microcode for the Linux Fman driver */
 681 #if defined(CONFIG_SPIFLASH)
 682 /*
 683  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 684  * env, so we got 0x110000.
 685  */
 686 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 687 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 688 #elif defined(CONFIG_SDCARD)
 689 /*
 690  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 691  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 692  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 693  */
 694 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 695 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 696 #elif defined(CONFIG_NAND)
 697 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 698 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 699 #else
 700 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 701 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 702 #endif
 703
 704 #if defined(CONFIG_SPIFLASH)
 705 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 706 #elif defined(CONFIG_SDCARD)
 707 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 708 #elif defined(CONFIG_NAND)
 709 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 710 #else
 711 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 712 #endif
 713
 714 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 715 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 716 #endif /* CONFIG_NOBQFMAN */
 717
 718 #ifdef CONFIG_SYS_DPAA_FMAN
 719 #define CONFIG_FMAN_ENET
 720 #define CONFIG_PHY_VITESSE
 721 #define CONFIG_PHY_REALTEK
 722 #endif
 723
 724 #ifdef CONFIG_FMAN_ENET
 725 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 726 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 727 #elif defined(CONFIG_TARGET_T1040D4RDB)
 728 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 729 #elif defined(CONFIG_TARGET_T1042D4RDB)
 730 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 731 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 732 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 733 #endif
 734
 735 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 736 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 737 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 738 #else
 739 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 740 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 741 #endif
 742
 743 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 744 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 745 #define CONFIG_VSC9953
 746 #ifdef CONFIG_TARGET_T1040RDB
 747 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 748 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 749 #else
 750 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 751 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 752 #endif
 753 #endif
 754
 755 #define CONFIG_MII              /* MII PHY management */
 756 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 757 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 758 #endif
 759
 760 /*
 761  * Environment
 762  */
 763 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 764 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 765
 766 /*
 767  * Command line configuration.
 768  */
 769 #define CONFIG_CMD_REGINFO
 770
 771 #ifdef CONFIG_PCI
 772 #define CONFIG_CMD_PCI
 773 #endif
 774
 775 /*
 776  * Miscellaneous configurable options
 777  */
 778 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 779 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 780 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 781 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 782 #ifdef CONFIG_CMD_KGDB
 783 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 784 #else
 785 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 786 #endif
 787 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 788 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 789 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 790
 791 /*
 792  * For booting Linux, the board info and command line data
 793  * have to be in the first 64 MB of memory, since this is
 794  * the maximum mapped by the Linux kernel during initialization.
 795  */
 796 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 797 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 798
 799 #ifdef CONFIG_CMD_KGDB
 800 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 801 #endif
 802
 803 /*
 804  * Dynamic MTD Partition support with mtdparts
 805  */
 806 #ifdef CONFIG_MTD_NOR_FLASH
 807 #define CONFIG_MTD_DEVICE
 808 #define CONFIG_MTD_PARTITIONS
 809 #define CONFIG_FLASH_CFI_MTD
 810 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 811                         "spi0=spife110000.0"
 812 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 813                                 "128k(dtb),96m(fs),-(user);"\
 814                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 815                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 816                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 817 #endif
 818
 819 /*
 820  * Environment Configuration
 821  */
 822 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 823 #define CONFIG_BOOTFILE         "uImage"
 824 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 825
 826 /* default location for tftp and bootm */
 827 #define CONFIG_LOADADDR         1000000
 828
 829 #define __USB_PHY_TYPE  utmi
 830 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 831
 832 #ifdef CONFIG_TARGET_T1040RDB
 833 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 834 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 835 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 836 #elif defined(CONFIG_TARGET_T1042RDB)
 837 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 838 #elif defined(CONFIG_TARGET_T1040D4RDB)
 839 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 840 #elif defined(CONFIG_TARGET_T1042D4RDB)
 841 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 842 #endif
 843
 844 #ifdef CONFIG_FSL_DIU_FB
 845 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 846 #else
 847 #define DIU_ENVIRONMENT
 848 #endif
 849
 850 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 851         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 852         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 853         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 854         "netdev=eth0\0"                                         \
 855         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 856         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 857         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 858         "tftpflash=tftpboot $loadaddr $uboot && "               \
 859         "protect off $ubootaddr +$filesize && "                 \
 860         "erase $ubootaddr +$filesize && "                       \
 861         "cp.b $loadaddr $ubootaddr $filesize && "               \
 862         "protect on $ubootaddr +$filesize && "                  \
 863         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 864         "consoledev=ttyS0\0"                                    \
 865         "ramdiskaddr=2000000\0"                                 \
 866         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 867         "fdtaddr=1e00000\0"                                     \
 868         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 869         "bdev=sda3\0"
 870
 871 #define CONFIG_LINUX                       \
 872         "setenv bootargs root=/dev/ram rw "            \
 873         "console=$consoledev,$baudrate $othbootargs;"  \
 874         "setenv ramdiskaddr 0x02000000;"               \
 875         "setenv fdtaddr 0x00c00000;"                   \
 876         "setenv loadaddr 0x1000000;"                   \
 877         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 878
 879 #define CONFIG_HDBOOT                                   \
 880         "setenv bootargs root=/dev/$bdev rw "           \
 881         "console=$consoledev,$baudrate $othbootargs;"   \
 882         "tftp $loadaddr $bootfile;"                     \
 883         "tftp $fdtaddr $fdtfile;"                       \
 884         "bootm $loadaddr - $fdtaddr"
 885
 886 #define CONFIG_NFSBOOTCOMMAND                   \
 887         "setenv bootargs root=/dev/nfs rw "     \
 888         "nfsroot=$serverip:$rootpath "          \
 889         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 890         "console=$consoledev,$baudrate $othbootargs;"   \
 891         "tftp $loadaddr $bootfile;"             \
 892         "tftp $fdtaddr $fdtfile;"               \
 893         "bootm $loadaddr - $fdtaddr"
 894
 895 #define CONFIG_RAMBOOTCOMMAND                           \
 896         "setenv bootargs root=/dev/ram rw "             \
 897         "console=$consoledev,$baudrate $othbootargs;"   \
 898         "tftp $ramdiskaddr $ramdiskfile;"               \
 899         "tftp $loadaddr $bootfile;"                     \
 900         "tftp $fdtaddr $fdtfile;"                       \
 901         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 902
 903 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 904
 905 #include <asm/fsl_secure_boot.h>
 906
 907 #endif  /* __CONFIG_H */