include/configs/T1040QDS.h

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2020 NXP
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #include <linux/stringify.h>
  28
  29 /*
  30  * T1040 QDS board configuration file
  31  */
  32
  33 #ifdef CONFIG_RAMBOOT_PBL
  34 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  38 #endif
  39
  40 /* High Level Configuration Options */
  41 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  42
  43 /* support deep sleep */
  44 #define CONFIG_DEEP_SLEEP
  45
  46 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  47 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  48 #endif
  49
  50 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  51 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  52 #define CONFIG_PCI_INDIRECT_BRIDGE
  53 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  54 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  55 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  56 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  57
  58 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  59 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  60
  61 #define CONFIG_ENV_OVERWRITE
  62
  63 #ifdef CONFIG_MTD_NOR_FLASH
  64 #if defined(CONFIG_SPIFLASH)
  65 #elif defined(CONFIG_SDCARD)
  66 #define CONFIG_SYS_MMC_ENV_DEV          0
  67 #endif
  68 #endif
  69
  70 #ifndef __ASSEMBLY__
  71 unsigned long get_board_sys_clk(void);
  72 unsigned long get_board_ddr_clk(void);
  73 #endif
  74
  75 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  76 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  77
  78 /*
  79  * These can be toggled for performance analysis, otherwise use default.
  80  */
  81 #define CONFIG_SYS_CACHE_STASHING
  82 #define CONFIG_BACKSIDE_L2_CACHE
  83 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  84 #define CONFIG_BTB                      /* toggle branch predition */
  85 #define CONFIG_DDR_ECC
  86 #ifdef CONFIG_DDR_ECC
  87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  88 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  89 #endif
  90
  91 #define CONFIG_ENABLE_36BIT_PHYS
  92
  93 #define CONFIG_ADDR_MAP
  94 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  95
  96 /*
  97  *  Config the L3 Cache as L3 SRAM
  98  */
  99 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 100
 101 #define CONFIG_SYS_DCSRBAR              0xf0000000
 102 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 103
 104 /* EEPROM */
 105 #define CONFIG_ID_EEPROM
 106 #define CONFIG_SYS_I2C_EEPROM_NXID
 107 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 108 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 112
 113 /*
 114  * DDR Setup
 115  */
 116 #define CONFIG_VERY_BIG_RAM
 117 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 118 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 119
 120 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 121 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 122
 123 #define CONFIG_DDR_SPD
 124
 125 #define CONFIG_SYS_SPD_BUS_NUM  0
 126 #define SPD_EEPROM_ADDRESS      0x51
 127
 128 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 129
 130 /*
 131  * IFC Definitions
 132  */
 133 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 134 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 135
 136 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 137 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 138                                 + 0x8000000) | \
 139                                 CSPR_PORT_SIZE_16 | \
 140                                 CSPR_MSEL_NOR | \
 141                                 CSPR_V)
 142 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 143 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 144                                 CSPR_PORT_SIZE_16 | \
 145                                 CSPR_MSEL_NOR | \
 146                                 CSPR_V)
 147 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 148
 149 /*
 150  * TDM Definition
 151  */
 152 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 153
 154 /* NOR Flash Timing Params */
 155 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 156 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 157                                 FTIM0_NOR_TEADC(0x5) | \
 158                                 FTIM0_NOR_TEAHC(0x5))
 159 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 160                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 161                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 162 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 163                                 FTIM2_NOR_TCH(0x4) | \
 164                                 FTIM2_NOR_TWPH(0x0E) | \
 165                                 FTIM2_NOR_TWP(0x1c))
 166 #define CONFIG_SYS_NOR_FTIM3    0x0
 167
 168 #define CONFIG_SYS_FLASH_QUIET_TEST
 169 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 170
 171 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 172 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 173 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 174 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 175
 176 #define CONFIG_SYS_FLASH_EMPTY_INFO
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 178                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 179 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 180 #define QIXIS_BASE              0xffdf0000
 181 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 182 #define QIXIS_LBMAP_SWITCH              0x06
 183 #define QIXIS_LBMAP_MASK                0x0f
 184 #define QIXIS_LBMAP_SHIFT               0
 185 #define QIXIS_LBMAP_DFLTBANK            0x00
 186 #define QIXIS_LBMAP_ALTBANK             0x04
 187 #define QIXIS_RST_CTL_RESET             0x31
 188 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 189 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 190 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 191 #define QIXIS_RST_FORCE_MEM             0x01
 192
 193 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 194 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 195                                 | CSPR_PORT_SIZE_8 \
 196                                 | CSPR_MSEL_GPCM \
 197                                 | CSPR_V)
 198 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 199 #define CONFIG_SYS_CSOR3        0x0
 200 /* QIXIS Timing parameters for IFC CS3 */
 201 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 202                                         FTIM0_GPCM_TEADC(0x0e) | \
 203                                         FTIM0_GPCM_TEAHC(0x0e))
 204 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 205                                         FTIM1_GPCM_TRAD(0x3f))
 206 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 207                                         FTIM2_GPCM_TCH(0x8) | \
 208                                         FTIM2_GPCM_TWP(0x1f))
 209 #define CONFIG_SYS_CS3_FTIM3            0x0
 210
 211 #define CONFIG_NAND_FSL_IFC
 212 #define CONFIG_SYS_NAND_BASE            0xff800000
 213 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 214
 215 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 216 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 217                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 218                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 219                                 | CSPR_V)
 220 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 221
 222 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 223                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 224                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 225                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 226                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 227                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 228                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 229
 230 #define CONFIG_SYS_NAND_ONFI_DETECTION
 231
 232 /* ONFI NAND Flash mode0 Timing Params */
 233 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 234                                         FTIM0_NAND_TWP(0x18)   | \
 235                                         FTIM0_NAND_TWCHT(0x07) | \
 236                                         FTIM0_NAND_TWH(0x0a))
 237 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 238                                         FTIM1_NAND_TWBE(0x39)  | \
 239                                         FTIM1_NAND_TRR(0x0e)   | \
 240                                         FTIM1_NAND_TRP(0x18))
 241 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 242                                         FTIM2_NAND_TREH(0x0a) | \
 243                                         FTIM2_NAND_TWHRE(0x1e))
 244 #define CONFIG_SYS_NAND_FTIM3           0x0
 245
 246 #define CONFIG_SYS_NAND_DDR_LAW         11
 247 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 248 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 249
 250 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 251
 252 #if defined(CONFIG_MTD_RAW_NAND)
 253 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 255 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 256 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 257 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 258 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 259 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 260 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 261 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 262 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 263 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 264 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 265 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 266 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 267 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 268 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 269 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 270 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 271 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #else
 278 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 279 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 280 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 281 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 282 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 283 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 284 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 285 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 286 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 287 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 288 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 289 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 290 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 291 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 292 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 293 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 294 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 295 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 296 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 297 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 298 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 299 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 300 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 301 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 302 #endif
 303
 304 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 305
 306 #if defined(CONFIG_RAMBOOT_PBL)
 307 #define CONFIG_SYS_RAMBOOT
 308 #endif
 309
 310 #define CONFIG_HWCONFIG
 311
 312 /* define to use L1 as initial stack */
 313 #define CONFIG_L1_INIT_RAM
 314 #define CONFIG_SYS_INIT_RAM_LOCK
 315 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 318 /* The assembler doesn't like typecast */
 319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 320         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 321           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 322 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 323
 324 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 325                                         GENERATED_GBL_DATA_SIZE)
 326 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 327
 328 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 329 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 330
 331 /* Serial Port - controlled on board with jumper J8
 332  * open - index 2
 333  * shorted - index 1
 334  */
 335 #define CONFIG_SYS_NS16550_SERIAL
 336 #define CONFIG_SYS_NS16550_REG_SIZE     1
 337 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 338
 339 #define CONFIG_SYS_BAUDRATE_TABLE       \
 340         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 341
 342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 344 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 345 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 346
 347 /* Video */
 348 #define CONFIG_FSL_DIU_FB
 349 #ifdef CONFIG_FSL_DIU_FB
 350 #define CONFIG_FSL_DIU_CH7301
 351 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 352 #define CONFIG_VIDEO_LOGO
 353 #define CONFIG_VIDEO_BMP_LOGO
 354 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 355 /*
 356  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 357  * disable empty flash sector detection, which is I/O-intensive.
 358  */
 359 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 360 #endif
 361
 362 /* I2C */
 363
 364 #ifndef CONFIG_DM_I2C
 365 #define CONFIG_SYS_I2C
 366 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 367 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 368 #define CONFIG_SYS_FSL_I2C2_SPEED       50000
 369 #define CONFIG_SYS_FSL_I2C3_SPEED       50000
 370 #define CONFIG_SYS_FSL_I2C4_SPEED       50000
 371 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 372 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 373 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 374 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 375 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 376 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 377 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 378 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 379 #endif
 380
 381 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 382
 383 #define I2C_MUX_PCA_ADDR                0x77
 384 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 385
 386 /* I2C bus multiplexer */
 387 #define I2C_MUX_CH_DEFAULT      0x8
 388 #define I2C_MUX_CH_DIU          0xC
 389
 390 /* LDI/DVI Encoder for display */
 391 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 392 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 393 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 394
 395 /*
 396  * RTC configuration
 397  */
 398 #define RTC
 399 #define CONFIG_RTC_DS3231               1
 400 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 401
 402 /*
 403  * eSPI - Enhanced SPI
 404  */
 405
 406 /*
 407  * General PCI
 408  * Memory space is mapped 1-1, but I/O space must start from 0.
 409  */
 410
 411 #ifdef CONFIG_PCI
 412 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 413 #ifdef CONFIG_PCIE1
 414 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 415 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 416 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 417 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 418 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 419 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 420 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 421 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 422 #endif
 423
 424 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 425 #ifdef CONFIG_PCIE2
 426 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 427 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 428 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 429 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 430 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 431 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 432 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 433 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 434 #endif
 435
 436 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 437 #ifdef CONFIG_PCIE3
 438 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 439 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 440 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 441 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 442 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 443 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 444 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 445 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 446 #endif
 447
 448 /* controller 4, Base address 203000 */
 449 #ifdef CONFIG_PCIE4
 450 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 451 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 452 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 453 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 454 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 455 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 456 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 457 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 458 #endif
 459
 460 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 461 #endif  /* CONFIG_PCI */
 462
 463 /* SATA */
 464 #define CONFIG_FSL_SATA_V2
 465 #ifdef CONFIG_FSL_SATA_V2
 466 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 467 #define CONFIG_SATA1
 468 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 469 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 470 #define CONFIG_SATA2
 471 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 472 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 473
 474 #define CONFIG_LBA48
 475 #endif
 476
 477 /*
 478 * USB
 479 */
 480 #define CONFIG_HAS_FSL_DR_USB
 481
 482 #ifdef CONFIG_HAS_FSL_DR_USB
 483 #ifdef CONFIG_USB_EHCI_HCD
 484 #define CONFIG_USB_EHCI_FSL
 485 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 486 #endif
 487 #endif
 488
 489 #ifdef CONFIG_MMC
 490 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 491 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 492 #endif
 493
 494 /* Qman/Bman */
 495 #ifndef CONFIG_NOBQFMAN
 496 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 497 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 498 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 499 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 500 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 501 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 502 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 503 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 504 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 505                                         CONFIG_SYS_BMAN_CENA_SIZE)
 506 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 507 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 508 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 509 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 510 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 511 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 512 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 513 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 514 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 515 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 516 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 517                                         CONFIG_SYS_QMAN_CENA_SIZE)
 518 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 519 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 520
 521 #define CONFIG_SYS_DPAA_FMAN
 522 #define CONFIG_SYS_DPAA_PME
 523
 524 /* Default address of microcode for the Linux Fman driver */
 525 #if defined(CONFIG_SPIFLASH)
 526 /*
 527  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 528  * env, so we got 0x110000.
 529  */
 530 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 531 #elif defined(CONFIG_SDCARD)
 532 /*
 533  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 534  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 535  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 536  */
 537 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 538 #elif defined(CONFIG_MTD_RAW_NAND)
 539 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 540 #else
 541 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 542 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 543 #endif
 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 545 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 546 #endif /* CONFIG_NOBQFMAN */
 547
 548 #ifdef CONFIG_SYS_DPAA_FMAN
 549 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 550 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 551 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 552 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 553 #endif
 554
 555 #ifdef CONFIG_FMAN_ENET
 556 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
 557 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
 558
 559 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 560 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 561 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 562 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 563
 564 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 565 #endif
 566
 567 /* Enable VSC9953 L2 Switch driver */
 568 #define CONFIG_VSC9953
 569 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x14
 570 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x18
 571
 572 /*
 573  * Dynamic MTD Partition support with mtdparts
 574  */
 575
 576 /*
 577  * Environment
 578  */
 579 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 580 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 581
 582 /*
 583  * Miscellaneous configurable options
 584  */
 585 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 586
 587 /*
 588  * For booting Linux, the board info and command line data
 589  * have to be in the first 64 MB of memory, since this is
 590  * the maximum mapped by the Linux kernel during initialization.
 591  */
 592 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 593 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 594
 595 #ifdef CONFIG_CMD_KGDB
 596 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 597 #endif
 598
 599 /*
 600  * Environment Configuration
 601  */
 602 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 603 #define CONFIG_BOOTFILE         "uImage"
 604 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 605
 606 /* default location for tftp and bootm */
 607 #define CONFIG_LOADADDR         1000000
 608
 609 #define __USB_PHY_TYPE  utmi
 610
 611 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 612         "hwconfig=fsl_ddr:bank_intlv=auto;"                     \
 613         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 614         "netdev=eth0\0"                                         \
 615         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 616         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 617         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 618         "tftpflash=tftpboot $loadaddr $uboot && "               \
 619         "protect off $ubootaddr +$filesize && "                 \
 620         "erase $ubootaddr +$filesize && "                       \
 621         "cp.b $loadaddr $ubootaddr $filesize && "               \
 622         "protect on $ubootaddr +$filesize && "                  \
 623         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 624         "consoledev=ttyS0\0"                                    \
 625         "ramdiskaddr=2000000\0"                                 \
 626         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
 627         "fdtaddr=1e00000\0"                                     \
 628         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
 629         "bdev=sda3\0"
 630
 631 #define CONFIG_LINUX                       \
 632         "setenv bootargs root=/dev/ram rw "            \
 633         "console=$consoledev,$baudrate $othbootargs;"  \
 634         "setenv ramdiskaddr 0x02000000;"               \
 635         "setenv fdtaddr 0x00c00000;"                   \
 636         "setenv loadaddr 0x1000000;"                   \
 637         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 638
 639 #define CONFIG_HDBOOT                                   \
 640         "setenv bootargs root=/dev/$bdev rw "           \
 641         "console=$consoledev,$baudrate $othbootargs;"   \
 642         "tftp $loadaddr $bootfile;"                     \
 643         "tftp $fdtaddr $fdtfile;"                       \
 644         "bootm $loadaddr - $fdtaddr"
 645
 646 #define CONFIG_NFSBOOTCOMMAND                   \
 647         "setenv bootargs root=/dev/nfs rw "     \
 648         "nfsroot=$serverip:$rootpath "          \
 649         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 650         "console=$consoledev,$baudrate $othbootargs;"   \
 651         "tftp $loadaddr $bootfile;"             \
 652         "tftp $fdtaddr $fdtfile;"               \
 653         "bootm $loadaddr - $fdtaddr"
 654
 655 #define CONFIG_RAMBOOTCOMMAND                           \
 656         "setenv bootargs root=/dev/ram rw "             \
 657         "console=$consoledev,$baudrate $othbootargs;"   \
 658         "tftp $ramdiskaddr $ramdiskfile;"               \
 659         "tftp $loadaddr $bootfile;"                     \
 660         "tftp $fdtaddr $fdtfile;"                       \
 661         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 662
 663 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 664
 665 #include <asm/fsl_secure_boot.h>
 666
 667 #endif  /* __CONFIG_H */