include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 #ifdef CONFIG_RAMBOOT_PBL
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26 #ifdef CONFIG_SPL_BUILD
  27 #define CONFIG_SPL_COMMON_INIT_DDR
  28 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  29 #endif
  30
  31 #ifdef CONFIG_MTD_RAW_NAND
  32 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  35 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_SPIFLASH
  41 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  42 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  47 #ifndef CONFIG_SPL_BUILD
  48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  49 #endif
  50 #endif
  51
  52 #ifdef CONFIG_SDCARD
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  54 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  55 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  56 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  57 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  58 #ifndef CONFIG_SPL_BUILD
  59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60 #endif
  61 #endif
  62
  63 #endif /* CONFIG_RAMBOOT_PBL */
  64
  65 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  66 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  67 #endif
  68
  69 /* PCIe Boot - Master */
  70 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  71 /*
  72  * for slave u-boot IMAGE instored in master memory space,
  73  * PHYS must be aligned based on the SIZE
  74  */
  75 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  76 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  77 #ifdef CONFIG_PHYS_64BIT
  78 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  79 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  80 #else
  81 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  83 #endif
  84 /*
  85  * for slave UCODE and ENV instored in master memory space,
  86  * PHYS must be aligned based on the SIZE
  87  */
  88 #ifdef CONFIG_PHYS_64BIT
  89 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  90 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  91 #else
  92 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  93 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
  94 #endif
  95 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
  96 /* slave core release by master*/
  97 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
  98 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
  99
 100 /* PCIe Boot - Slave */
 101 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 102 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 103 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 104                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 105 /* Set 1M boot space for PCIe boot */
 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 108                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 110 #endif
 111
 112 /*
 113  * These can be toggled for performance analysis, otherwise use default.
 114  */
 115 #define CONFIG_SYS_CACHE_STASHING
 116 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 117 #ifdef CONFIG_DDR_ECC
 118 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 119 #endif
 120
 121 /*
 122  *  Config the L3 Cache as L3 SRAM
 123  */
 124 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 125 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 126 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 127 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 128 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 129 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 130 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 131
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SYS_DCSRBAR              0xf0000000
 134 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 135 #endif
 136
 137 /* EEPROM */
 138 #define CONFIG_SYS_I2C_EEPROM_NXID
 139 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 140
 141 /*
 142  * DDR Setup
 143  */
 144 #define CONFIG_VERY_BIG_RAM
 145 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 146 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 147 #if defined(CONFIG_TARGET_T1024RDB)
 148 #define CONFIG_SYS_SPD_BUS_NUM  0
 149 #define SPD_EEPROM_ADDRESS      0x51
 150 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 151 #elif defined(CONFIG_TARGET_T1023RDB)
 152 #define CONFIG_SYS_DDR_RAW_TIMING
 153 #define CONFIG_SYS_SDRAM_SIZE   2048
 154 #endif
 155
 156 /*
 157  * IFC Definitions
 158  */
 159 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 160 #ifdef CONFIG_PHYS_64BIT
 161 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 162 #else
 163 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 164 #endif
 165
 166 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 167 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 168                                 CSPR_PORT_SIZE_16 | \
 169                                 CSPR_MSEL_NOR | \
 170                                 CSPR_V)
 171 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 172
 173 /* NOR Flash Timing Params */
 174 #if defined(CONFIG_TARGET_T1024RDB)
 175 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 176 #elif defined(CONFIG_TARGET_T1023RDB)
 177 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 178                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 179 #endif
 180 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 181                                 FTIM0_NOR_TEADC(0x5) | \
 182                                 FTIM0_NOR_TEAHC(0x5))
 183 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 184                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 185                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 186 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 187                                 FTIM2_NOR_TCH(0x4) | \
 188                                 FTIM2_NOR_TWPH(0x0E) | \
 189                                 FTIM2_NOR_TWP(0x1c))
 190 #define CONFIG_SYS_NOR_FTIM3    0x0
 191
 192 #define CONFIG_SYS_FLASH_QUIET_TEST
 193 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 194
 195 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 198
 199 #define CONFIG_SYS_FLASH_EMPTY_INFO
 200 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 201
 202 #ifdef CONFIG_TARGET_T1024RDB
 203 /* CPLD on IFC */
 204 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 205 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 206 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 207 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 208                                                 | CSPR_PORT_SIZE_8 \
 209                                                 | CSPR_MSEL_GPCM \
 210                                                 | CSPR_V)
 211 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 212 #define CONFIG_SYS_CSOR2                0x0
 213
 214 /* CPLD Timing parameters for IFC CS2 */
 215 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 216                                                 FTIM0_GPCM_TEADC(0x0e) | \
 217                                                 FTIM0_GPCM_TEAHC(0x0e))
 218 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 219                                                 FTIM1_GPCM_TRAD(0x1f))
 220 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 221                                                 FTIM2_GPCM_TCH(0x8) | \
 222                                                 FTIM2_GPCM_TWP(0x1f))
 223 #define CONFIG_SYS_CS2_FTIM3            0x0
 224 #endif
 225
 226 /* NAND Flash on IFC */
 227 #define CONFIG_SYS_NAND_BASE            0xff800000
 228 #ifdef CONFIG_PHYS_64BIT
 229 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 230 #else
 231 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 232 #endif
 233 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 234 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 235                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 236                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 237                                 | CSPR_V)
 238 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 239
 240 #if defined(CONFIG_TARGET_T1024RDB)
 241 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 242                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 243                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 244                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 245                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 246                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 247                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 248 #elif defined(CONFIG_TARGET_T1023RDB)
 249 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 250                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 251                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 252                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 253                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 254                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 255                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 256 #endif
 257
 258 /* ONFI NAND Flash mode0 Timing Params */
 259 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 260                                         FTIM0_NAND_TWP(0x18)   | \
 261                                         FTIM0_NAND_TWCHT(0x07) | \
 262                                         FTIM0_NAND_TWH(0x0a))
 263 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 264                                         FTIM1_NAND_TWBE(0x39)  | \
 265                                         FTIM1_NAND_TRR(0x0e)   | \
 266                                         FTIM1_NAND_TRP(0x18))
 267 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 268                                         FTIM2_NAND_TREH(0x0a) | \
 269                                         FTIM2_NAND_TWHRE(0x1e))
 270 #define CONFIG_SYS_NAND_FTIM3           0x0
 271
 272 #define CONFIG_SYS_NAND_DDR_LAW         11
 273 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 274 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 275
 276 #if defined(CONFIG_MTD_RAW_NAND)
 277 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 278 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 279 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 280 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 281 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 282 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 283 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 284 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 285 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 286 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 287 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 288 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 289 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 290 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 291 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 292 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 293 #else
 294 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 295 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 296 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 297 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 298 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 299 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 300 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 301 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 302 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 303 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 304 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 305 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 306 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 307 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 308 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 309 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 310 #endif
 311
 312 #if defined(CONFIG_RAMBOOT_PBL)
 313 #define CONFIG_SYS_RAMBOOT
 314 #endif
 315
 316 #define CONFIG_HWCONFIG
 317
 318 /* define to use L1 as initial stack */
 319 #define CONFIG_L1_INIT_RAM
 320 #define CONFIG_SYS_INIT_RAM_LOCK
 321 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 322 #ifdef CONFIG_PHYS_64BIT
 323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 325 /* The assembler doesn't like typecast */
 326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 327         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 328           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 329 #else
 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 333 #endif
 334 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 335
 336 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 337                                         GENERATED_GBL_DATA_SIZE)
 338 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 339
 340 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 341
 342 /* Serial Port */
 343 #define CONFIG_SYS_NS16550_SERIAL
 344 #define CONFIG_SYS_NS16550_REG_SIZE     1
 345 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 346
 347 #define CONFIG_SYS_BAUDRATE_TABLE       \
 348         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 349
 350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 352 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 353 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 354
 355 /* I2C */
 356
 357 #define I2C_PCA6408_BUS_NUM             1
 358 #define I2C_PCA6408_ADDR                0x20
 359
 360 /* I2C bus multiplexer */
 361 #define I2C_MUX_CH_DEFAULT      0x8
 362
 363 /*
 364  * RTC configuration
 365  */
 366 #define RTC
 367 #define CONFIG_RTC_DS1337       1
 368 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 369
 370 /*
 371  * eSPI - Enhanced SPI
 372  */
 373
 374 /*
 375  * General PCIe
 376  * Memory space is mapped 1-1, but I/O space must start from 0.
 377  */
 378 #define CONFIG_PCIE1            /* PCIE controller 1 */
 379 #define CONFIG_PCIE2            /* PCIE controller 2 */
 380 #define CONFIG_PCIE3            /* PCIE controller 3 */
 381
 382 #ifdef CONFIG_PCI
 383 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 384 #ifdef CONFIG_PCIE1
 385 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 386 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 387 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 388 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 389 #endif
 390
 391 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 392 #ifdef CONFIG_PCIE2
 393 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 394 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 395 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 396 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 397 #endif
 398
 399 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 400 #ifdef CONFIG_PCIE3
 401 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 402 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 403 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 404 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 405 #endif
 406
 407 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 408 #endif  /* CONFIG_PCI */
 409
 410 /*
 411  * USB
 412  */
 413 #define CONFIG_HAS_FSL_DR_USB
 414
 415 #ifdef CONFIG_HAS_FSL_DR_USB
 416 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 417 #endif
 418
 419 /*
 420  * SDHC
 421  */
 422 #ifdef CONFIG_MMC
 423 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 424 #endif
 425
 426 /* Qman/Bman */
 427 #ifndef CONFIG_NOBQFMAN
 428 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 429 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 430 #ifdef CONFIG_PHYS_64BIT
 431 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 432 #else
 433 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 434 #endif
 435 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 436 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 437 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 438 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 439 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 440 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 441                                         CONFIG_SYS_BMAN_CENA_SIZE)
 442 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 443 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 444 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 445 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 446 #ifdef CONFIG_PHYS_64BIT
 447 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 448 #else
 449 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 450 #endif
 451 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 452 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 453 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 454 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 455 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 456 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 457                                         CONFIG_SYS_QMAN_CENA_SIZE)
 458 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 459 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 460
 461 #define CONFIG_SYS_DPAA_FMAN
 462
 463 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 464 #endif /* CONFIG_NOBQFMAN */
 465
 466 #ifdef CONFIG_SYS_DPAA_FMAN
 467 #if defined(CONFIG_TARGET_T1024RDB)
 468 #define RGMII_PHY1_ADDR         0x2
 469 #define RGMII_PHY2_ADDR         0x6
 470 #define SGMII_AQR_PHY_ADDR      0x2
 471 #define FM1_10GEC1_PHY_ADDR     0x1
 472 #elif defined(CONFIG_TARGET_T1023RDB)
 473 #define RGMII_PHY1_ADDR         0x1
 474 #define SGMII_RTK_PHY_ADDR      0x3
 475 #define SGMII_AQR_PHY_ADDR      0x2
 476 #endif
 477 #endif
 478
 479 /*
 480  * Dynamic MTD Partition support with mtdparts
 481  */
 482
 483 /*
 484  * Environment
 485  */
 486 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 487 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 488
 489 /*
 490  * Miscellaneous configurable options
 491  */
 492
 493 /*
 494  * For booting Linux, the board info and command line data
 495  * have to be in the first 64 MB of memory, since this is
 496  * the maximum mapped by the Linux kernel during initialization.
 497  */
 498 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 499 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 500
 501 /*
 502  * Environment Configuration
 503  */
 504 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 505 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 506 #define __USB_PHY_TYPE          utmi
 507
 508 #ifdef CONFIG_ARCH_T1024
 509 #define ARCH_EXTRA_ENV_SETTINGS \
 510         "bank_intlv=cs0_cs1\0"                  \
 511         "ramdiskfile=t1024rdb/ramdisk.uboot\0"  \
 512         "fdtfile=t1024rdb/t1024rdb.dtb\0"
 513 #else
 514 #define ARCH_EXTRA_ENV_SETTINGS \
 515         "bank_intlv=null\0"                     \
 516         "ramdiskfile=t1023rdb/ramdisk.uboot\0"  \
 517         "fdtfile=t1023rdb/t1023rdb.dtb\0"
 518 #endif
 519
 520 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 521         ARCH_EXTRA_ENV_SETTINGS                                 \
 522         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 523         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 524         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 525         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 526         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 527         "netdev=eth0\0"                                         \
 528         "tftpflash=tftpboot $loadaddr $uboot && "               \
 529         "protect off $ubootaddr +$filesize && "                 \
 530         "erase $ubootaddr +$filesize && "                       \
 531         "cp.b $loadaddr $ubootaddr $filesize && "               \
 532         "protect on $ubootaddr +$filesize && "                  \
 533         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 534         "consoledev=ttyS0\0"                                    \
 535         "ramdiskaddr=2000000\0"                                 \
 536         "fdtaddr=1e00000\0"                                     \
 537         "bdev=sda3\0"
 538
 539 #include <asm/fsl_secure_boot.h>
 540
 541 #endif  /* __T1024RDB_H */