include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 /* support deep sleep */
  24 #ifdef CONFIG_ARCH_T1024
  25 #define CONFIG_DEEP_SLEEP
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #endif
  39
  40 #ifdef CONFIG_MTD_RAW_NAND
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  42 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  43 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  44 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  45 #endif
  46
  47 #ifdef CONFIG_SPIFLASH
  48 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  49 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  54 #ifndef CONFIG_SPL_BUILD
  55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  56 #endif
  57 #endif
  58
  59 #ifdef CONFIG_SDCARD
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  61 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  62 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  63 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  64 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #endif
  69
  70 #endif /* CONFIG_RAMBOOT_PBL */
  71
  72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  73 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  74 #endif
  75
  76 /* PCIe Boot - Master */
  77 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  78 /*
  79  * for slave u-boot IMAGE instored in master memory space,
  80  * PHYS must be aligned based on the SIZE
  81  */
  82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  83 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  84 #ifdef CONFIG_PHYS_64BIT
  85 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  86 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  87 #else
  88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  89 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  90 #endif
  91 /*
  92  * for slave UCODE and ENV instored in master memory space,
  93  * PHYS must be aligned based on the SIZE
  94  */
  95 #ifdef CONFIG_PHYS_64BIT
  96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  97 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
  98 #else
  99 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 100 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 101 #endif
 102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 103 /* slave core release by master*/
 104 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 105 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 106
 107 /* PCIe Boot - Slave */
 108 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 109 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 110 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 111                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 112 /* Set 1M boot space for PCIe boot */
 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 115                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 117 #endif
 118
 119 #ifndef __ASSEMBLY__
 120 unsigned long get_board_sys_clk(void);
 121 #endif
 122
 123 #define CONFIG_SYS_CLK_FREQ     100000000
 124
 125 /*
 126  * These can be toggled for performance analysis, otherwise use default.
 127  */
 128 #define CONFIG_SYS_CACHE_STASHING
 129 #define CONFIG_BACKSIDE_L2_CACHE
 130 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 131 #define CONFIG_BTB                      /* toggle branch predition */
 132 #ifdef CONFIG_DDR_ECC
 133 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 134 #endif
 135
 136 /*
 137  *  Config the L3 Cache as L3 SRAM
 138  */
 139 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 140 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 141 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 142 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 143 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 144 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 145 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 146
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_DCSRBAR              0xf0000000
 149 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 150 #endif
 151
 152 /* EEPROM */
 153 #define CONFIG_SYS_I2C_EEPROM_NXID
 154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 155
 156 /*
 157  * DDR Setup
 158  */
 159 #define CONFIG_VERY_BIG_RAM
 160 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 161 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 162 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 163 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 164 #if defined(CONFIG_TARGET_T1024RDB)
 165 #define CONFIG_SYS_SPD_BUS_NUM  0
 166 #define SPD_EEPROM_ADDRESS      0x51
 167 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 168 #elif defined(CONFIG_TARGET_T1023RDB)
 169 #define CONFIG_SYS_DDR_RAW_TIMING
 170 #define CONFIG_SYS_SDRAM_SIZE   2048
 171 #endif
 172
 173 /*
 174  * IFC Definitions
 175  */
 176 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 179 #else
 180 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 181 #endif
 182
 183 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 184 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 185                                 CSPR_PORT_SIZE_16 | \
 186                                 CSPR_MSEL_NOR | \
 187                                 CSPR_V)
 188 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 189
 190 /* NOR Flash Timing Params */
 191 #if defined(CONFIG_TARGET_T1024RDB)
 192 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 193 #elif defined(CONFIG_TARGET_T1023RDB)
 194 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 195                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 196 #endif
 197 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 198                                 FTIM0_NOR_TEADC(0x5) | \
 199                                 FTIM0_NOR_TEAHC(0x5))
 200 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 201                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 202                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 203 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 204                                 FTIM2_NOR_TCH(0x4) | \
 205                                 FTIM2_NOR_TWPH(0x0E) | \
 206                                 FTIM2_NOR_TWP(0x1c))
 207 #define CONFIG_SYS_NOR_FTIM3    0x0
 208
 209 #define CONFIG_SYS_FLASH_QUIET_TEST
 210 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 211
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 214 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 216
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO
 218 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 219
 220 #ifdef CONFIG_TARGET_T1024RDB
 221 /* CPLD on IFC */
 222 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 223 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 224 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 225 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 226                                                 | CSPR_PORT_SIZE_8 \
 227                                                 | CSPR_MSEL_GPCM \
 228                                                 | CSPR_V)
 229 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 230 #define CONFIG_SYS_CSOR2                0x0
 231
 232 /* CPLD Timing parameters for IFC CS2 */
 233 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 234                                                 FTIM0_GPCM_TEADC(0x0e) | \
 235                                                 FTIM0_GPCM_TEAHC(0x0e))
 236 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 237                                                 FTIM1_GPCM_TRAD(0x1f))
 238 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 239                                                 FTIM2_GPCM_TCH(0x8) | \
 240                                                 FTIM2_GPCM_TWP(0x1f))
 241 #define CONFIG_SYS_CS2_FTIM3            0x0
 242 #endif
 243
 244 /* NAND Flash on IFC */
 245 #define CONFIG_NAND_FSL_IFC
 246 #define CONFIG_SYS_NAND_BASE            0xff800000
 247 #ifdef CONFIG_PHYS_64BIT
 248 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 249 #else
 250 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 251 #endif
 252 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 253 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 254                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 255                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 256                                 | CSPR_V)
 257 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 258
 259 #if defined(CONFIG_TARGET_T1024RDB)
 260 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 261                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 262                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 263                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 264                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 265                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 266                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 267 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 268 #elif defined(CONFIG_TARGET_T1023RDB)
 269 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 270                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 271                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 272                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 273                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 274                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 275                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 276 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 277 #endif
 278
 279 #define CONFIG_SYS_NAND_ONFI_DETECTION
 280 /* ONFI NAND Flash mode0 Timing Params */
 281 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 282                                         FTIM0_NAND_TWP(0x18)   | \
 283                                         FTIM0_NAND_TWCHT(0x07) | \
 284                                         FTIM0_NAND_TWH(0x0a))
 285 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 286                                         FTIM1_NAND_TWBE(0x39)  | \
 287                                         FTIM1_NAND_TRR(0x0e)   | \
 288                                         FTIM1_NAND_TRP(0x18))
 289 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 290                                         FTIM2_NAND_TREH(0x0a) | \
 291                                         FTIM2_NAND_TWHRE(0x1e))
 292 #define CONFIG_SYS_NAND_FTIM3           0x0
 293
 294 #define CONFIG_SYS_NAND_DDR_LAW         11
 295 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 296 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 297
 298 #if defined(CONFIG_MTD_RAW_NAND)
 299 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 300 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 301 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 302 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 303 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 304 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 305 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 306 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 307 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 308 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 309 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 310 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 311 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 312 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 313 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 314 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 315 #else
 316 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 317 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 318 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 319 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 320 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 321 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 322 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 323 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 324 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 325 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 326 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 327 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 328 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 329 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 330 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 331 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 332 #endif
 333
 334 #ifdef CONFIG_SPL_BUILD
 335 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 336 #else
 337 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 338 #endif
 339
 340 #if defined(CONFIG_RAMBOOT_PBL)
 341 #define CONFIG_SYS_RAMBOOT
 342 #endif
 343
 344 #define CONFIG_HWCONFIG
 345
 346 /* define to use L1 as initial stack */
 347 #define CONFIG_L1_INIT_RAM
 348 #define CONFIG_SYS_INIT_RAM_LOCK
 349 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 350 #ifdef CONFIG_PHYS_64BIT
 351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 353 /* The assembler doesn't like typecast */
 354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 355         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 356           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 357 #else
 358 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 361 #endif
 362 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 363
 364 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 365                                         GENERATED_GBL_DATA_SIZE)
 366 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 367
 368 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 369
 370 /* Serial Port */
 371 #define CONFIG_SYS_NS16550_SERIAL
 372 #define CONFIG_SYS_NS16550_REG_SIZE     1
 373 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 374
 375 #define CONFIG_SYS_BAUDRATE_TABLE       \
 376         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 377
 378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 380 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 381 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 382
 383 /* Video */
 384 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 385 #ifdef CONFIG_FSL_DIU_FB
 386 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 387 #define CONFIG_VIDEO_LOGO
 388 #define CONFIG_VIDEO_BMP_LOGO
 389 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 390 /*
 391  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 392  * disable empty flash sector detection, which is I/O-intensive.
 393  */
 394 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 395 #endif
 396
 397 /* I2C */
 398
 399 #define I2C_PCA6408_BUS_NUM             1
 400 #define I2C_PCA6408_ADDR                0x20
 401
 402 /* I2C bus multiplexer */
 403 #define I2C_MUX_CH_DEFAULT      0x8
 404
 405 /*
 406  * RTC configuration
 407  */
 408 #define RTC
 409 #define CONFIG_RTC_DS1337       1
 410 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 411
 412 /*
 413  * eSPI - Enhanced SPI
 414  */
 415
 416 /*
 417  * General PCIe
 418  * Memory space is mapped 1-1, but I/O space must start from 0.
 419  */
 420 #define CONFIG_PCIE1            /* PCIE controller 1 */
 421 #define CONFIG_PCIE2            /* PCIE controller 2 */
 422 #define CONFIG_PCIE3            /* PCIE controller 3 */
 423 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 424
 425 #ifdef CONFIG_PCI
 426 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 427 #ifdef CONFIG_PCIE1
 428 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 429 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 430 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 431 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 432 #endif
 433
 434 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 435 #ifdef CONFIG_PCIE2
 436 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 437 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 438 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 439 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 440 #endif
 441
 442 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 443 #ifdef CONFIG_PCIE3
 444 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 445 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 446 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 447 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 448 #endif
 449
 450 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 451 #endif  /* CONFIG_PCI */
 452
 453 /*
 454  * USB
 455  */
 456 #define CONFIG_HAS_FSL_DR_USB
 457
 458 #ifdef CONFIG_HAS_FSL_DR_USB
 459 #define CONFIG_USB_EHCI_FSL
 460 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 461 #endif
 462
 463 /*
 464  * SDHC
 465  */
 466 #ifdef CONFIG_MMC
 467 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 468 #endif
 469
 470 /* Qman/Bman */
 471 #ifndef CONFIG_NOBQFMAN
 472 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 473 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 476 #else
 477 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 478 #endif
 479 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 480 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 481 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 482 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 483 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 484 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 485                                         CONFIG_SYS_BMAN_CENA_SIZE)
 486 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 487 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 488 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 489 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 490 #ifdef CONFIG_PHYS_64BIT
 491 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 492 #else
 493 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 494 #endif
 495 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 496 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 497 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 498 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 499 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 500 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 501                                         CONFIG_SYS_QMAN_CENA_SIZE)
 502 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 503 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 504
 505 #define CONFIG_SYS_DPAA_FMAN
 506
 507 /* Default address of microcode for the Linux FMan driver */
 508 #if defined(CONFIG_SPIFLASH)
 509 /*
 510  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 511  * env, so we got 0x110000.
 512  */
 513 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 514 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 515 #elif defined(CONFIG_SDCARD)
 516 /*
 517  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 518  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 519  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 520  */
 521 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 522 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 523 #elif defined(CONFIG_MTD_RAW_NAND)
 524 #if defined(CONFIG_TARGET_T1024RDB)
 525 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 526 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 527 #elif defined(CONFIG_TARGET_T1023RDB)
 528 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 529 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 530 #endif
 531 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 532 /*
 533  * Slave has no ucode locally, it can fetch this from remote. When implementing
 534  * in two corenet boards, slave's ucode could be stored in master's memory
 535  * space, the address can be mapped from slave TLB->slave LAW->
 536  * slave SRIO or PCIE outbound window->master inbound window->
 537  * master LAW->the ucode address in master's memory space.
 538  */
 539 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 540 #else
 541 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 542 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 543 #endif
 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 545 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 546 #endif /* CONFIG_NOBQFMAN */
 547
 548 #ifdef CONFIG_SYS_DPAA_FMAN
 549 #if defined(CONFIG_TARGET_T1024RDB)
 550 #define RGMII_PHY1_ADDR         0x2
 551 #define RGMII_PHY2_ADDR         0x6
 552 #define SGMII_AQR_PHY_ADDR      0x2
 553 #define FM1_10GEC1_PHY_ADDR     0x1
 554 #elif defined(CONFIG_TARGET_T1023RDB)
 555 #define RGMII_PHY1_ADDR         0x1
 556 #define SGMII_RTK_PHY_ADDR      0x3
 557 #define SGMII_AQR_PHY_ADDR      0x2
 558 #endif
 559 #endif
 560
 561 #ifdef CONFIG_FMAN_ENET
 562 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 563 #endif
 564
 565 /*
 566  * Dynamic MTD Partition support with mtdparts
 567  */
 568
 569 /*
 570  * Environment
 571  */
 572 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 573 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 574
 575 /*
 576  * Miscellaneous configurable options
 577  */
 578
 579 /*
 580  * For booting Linux, the board info and command line data
 581  * have to be in the first 64 MB of memory, since this is
 582  * the maximum mapped by the Linux kernel during initialization.
 583  */
 584 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 585 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 586
 587 /*
 588  * Environment Configuration
 589  */
 590 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 591 #define CONFIG_BOOTFILE         "uImage"
 592 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 593 #define __USB_PHY_TYPE          utmi
 594
 595 #ifdef CONFIG_ARCH_T1024
 596 #define CONFIG_BOARDNAME t1024rdb
 597 #define BANK_INTLV cs0_cs1
 598 #else
 599 #define CONFIG_BOARDNAME t1023rdb
 600 #define BANK_INTLV  null
 601 #endif
 602
 603 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 604         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 605         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 606         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 607         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 608         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 609         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 610         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 611         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 612         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 613         "netdev=eth0\0"                                         \
 614         "tftpflash=tftpboot $loadaddr $uboot && "               \
 615         "protect off $ubootaddr +$filesize && "                 \
 616         "erase $ubootaddr +$filesize && "                       \
 617         "cp.b $loadaddr $ubootaddr $filesize && "               \
 618         "protect on $ubootaddr +$filesize && "                  \
 619         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 620         "consoledev=ttyS0\0"                                    \
 621         "ramdiskaddr=2000000\0"                                 \
 622         "fdtaddr=1e00000\0"                                     \
 623         "bdev=sda3\0"
 624
 625 #define LINUXBOOTCOMMAND                                        \
 626         "setenv bootargs root=/dev/ram rw "             \
 627         "console=$consoledev,$baudrate $othbootargs;"   \
 628         "setenv ramdiskaddr 0x02000000;"                \
 629         "setenv fdtaddr 0x00c00000;"                    \
 630         "setenv loadaddr 0x1000000;"                    \
 631         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 632
 633 #define NFSBOOTCOMMAND                  \
 634         "setenv bootargs root=/dev/nfs rw "     \
 635         "nfsroot=$serverip:$rootpath "          \
 636         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 637         "console=$consoledev,$baudrate $othbootargs;"   \
 638         "tftp $loadaddr $bootfile;"             \
 639         "tftp $fdtaddr $fdtfile;"               \
 640         "bootm $loadaddr - $fdtaddr"
 641
 642 #define CONFIG_BOOTCOMMAND      LINUXBOOTCOMMAND
 643
 644 #include <asm/fsl_secure_boot.h>
 645
 646 #endif  /* __T1024RDB_H */