include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 /* support deep sleep */
  24 #ifdef CONFIG_ARCH_T1024
  25 #define CONFIG_DEEP_SLEEP
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  30 #define CONFIG_SPL_FLUSH_IMAGE
  31 #define CONFIG_SPL_PAD_TO               0x40000
  32 #define CONFIG_SPL_MAX_SIZE             0x28000
  33 #define RESET_VECTOR_OFFSET             0x27FFC
  34 #define BOOT_PAGE_OFFSET                0x27000
  35 #ifdef CONFIG_SPL_BUILD
  36 #define CONFIG_SPL_SKIP_RELOCATE
  37 #define CONFIG_SPL_COMMON_INIT_DDR
  38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39 #endif
  40
  41 #ifdef CONFIG_MTD_RAW_NAND
  42 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  44 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  45 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  46 #if defined(CONFIG_TARGET_T1024RDB)
  47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  48 #elif defined(CONFIG_TARGET_T1023RDB)
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_SPIFLASH
  54 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  60 #ifndef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #if defined(CONFIG_TARGET_T1024RDB)
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  65 #elif defined(CONFIG_TARGET_T1023RDB)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  67 #endif
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #if defined(CONFIG_TARGET_T1024RDB)
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  81 #elif defined(CONFIG_TARGET_T1023RDB)
  82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  83 #endif
  84 #endif
  85
  86 #endif /* CONFIG_RAMBOOT_PBL */
  87
  88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  89 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  90 #endif
  91
  92 /* PCIe Boot - Master */
  93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  94 /*
  95  * for slave u-boot IMAGE instored in master memory space,
  96  * PHYS must be aligned based on the SIZE
  97  */
  98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  99 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 103 #else
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 106 #endif
 107 /*
 108  * for slave UCODE and ENV instored in master memory space,
 109  * PHYS must be aligned based on the SIZE
 110  */
 111 #ifdef CONFIG_PHYS_64BIT
 112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 113 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 114 #else
 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 117 #endif
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 119 /* slave core release by master*/
 120 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 121 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 122
 123 /* PCIe Boot - Slave */
 124 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 127                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 128 /* Set 1M boot space for PCIe boot */
 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 131                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 133 #endif
 134
 135 #ifndef __ASSEMBLY__
 136 unsigned long get_board_sys_clk(void);
 137 #endif
 138
 139 #define CONFIG_SYS_CLK_FREQ     100000000
 140
 141 /*
 142  * These can be toggled for performance analysis, otherwise use default.
 143  */
 144 #define CONFIG_SYS_CACHE_STASHING
 145 #define CONFIG_BACKSIDE_L2_CACHE
 146 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 147 #define CONFIG_BTB                      /* toggle branch predition */
 148 #ifdef CONFIG_DDR_ECC
 149 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 150 #endif
 151
 152 /*
 153  *  Config the L3 Cache as L3 SRAM
 154  */
 155 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 156 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 157 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 158 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 159 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 160 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 161 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 162
 163 #ifdef CONFIG_PHYS_64BIT
 164 #define CONFIG_SYS_DCSRBAR              0xf0000000
 165 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 166 #endif
 167
 168 /* EEPROM */
 169 #define CONFIG_SYS_I2C_EEPROM_NXID
 170 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 171
 172 /*
 173  * DDR Setup
 174  */
 175 #define CONFIG_VERY_BIG_RAM
 176 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 177 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 178 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 179 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 180 #if defined(CONFIG_TARGET_T1024RDB)
 181 #define CONFIG_SYS_SPD_BUS_NUM  0
 182 #define SPD_EEPROM_ADDRESS      0x51
 183 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 184 #elif defined(CONFIG_TARGET_T1023RDB)
 185 #define CONFIG_SYS_DDR_RAW_TIMING
 186 #define CONFIG_SYS_SDRAM_SIZE   2048
 187 #endif
 188
 189 /*
 190  * IFC Definitions
 191  */
 192 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 193 #ifdef CONFIG_PHYS_64BIT
 194 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 195 #else
 196 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 197 #endif
 198
 199 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 200 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 201                                 CSPR_PORT_SIZE_16 | \
 202                                 CSPR_MSEL_NOR | \
 203                                 CSPR_V)
 204 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 205
 206 /* NOR Flash Timing Params */
 207 #if defined(CONFIG_TARGET_T1024RDB)
 208 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 209 #elif defined(CONFIG_TARGET_T1023RDB)
 210 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 211                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 212 #endif
 213 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 214                                 FTIM0_NOR_TEADC(0x5) | \
 215                                 FTIM0_NOR_TEAHC(0x5))
 216 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 217                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 218                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 219 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 220                                 FTIM2_NOR_TCH(0x4) | \
 221                                 FTIM2_NOR_TWPH(0x0E) | \
 222                                 FTIM2_NOR_TWP(0x1c))
 223 #define CONFIG_SYS_NOR_FTIM3    0x0
 224
 225 #define CONFIG_SYS_FLASH_QUIET_TEST
 226 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 227
 228 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 232
 233 #define CONFIG_SYS_FLASH_EMPTY_INFO
 234 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 235
 236 #ifdef CONFIG_TARGET_T1024RDB
 237 /* CPLD on IFC */
 238 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 239 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 240 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 241 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 242                                                 | CSPR_PORT_SIZE_8 \
 243                                                 | CSPR_MSEL_GPCM \
 244                                                 | CSPR_V)
 245 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 246 #define CONFIG_SYS_CSOR2                0x0
 247
 248 /* CPLD Timing parameters for IFC CS2 */
 249 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 250                                                 FTIM0_GPCM_TEADC(0x0e) | \
 251                                                 FTIM0_GPCM_TEAHC(0x0e))
 252 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 253                                                 FTIM1_GPCM_TRAD(0x1f))
 254 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 255                                                 FTIM2_GPCM_TCH(0x8) | \
 256                                                 FTIM2_GPCM_TWP(0x1f))
 257 #define CONFIG_SYS_CS2_FTIM3            0x0
 258 #endif
 259
 260 /* NAND Flash on IFC */
 261 #define CONFIG_NAND_FSL_IFC
 262 #define CONFIG_SYS_NAND_BASE            0xff800000
 263 #ifdef CONFIG_PHYS_64BIT
 264 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 265 #else
 266 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 267 #endif
 268 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 269 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 270                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 271                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 272                                 | CSPR_V)
 273 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 274
 275 #if defined(CONFIG_TARGET_T1024RDB)
 276 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 277                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 278                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 279                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 280                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 281                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 282                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 283 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 284 #elif defined(CONFIG_TARGET_T1023RDB)
 285 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 286                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 287                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 288                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 289                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 290                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 291                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 292 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 293 #endif
 294
 295 #define CONFIG_SYS_NAND_ONFI_DETECTION
 296 /* ONFI NAND Flash mode0 Timing Params */
 297 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 298                                         FTIM0_NAND_TWP(0x18)   | \
 299                                         FTIM0_NAND_TWCHT(0x07) | \
 300                                         FTIM0_NAND_TWH(0x0a))
 301 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 302                                         FTIM1_NAND_TWBE(0x39)  | \
 303                                         FTIM1_NAND_TRR(0x0e)   | \
 304                                         FTIM1_NAND_TRP(0x18))
 305 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 306                                         FTIM2_NAND_TREH(0x0a) | \
 307                                         FTIM2_NAND_TWHRE(0x1e))
 308 #define CONFIG_SYS_NAND_FTIM3           0x0
 309
 310 #define CONFIG_SYS_NAND_DDR_LAW         11
 311 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 312 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 313
 314 #if defined(CONFIG_MTD_RAW_NAND)
 315 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 316 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 317 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 318 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 319 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 320 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 321 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 322 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 323 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 324 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 325 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 326 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 327 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 328 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 329 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 330 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 331 #else
 332 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 333 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 334 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 335 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 336 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 337 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 338 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 339 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 340 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 341 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 342 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 343 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 344 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 345 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 346 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 347 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 348 #endif
 349
 350 #ifdef CONFIG_SPL_BUILD
 351 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 352 #else
 353 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 354 #endif
 355
 356 #if defined(CONFIG_RAMBOOT_PBL)
 357 #define CONFIG_SYS_RAMBOOT
 358 #endif
 359
 360 #define CONFIG_HWCONFIG
 361
 362 /* define to use L1 as initial stack */
 363 #define CONFIG_L1_INIT_RAM
 364 #define CONFIG_SYS_INIT_RAM_LOCK
 365 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 366 #ifdef CONFIG_PHYS_64BIT
 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 369 /* The assembler doesn't like typecast */
 370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 371         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 372           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 373 #else
 374 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 375 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 376 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 377 #endif
 378 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 379
 380 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 381                                         GENERATED_GBL_DATA_SIZE)
 382 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 383
 384 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 385 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 386
 387 /* Serial Port */
 388 #define CONFIG_SYS_NS16550_SERIAL
 389 #define CONFIG_SYS_NS16550_REG_SIZE     1
 390 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 391
 392 #define CONFIG_SYS_BAUDRATE_TABLE       \
 393         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 394
 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 397 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 398 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 399
 400 /* Video */
 401 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 402 #ifdef CONFIG_FSL_DIU_FB
 403 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 404 #define CONFIG_VIDEO_LOGO
 405 #define CONFIG_VIDEO_BMP_LOGO
 406 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 407 /*
 408  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 409  * disable empty flash sector detection, which is I/O-intensive.
 410  */
 411 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 412 #endif
 413
 414 /* I2C */
 415
 416 #define I2C_PCA6408_BUS_NUM             1
 417 #define I2C_PCA6408_ADDR                0x20
 418
 419 /* I2C bus multiplexer */
 420 #define I2C_MUX_CH_DEFAULT      0x8
 421
 422 /*
 423  * RTC configuration
 424  */
 425 #define RTC
 426 #define CONFIG_RTC_DS1337       1
 427 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 428
 429 /*
 430  * eSPI - Enhanced SPI
 431  */
 432
 433 /*
 434  * General PCIe
 435  * Memory space is mapped 1-1, but I/O space must start from 0.
 436  */
 437 #define CONFIG_PCIE1            /* PCIE controller 1 */
 438 #define CONFIG_PCIE2            /* PCIE controller 2 */
 439 #define CONFIG_PCIE3            /* PCIE controller 3 */
 440 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 441
 442 #ifdef CONFIG_PCI
 443 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 444 #ifdef CONFIG_PCIE1
 445 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 446 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 447 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 448 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 449 #endif
 450
 451 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 452 #ifdef CONFIG_PCIE2
 453 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 454 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 455 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 456 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 457 #endif
 458
 459 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 460 #ifdef CONFIG_PCIE3
 461 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 462 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 463 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 464 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 465 #endif
 466
 467 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 468 #endif  /* CONFIG_PCI */
 469
 470 /*
 471  * USB
 472  */
 473 #define CONFIG_HAS_FSL_DR_USB
 474
 475 #ifdef CONFIG_HAS_FSL_DR_USB
 476 #define CONFIG_USB_EHCI_FSL
 477 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 478 #endif
 479
 480 /*
 481  * SDHC
 482  */
 483 #ifdef CONFIG_MMC
 484 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 485 #endif
 486
 487 /* Qman/Bman */
 488 #ifndef CONFIG_NOBQFMAN
 489 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 490 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 491 #ifdef CONFIG_PHYS_64BIT
 492 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 493 #else
 494 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 495 #endif
 496 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 497 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 498 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 499 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 500 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 501 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 502                                         CONFIG_SYS_BMAN_CENA_SIZE)
 503 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 504 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 505 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 506 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 507 #ifdef CONFIG_PHYS_64BIT
 508 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 509 #else
 510 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 511 #endif
 512 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 513 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 514 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 515 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 516 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 517 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 518                                         CONFIG_SYS_QMAN_CENA_SIZE)
 519 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 520 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 521
 522 #define CONFIG_SYS_DPAA_FMAN
 523
 524 /* Default address of microcode for the Linux FMan driver */
 525 #if defined(CONFIG_SPIFLASH)
 526 /*
 527  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 528  * env, so we got 0x110000.
 529  */
 530 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 531 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 532 #elif defined(CONFIG_SDCARD)
 533 /*
 534  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 535  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 536  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 537  */
 538 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 539 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 540 #elif defined(CONFIG_MTD_RAW_NAND)
 541 #if defined(CONFIG_TARGET_T1024RDB)
 542 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 543 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 544 #elif defined(CONFIG_TARGET_T1023RDB)
 545 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 546 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 547 #endif
 548 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 549 /*
 550  * Slave has no ucode locally, it can fetch this from remote. When implementing
 551  * in two corenet boards, slave's ucode could be stored in master's memory
 552  * space, the address can be mapped from slave TLB->slave LAW->
 553  * slave SRIO or PCIE outbound window->master inbound window->
 554  * master LAW->the ucode address in master's memory space.
 555  */
 556 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 557 #else
 558 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 559 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 560 #endif
 561 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 562 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 563 #endif /* CONFIG_NOBQFMAN */
 564
 565 #ifdef CONFIG_SYS_DPAA_FMAN
 566 #if defined(CONFIG_TARGET_T1024RDB)
 567 #define RGMII_PHY1_ADDR         0x2
 568 #define RGMII_PHY2_ADDR         0x6
 569 #define SGMII_AQR_PHY_ADDR      0x2
 570 #define FM1_10GEC1_PHY_ADDR     0x1
 571 #elif defined(CONFIG_TARGET_T1023RDB)
 572 #define RGMII_PHY1_ADDR         0x1
 573 #define SGMII_RTK_PHY_ADDR      0x3
 574 #define SGMII_AQR_PHY_ADDR      0x2
 575 #endif
 576 #endif
 577
 578 #ifdef CONFIG_FMAN_ENET
 579 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 580 #endif
 581
 582 /*
 583  * Dynamic MTD Partition support with mtdparts
 584  */
 585
 586 /*
 587  * Environment
 588  */
 589 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 590 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 591
 592 /*
 593  * Miscellaneous configurable options
 594  */
 595 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 596
 597 /*
 598  * For booting Linux, the board info and command line data
 599  * have to be in the first 64 MB of memory, since this is
 600  * the maximum mapped by the Linux kernel during initialization.
 601  */
 602 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 603 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 604
 605 #ifdef CONFIG_CMD_KGDB
 606 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 607 #endif
 608
 609 /*
 610  * Environment Configuration
 611  */
 612 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 613 #define CONFIG_BOOTFILE         "uImage"
 614 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 615 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 616 #define __USB_PHY_TYPE          utmi
 617
 618 #ifdef CONFIG_ARCH_T1024
 619 #define CONFIG_BOARDNAME t1024rdb
 620 #define BANK_INTLV cs0_cs1
 621 #else
 622 #define CONFIG_BOARDNAME t1023rdb
 623 #define BANK_INTLV  null
 624 #endif
 625
 626 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 627         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 628         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 629         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 630         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 631         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 632         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 633         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 634         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 635         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 636         "netdev=eth0\0"                                         \
 637         "tftpflash=tftpboot $loadaddr $uboot && "               \
 638         "protect off $ubootaddr +$filesize && "                 \
 639         "erase $ubootaddr +$filesize && "                       \
 640         "cp.b $loadaddr $ubootaddr $filesize && "               \
 641         "protect on $ubootaddr +$filesize && "                  \
 642         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 643         "consoledev=ttyS0\0"                                    \
 644         "ramdiskaddr=2000000\0"                                 \
 645         "fdtaddr=1e00000\0"                                     \
 646         "bdev=sda3\0"
 647
 648 #define LINUXBOOTCOMMAND                                        \
 649         "setenv bootargs root=/dev/ram rw "             \
 650         "console=$consoledev,$baudrate $othbootargs;"   \
 651         "setenv ramdiskaddr 0x02000000;"                \
 652         "setenv fdtaddr 0x00c00000;"                    \
 653         "setenv loadaddr 0x1000000;"                    \
 654         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 655
 656 #define NFSBOOTCOMMAND                  \
 657         "setenv bootargs root=/dev/nfs rw "     \
 658         "nfsroot=$serverip:$rootpath "          \
 659         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 660         "console=$consoledev,$baudrate $othbootargs;"   \
 661         "tftp $loadaddr $bootfile;"             \
 662         "tftp $fdtaddr $fdtfile;"               \
 663         "bootm $loadaddr - $fdtaddr"
 664
 665 #define CONFIG_BOOTCOMMAND      LINUXBOOTCOMMAND
 666
 667 #include <asm/fsl_secure_boot.h>
 668
 669 #endif  /* __T1024RDB_H */