1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T1024/T1023 RDB board configuration file
14 #include <linux/stringify.h>
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
23 /* support deep sleep */
24 #ifdef CONFIG_ARCH_T1024
25 #define CONFIG_DEEP_SLEEP
28 #ifdef CONFIG_RAMBOOT_PBL
29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
30 #define CONFIG_SPL_FLUSH_IMAGE
31 #define CONFIG_SPL_PAD_TO 0x40000
32 #define CONFIG_SPL_MAX_SIZE 0x28000
33 #define RESET_VECTOR_OFFSET 0x27FFC
34 #define BOOT_PAGE_OFFSET 0x27000
35 #ifdef CONFIG_SPL_BUILD
36 #define CONFIG_SPL_SKIP_RELOCATE
37 #define CONFIG_SPL_COMMON_INIT_DDR
38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41 #ifdef CONFIG_MTD_RAW_NAND
42 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
44 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
45 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
46 #if defined(CONFIG_TARGET_T1024RDB)
47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
48 #elif defined(CONFIG_TARGET_T1023RDB)
49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
53 #ifdef CONFIG_SPIFLASH
54 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
60 #ifndef CONFIG_SPL_BUILD
61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #if defined(CONFIG_TARGET_T1024RDB)
64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
65 #elif defined(CONFIG_TARGET_T1023RDB)
66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
71 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
72 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
73 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
74 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
75 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
76 #ifndef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
79 #if defined(CONFIG_TARGET_T1024RDB)
80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
81 #elif defined(CONFIG_TARGET_T1023RDB)
82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
86 #endif /* CONFIG_RAMBOOT_PBL */
88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
89 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
92 /* PCIe Boot - Master */
93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
95 * for slave u-boot IMAGE instored in master memory space,
96 * PHYS must be aligned based on the SIZE
98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
99 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
100 #ifdef CONFIG_PHYS_64BIT
101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
108 * for slave UCODE and ENV instored in master memory space,
109 * PHYS must be aligned based on the SIZE
111 #ifdef CONFIG_PHYS_64BIT
112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
113 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
119 /* slave core release by master*/
120 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
121 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
123 /* PCIe Boot - Slave */
124 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
125 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
126 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
127 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
128 /* Set 1M boot space for PCIe boot */
129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
130 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
131 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
132 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
136 unsigned long get_board_sys_clk(void);
137 unsigned long get_board_ddr_clk(void);
140 #define CONFIG_SYS_CLK_FREQ 100000000
141 #define CONFIG_DDR_CLK_FREQ 100000000
144 * These can be toggled for performance analysis, otherwise use default.
146 #define CONFIG_SYS_CACHE_STASHING
147 #define CONFIG_BACKSIDE_L2_CACHE
148 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
149 #define CONFIG_BTB /* toggle branch predition */
150 #define CONFIG_DDR_ECC
151 #ifdef CONFIG_DDR_ECC
152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
153 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
157 * Config the L3 Cache as L3 SRAM
159 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
160 #define CONFIG_SYS_L3_SIZE (256 << 10)
161 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
162 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
163 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
164 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
165 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
167 #ifdef CONFIG_PHYS_64BIT
168 #define CONFIG_SYS_DCSRBAR 0xf0000000
169 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
173 #define CONFIG_SYS_I2C_EEPROM_NXID
174 #define CONFIG_SYS_EEPROM_BUS_NUM 0
179 #define CONFIG_VERY_BIG_RAM
180 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
181 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
182 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
183 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
184 #if defined(CONFIG_TARGET_T1024RDB)
185 #define CONFIG_DDR_SPD
186 #define CONFIG_SYS_SPD_BUS_NUM 0
187 #define SPD_EEPROM_ADDRESS 0x51
188 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
189 #elif defined(CONFIG_TARGET_T1023RDB)
190 #define CONFIG_SYS_DDR_RAW_TIMING
191 #define CONFIG_SYS_SDRAM_SIZE 2048
197 #define CONFIG_SYS_FLASH_BASE 0xe8000000
198 #ifdef CONFIG_PHYS_64BIT
199 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
205 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
206 CSPR_PORT_SIZE_16 | \
209 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
211 /* NOR Flash Timing Params */
212 #if defined(CONFIG_TARGET_T1024RDB)
213 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
214 #elif defined(CONFIG_TARGET_T1023RDB)
215 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
216 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
218 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
219 FTIM0_NOR_TEADC(0x5) | \
220 FTIM0_NOR_TEAHC(0x5))
221 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
222 FTIM1_NOR_TRAD_NOR(0x1A) |\
223 FTIM1_NOR_TSEQRAD_NOR(0x13))
224 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
225 FTIM2_NOR_TCH(0x4) | \
226 FTIM2_NOR_TWPH(0x0E) | \
228 #define CONFIG_SYS_NOR_FTIM3 0x0
230 #define CONFIG_SYS_FLASH_QUIET_TEST
231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
238 #define CONFIG_SYS_FLASH_EMPTY_INFO
239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
241 #ifdef CONFIG_TARGET_T1024RDB
243 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
244 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
245 #define CONFIG_SYS_CSPR2_EXT (0xf)
246 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
250 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
251 #define CONFIG_SYS_CSOR2 0x0
253 /* CPLD Timing parameters for IFC CS2 */
254 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
255 FTIM0_GPCM_TEADC(0x0e) | \
256 FTIM0_GPCM_TEAHC(0x0e))
257 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
258 FTIM1_GPCM_TRAD(0x1f))
259 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
260 FTIM2_GPCM_TCH(0x8) | \
261 FTIM2_GPCM_TWP(0x1f))
262 #define CONFIG_SYS_CS2_FTIM3 0x0
265 /* NAND Flash on IFC */
266 #define CONFIG_NAND_FSL_IFC
267 #define CONFIG_SYS_NAND_BASE 0xff800000
268 #ifdef CONFIG_PHYS_64BIT
269 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
271 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
273 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
274 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
275 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
276 | CSPR_MSEL_NAND /* MSEL = NAND */ \
278 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
280 #if defined(CONFIG_TARGET_T1024RDB)
281 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
282 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
283 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
284 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
285 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
286 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
287 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
288 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
289 #elif defined(CONFIG_TARGET_T1023RDB)
290 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
291 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
292 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
293 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
294 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
295 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
296 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
300 #define CONFIG_SYS_NAND_ONFI_DETECTION
301 /* ONFI NAND Flash mode0 Timing Params */
302 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
303 FTIM0_NAND_TWP(0x18) | \
304 FTIM0_NAND_TWCHT(0x07) | \
305 FTIM0_NAND_TWH(0x0a))
306 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
307 FTIM1_NAND_TWBE(0x39) | \
308 FTIM1_NAND_TRR(0x0e) | \
309 FTIM1_NAND_TRP(0x18))
310 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
311 FTIM2_NAND_TREH(0x0a) | \
312 FTIM2_NAND_TWHRE(0x1e))
313 #define CONFIG_SYS_NAND_FTIM3 0x0
315 #define CONFIG_SYS_NAND_DDR_LAW 11
316 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
317 #define CONFIG_SYS_MAX_NAND_DEVICE 1
319 #if defined(CONFIG_MTD_RAW_NAND)
320 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
321 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
322 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
323 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
324 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
325 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
326 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
327 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
328 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
329 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
330 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
355 #ifdef CONFIG_SPL_BUILD
356 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
358 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
361 #if defined(CONFIG_RAMBOOT_PBL)
362 #define CONFIG_SYS_RAMBOOT
365 #define CONFIG_HWCONFIG
367 /* define to use L1 as initial stack */
368 #define CONFIG_L1_INIT_RAM
369 #define CONFIG_SYS_INIT_RAM_LOCK
370 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
371 #ifdef CONFIG_PHYS_64BIT
372 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
374 /* The assembler doesn't like typecast */
375 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
376 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
377 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
386 GENERATED_GBL_DATA_SIZE)
387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
390 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
393 #define CONFIG_SYS_NS16550_SERIAL
394 #define CONFIG_SYS_NS16550_REG_SIZE 1
395 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
397 #define CONFIG_SYS_BAUDRATE_TABLE \
398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
400 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
401 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
402 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
403 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
406 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
407 #ifdef CONFIG_FSL_DIU_FB
408 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
409 #define CONFIG_VIDEO_LOGO
410 #define CONFIG_VIDEO_BMP_LOGO
411 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
413 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
414 * disable empty flash sector detection, which is I/O-intensive.
416 #undef CONFIG_SYS_FLASH_EMPTY_INFO
420 #if !CONFIG_IS_ENABLED(DM_I2C)
421 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
422 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
423 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
424 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
425 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
426 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
428 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
429 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
432 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
433 #define I2C_PCA6408_BUS_NUM 1
434 #define I2C_PCA6408_ADDR 0x20
436 /* I2C bus multiplexer */
437 #define I2C_MUX_CH_DEFAULT 0x8
443 #define CONFIG_RTC_DS1337 1
444 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
447 * eSPI - Enhanced SPI
452 * Memory space is mapped 1-1, but I/O space must start from 0.
454 #define CONFIG_PCIE1 /* PCIE controller 1 */
455 #define CONFIG_PCIE2 /* PCIE controller 2 */
456 #define CONFIG_PCIE3 /* PCIE controller 3 */
457 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
460 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
462 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
463 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
464 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
465 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
468 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
470 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
473 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
478 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
479 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
480 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
484 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
485 #endif /* CONFIG_PCI */
490 #define CONFIG_HAS_FSL_DR_USB
492 #ifdef CONFIG_HAS_FSL_DR_USB
493 #define CONFIG_USB_EHCI_FSL
494 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
501 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
505 #ifndef CONFIG_NOBQFMAN
506 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
507 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
508 #ifdef CONFIG_PHYS_64BIT
509 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
511 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
513 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
514 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
515 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
516 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
517 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
518 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
519 CONFIG_SYS_BMAN_CENA_SIZE)
520 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
521 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
522 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
523 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
524 #ifdef CONFIG_PHYS_64BIT
525 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
527 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
529 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
530 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
531 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
532 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
533 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
534 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
535 CONFIG_SYS_QMAN_CENA_SIZE)
536 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
537 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
539 #define CONFIG_SYS_DPAA_FMAN
541 /* Default address of microcode for the Linux FMan driver */
542 #if defined(CONFIG_SPIFLASH)
544 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
545 * env, so we got 0x110000.
547 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
548 #define CONFIG_SYS_QE_FW_ADDR 0x130000
549 #elif defined(CONFIG_SDCARD)
551 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
552 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
553 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
555 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
556 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
557 #elif defined(CONFIG_MTD_RAW_NAND)
558 #if defined(CONFIG_TARGET_T1024RDB)
559 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
560 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
561 #elif defined(CONFIG_TARGET_T1023RDB)
562 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
563 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
565 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
567 * Slave has no ucode locally, it can fetch this from remote. When implementing
568 * in two corenet boards, slave's ucode could be stored in master's memory
569 * space, the address can be mapped from slave TLB->slave LAW->
570 * slave SRIO or PCIE outbound window->master inbound window->
571 * master LAW->the ucode address in master's memory space.
573 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
575 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
576 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
578 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
579 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
580 #endif /* CONFIG_NOBQFMAN */
582 #ifdef CONFIG_SYS_DPAA_FMAN
583 #if defined(CONFIG_TARGET_T1024RDB)
584 #define RGMII_PHY1_ADDR 0x2
585 #define RGMII_PHY2_ADDR 0x6
586 #define SGMII_AQR_PHY_ADDR 0x2
587 #define FM1_10GEC1_PHY_ADDR 0x1
588 #elif defined(CONFIG_TARGET_T1023RDB)
589 #define RGMII_PHY1_ADDR 0x1
590 #define SGMII_RTK_PHY_ADDR 0x3
591 #define SGMII_AQR_PHY_ADDR 0x2
595 #ifdef CONFIG_FMAN_ENET
596 #define CONFIG_ETHPRIME "FM1@DTSEC4"
600 * Dynamic MTD Partition support with mtdparts
606 #define CONFIG_LOADS_ECHO /* echo on for serial download */
607 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
610 * Miscellaneous configurable options
612 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
615 * For booting Linux, the board info and command line data
616 * have to be in the first 64 MB of memory, since this is
617 * the maximum mapped by the Linux kernel during initialization.
619 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
620 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
622 #ifdef CONFIG_CMD_KGDB
623 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
627 * Environment Configuration
629 #define CONFIG_ROOTPATH "/opt/nfsroot"
630 #define CONFIG_BOOTFILE "uImage"
631 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
632 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
633 #define __USB_PHY_TYPE utmi
635 #ifdef CONFIG_ARCH_T1024
636 #define CONFIG_BOARDNAME t1024rdb
637 #define BANK_INTLV cs0_cs1
639 #define CONFIG_BOARDNAME t1023rdb
640 #define BANK_INTLV null
643 #define CONFIG_EXTRA_ENV_SETTINGS \
644 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
645 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
646 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
647 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
648 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
649 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
650 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
651 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
652 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
654 "tftpflash=tftpboot $loadaddr $uboot && " \
655 "protect off $ubootaddr +$filesize && " \
656 "erase $ubootaddr +$filesize && " \
657 "cp.b $loadaddr $ubootaddr $filesize && " \
658 "protect on $ubootaddr +$filesize && " \
659 "cmp.b $loadaddr $ubootaddr $filesize\0" \
660 "consoledev=ttyS0\0" \
661 "ramdiskaddr=2000000\0" \
662 "fdtaddr=1e00000\0" \
665 #define CONFIG_LINUX \
666 "setenv bootargs root=/dev/ram rw " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "setenv ramdiskaddr 0x02000000;" \
669 "setenv fdtaddr 0x00c00000;" \
670 "setenv loadaddr 0x1000000;" \
671 "bootm $loadaddr $ramdiskaddr $fdtaddr"
673 #define CONFIG_NFSBOOTCOMMAND \
674 "setenv bootargs root=/dev/nfs rw " \
675 "nfsroot=$serverip:$rootpath " \
676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "tftp $loadaddr $bootfile;" \
679 "tftp $fdtaddr $fdtfile;" \
680 "bootm $loadaddr - $fdtaddr"
682 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
684 #include <asm/fsl_secure_boot.h>
686 #endif /* __T1024RDB_H */