include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 RDB board configuration file
   8  */
   9
  10 #ifndef __T1024RDB_H
  11 #define __T1024RDB_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 /* support deep sleep */
  28 #ifdef CONFIG_ARCH_T1024
  29 #define CONFIG_DEEP_SLEEP
  30 #endif
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  36 #define CONFIG_SPL_PAD_TO               0x40000
  37 #define CONFIG_SPL_MAX_SIZE             0x28000
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #ifdef CONFIG_NAND
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  52 #if defined(CONFIG_TARGET_T1024RDB)
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  54 #elif defined(CONFIG_TARGET_T1023RDB)
  55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  56 #endif
  57 #define CONFIG_SPL_NAND_BOOT
  58 #endif
  59
  60 #ifdef CONFIG_SPIFLASH
  61 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  62 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  67 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  68 #ifndef CONFIG_SPL_BUILD
  69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  70 #endif
  71 #if defined(CONFIG_TARGET_T1024RDB)
  72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  73 #elif defined(CONFIG_TARGET_T1023RDB)
  74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  75 #endif
  76 #define CONFIG_SPL_SPI_BOOT
  77 #endif
  78
  79 #ifdef CONFIG_SDCARD
  80 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  81 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  82 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  83 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  84 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  85 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  86 #ifndef CONFIG_SPL_BUILD
  87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  88 #endif
  89 #if defined(CONFIG_TARGET_T1024RDB)
  90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  91 #elif defined(CONFIG_TARGET_T1023RDB)
  92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  93 #endif
  94 #define CONFIG_SPL_MMC_BOOT
  95 #endif
  96
  97 #endif /* CONFIG_RAMBOOT_PBL */
  98
  99 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 100 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 101 #endif
 102
 103 /* PCIe Boot - Master */
 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 105 /*
 106  * for slave u-boot IMAGE instored in master memory space,
 107  * PHYS must be aligned based on the SIZE
 108  */
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 111 #ifdef CONFIG_PHYS_64BIT
 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 114 #else
 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 117 #endif
 118 /*
 119  * for slave UCODE and ENV instored in master memory space,
 120  * PHYS must be aligned based on the SIZE
 121  */
 122 #ifdef CONFIG_PHYS_64BIT
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 125 #else
 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 128 #endif
 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 130 /* slave core release by master*/
 131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 133
 134 /* PCIe Boot - Slave */
 135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 138                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 139 /* Set 1M boot space for PCIe boot */
 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 142                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 144 #endif
 145
 146 #if defined(CONFIG_SPIFLASH)
 147 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 148 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 149 #if defined(CONFIG_TARGET_T1024RDB)
 150 #define CONFIG_ENV_SECT_SIZE            0x10000
 151 #elif defined(CONFIG_TARGET_T1023RDB)
 152 #define CONFIG_ENV_SECT_SIZE            0x40000
 153 #endif
 154 #elif defined(CONFIG_SDCARD)
 155 #define CONFIG_SYS_MMC_ENV_DEV          0
 156 #define CONFIG_ENV_SIZE                 0x2000
 157 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 158 #elif defined(CONFIG_NAND)
 159 #define CONFIG_ENV_SIZE                 0x2000
 160 #if defined(CONFIG_TARGET_T1024RDB)
 161 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 162 #elif defined(CONFIG_TARGET_T1023RDB)
 163 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 164 #endif
 165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 166 #define CONFIG_ENV_ADDR         0xffe20000
 167 #define CONFIG_ENV_SIZE         0x2000
 168 #elif defined(CONFIG_ENV_IS_NOWHERE)
 169 #define CONFIG_ENV_SIZE         0x2000
 170 #else
 171 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 172 #define CONFIG_ENV_SIZE         0x2000
 173 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 174 #endif
 175
 176 #ifndef __ASSEMBLY__
 177 unsigned long get_board_sys_clk(void);
 178 unsigned long get_board_ddr_clk(void);
 179 #endif
 180
 181 #define CONFIG_SYS_CLK_FREQ     100000000
 182 #define CONFIG_DDR_CLK_FREQ     100000000
 183
 184 /*
 185  * These can be toggled for performance analysis, otherwise use default.
 186  */
 187 #define CONFIG_SYS_CACHE_STASHING
 188 #define CONFIG_BACKSIDE_L2_CACHE
 189 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 190 #define CONFIG_BTB                      /* toggle branch predition */
 191 #define CONFIG_DDR_ECC
 192 #ifdef CONFIG_DDR_ECC
 193 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 194 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 195 #endif
 196
 197 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 198 #define CONFIG_SYS_MEMTEST_END          0x00400000
 199
 200 /*
 201  *  Config the L3 Cache as L3 SRAM
 202  */
 203 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 204 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 205 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 206 #ifdef CONFIG_RAMBOOT_PBL
 207 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 208 #endif
 209 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 210 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 211 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 212
 213 #ifdef CONFIG_PHYS_64BIT
 214 #define CONFIG_SYS_DCSRBAR              0xf0000000
 215 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 216 #endif
 217
 218 /* EEPROM */
 219 #define CONFIG_ID_EEPROM
 220 #define CONFIG_SYS_I2C_EEPROM_NXID
 221 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 222 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 226
 227 /*
 228  * DDR Setup
 229  */
 230 #define CONFIG_VERY_BIG_RAM
 231 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 232 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 233 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 234 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 235 #if defined(CONFIG_TARGET_T1024RDB)
 236 #define CONFIG_DDR_SPD
 237 #define CONFIG_SYS_SPD_BUS_NUM  0
 238 #define SPD_EEPROM_ADDRESS      0x51
 239 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 240 #elif defined(CONFIG_TARGET_T1023RDB)
 241 #define CONFIG_SYS_DDR_RAW_TIMING
 242 #define CONFIG_SYS_SDRAM_SIZE   2048
 243 #endif
 244
 245 /*
 246  * IFC Definitions
 247  */
 248 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 249 #ifdef CONFIG_PHYS_64BIT
 250 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 251 #else
 252 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 253 #endif
 254
 255 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 256 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 257                                 CSPR_PORT_SIZE_16 | \
 258                                 CSPR_MSEL_NOR | \
 259                                 CSPR_V)
 260 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 261
 262 /* NOR Flash Timing Params */
 263 #if defined(CONFIG_TARGET_T1024RDB)
 264 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 265 #elif defined(CONFIG_TARGET_T1023RDB)
 266 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 267                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 268 #endif
 269 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 270                                 FTIM0_NOR_TEADC(0x5) | \
 271                                 FTIM0_NOR_TEAHC(0x5))
 272 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 273                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 274                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 275 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 276                                 FTIM2_NOR_TCH(0x4) | \
 277                                 FTIM2_NOR_TWPH(0x0E) | \
 278                                 FTIM2_NOR_TWP(0x1c))
 279 #define CONFIG_SYS_NOR_FTIM3    0x0
 280
 281 #define CONFIG_SYS_FLASH_QUIET_TEST
 282 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 283
 284 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 285 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 286 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 287 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 288
 289 #define CONFIG_SYS_FLASH_EMPTY_INFO
 290 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 291
 292 #ifdef CONFIG_TARGET_T1024RDB
 293 /* CPLD on IFC */
 294 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 295 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 296 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 297 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 298                                                 | CSPR_PORT_SIZE_8 \
 299                                                 | CSPR_MSEL_GPCM \
 300                                                 | CSPR_V)
 301 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 302 #define CONFIG_SYS_CSOR2                0x0
 303
 304 /* CPLD Timing parameters for IFC CS2 */
 305 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 306                                                 FTIM0_GPCM_TEADC(0x0e) | \
 307                                                 FTIM0_GPCM_TEAHC(0x0e))
 308 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 309                                                 FTIM1_GPCM_TRAD(0x1f))
 310 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 311                                                 FTIM2_GPCM_TCH(0x8) | \
 312                                                 FTIM2_GPCM_TWP(0x1f))
 313 #define CONFIG_SYS_CS2_FTIM3            0x0
 314 #endif
 315
 316 /* NAND Flash on IFC */
 317 #define CONFIG_NAND_FSL_IFC
 318 #define CONFIG_SYS_NAND_BASE            0xff800000
 319 #ifdef CONFIG_PHYS_64BIT
 320 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 321 #else
 322 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 323 #endif
 324 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 325 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 326                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 327                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 328                                 | CSPR_V)
 329 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 330
 331 #if defined(CONFIG_TARGET_T1024RDB)
 332 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 333                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 334                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 335                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 336                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 337                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 338                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 339 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 340 #elif defined(CONFIG_TARGET_T1023RDB)
 341 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 342                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 343                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 344                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 345                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 346                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 347                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 348 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 349 #endif
 350
 351 #define CONFIG_SYS_NAND_ONFI_DETECTION
 352 /* ONFI NAND Flash mode0 Timing Params */
 353 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 354                                         FTIM0_NAND_TWP(0x18)   | \
 355                                         FTIM0_NAND_TWCHT(0x07) | \
 356                                         FTIM0_NAND_TWH(0x0a))
 357 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 358                                         FTIM1_NAND_TWBE(0x39)  | \
 359                                         FTIM1_NAND_TRR(0x0e)   | \
 360                                         FTIM1_NAND_TRP(0x18))
 361 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 362                                         FTIM2_NAND_TREH(0x0a) | \
 363                                         FTIM2_NAND_TWHRE(0x1e))
 364 #define CONFIG_SYS_NAND_FTIM3           0x0
 365
 366 #define CONFIG_SYS_NAND_DDR_LAW         11
 367 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 368 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 369
 370 #if defined(CONFIG_NAND)
 371 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 372 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 373 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 374 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 375 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 376 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 377 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 378 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 379 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 380 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 381 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 382 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 383 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 384 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 385 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 386 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 387 #else
 388 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 389 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 390 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 391 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 392 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 393 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 394 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 395 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 396 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 397 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 398 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 399 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 400 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 401 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 402 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 403 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 404 #endif
 405
 406 #ifdef CONFIG_SPL_BUILD
 407 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 408 #else
 409 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 410 #endif
 411
 412 #if defined(CONFIG_RAMBOOT_PBL)
 413 #define CONFIG_SYS_RAMBOOT
 414 #endif
 415
 416 #define CONFIG_HWCONFIG
 417
 418 /* define to use L1 as initial stack */
 419 #define CONFIG_L1_INIT_RAM
 420 #define CONFIG_SYS_INIT_RAM_LOCK
 421 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 425 /* The assembler doesn't like typecast */
 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 427         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 428           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 429 #else
 430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 433 #endif
 434 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 435
 436 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 437                                         GENERATED_GBL_DATA_SIZE)
 438 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 439
 440 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 441 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 442
 443 /* Serial Port */
 444 #define CONFIG_SYS_NS16550_SERIAL
 445 #define CONFIG_SYS_NS16550_REG_SIZE     1
 446 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 447
 448 #define CONFIG_SYS_BAUDRATE_TABLE       \
 449         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 450
 451 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 452 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 453 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 454 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 455
 456 /* Video */
 457 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 458 #ifdef CONFIG_FSL_DIU_FB
 459 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 460 #define CONFIG_VIDEO_LOGO
 461 #define CONFIG_VIDEO_BMP_LOGO
 462 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 463 /*
 464  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 465  * disable empty flash sector detection, which is I/O-intensive.
 466  */
 467 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 468 #endif
 469
 470 /* I2C */
 471 #define CONFIG_SYS_I2C
 472 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 473 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 474 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 475 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 476 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 477 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 478 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 479
 480 #define I2C_PCA6408_BUS_NUM             1
 481 #define I2C_PCA6408_ADDR                0x20
 482
 483 /* I2C bus multiplexer */
 484 #define I2C_MUX_CH_DEFAULT      0x8
 485
 486 /*
 487  * RTC configuration
 488  */
 489 #define RTC
 490 #define CONFIG_RTC_DS1337       1
 491 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 492
 493 /*
 494  * eSPI - Enhanced SPI
 495  */
 496
 497 /*
 498  * General PCIe
 499  * Memory space is mapped 1-1, but I/O space must start from 0.
 500  */
 501 #define CONFIG_PCIE1            /* PCIE controller 1 */
 502 #define CONFIG_PCIE2            /* PCIE controller 2 */
 503 #define CONFIG_PCIE3            /* PCIE controller 3 */
 504 #ifdef CONFIG_ARCH_T1040
 505 #define CONFIG_PCIE4            /* PCIE controller 4 */
 506 #endif
 507 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 508 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 509 #define CONFIG_PCI_INDIRECT_BRIDGE
 510
 511 #ifdef CONFIG_PCI
 512 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 513 #ifdef CONFIG_PCIE1
 514 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 515 #ifdef CONFIG_PHYS_64BIT
 516 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 517 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 518 #else
 519 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 520 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 521 #endif
 522 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 523 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 524 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 525 #ifdef CONFIG_PHYS_64BIT
 526 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 527 #else
 528 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 529 #endif
 530 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 531 #endif
 532
 533 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 534 #ifdef CONFIG_PCIE2
 535 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 536 #ifdef CONFIG_PHYS_64BIT
 537 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 538 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 539 #else
 540 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 541 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 542 #endif
 543 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 544 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 545 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 546 #ifdef CONFIG_PHYS_64BIT
 547 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 548 #else
 549 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 550 #endif
 551 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 552 #endif
 553
 554 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 555 #ifdef CONFIG_PCIE3
 556 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 557 #ifdef CONFIG_PHYS_64BIT
 558 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 559 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 560 #else
 561 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 562 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 563 #endif
 564 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 565 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 566 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 567 #ifdef CONFIG_PHYS_64BIT
 568 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 569 #else
 570 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 571 #endif
 572 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 573 #endif
 574
 575 /* controller 4, Base address 203000, to be removed */
 576 #ifdef CONFIG_PCIE4
 577 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 578 #ifdef CONFIG_PHYS_64BIT
 579 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 580 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 581 #else
 582 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 583 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 584 #endif
 585 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 586 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 587 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 588 #ifdef CONFIG_PHYS_64BIT
 589 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 590 #else
 591 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 592 #endif
 593 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 594 #endif
 595
 596 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 597 #endif  /* CONFIG_PCI */
 598
 599 /*
 600  * USB
 601  */
 602 #define CONFIG_HAS_FSL_DR_USB
 603
 604 #ifdef CONFIG_HAS_FSL_DR_USB
 605 #define CONFIG_USB_EHCI_FSL
 606 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 607 #endif
 608
 609 /*
 610  * SDHC
 611  */
 612 #ifdef CONFIG_MMC
 613 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 614 #endif
 615
 616 /* Qman/Bman */
 617 #ifndef CONFIG_NOBQFMAN
 618 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 619 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 620 #ifdef CONFIG_PHYS_64BIT
 621 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 622 #else
 623 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 624 #endif
 625 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 626 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 627 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 628 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 629 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 630 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 631                                         CONFIG_SYS_BMAN_CENA_SIZE)
 632 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 633 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 634 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 635 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 636 #ifdef CONFIG_PHYS_64BIT
 637 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 638 #else
 639 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 640 #endif
 641 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 642 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 643 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 644 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 645 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 646 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 647                                         CONFIG_SYS_QMAN_CENA_SIZE)
 648 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 649 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 650
 651 #define CONFIG_SYS_DPAA_FMAN
 652
 653 #ifdef CONFIG_TARGET_T1024RDB
 654 #define CONFIG_QE
 655 #endif
 656 /* Default address of microcode for the Linux FMan driver */
 657 #if defined(CONFIG_SPIFLASH)
 658 /*
 659  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 660  * env, so we got 0x110000.
 661  */
 662 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 663 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 664 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 665 #elif defined(CONFIG_SDCARD)
 666 /*
 667  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 668  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 669  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 670  */
 671 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 672 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 673 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 674 #elif defined(CONFIG_NAND)
 675 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 676 #if defined(CONFIG_TARGET_T1024RDB)
 677 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 678 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 679 #elif defined(CONFIG_TARGET_T1023RDB)
 680 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 681 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 682 #endif
 683 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 684 /*
 685  * Slave has no ucode locally, it can fetch this from remote. When implementing
 686  * in two corenet boards, slave's ucode could be stored in master's memory
 687  * space, the address can be mapped from slave TLB->slave LAW->
 688  * slave SRIO or PCIE outbound window->master inbound window->
 689  * master LAW->the ucode address in master's memory space.
 690  */
 691 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 692 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 693 #else
 694 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 695 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 696 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 697 #endif
 698 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 699 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 700 #endif /* CONFIG_NOBQFMAN */
 701
 702 #ifdef CONFIG_SYS_DPAA_FMAN
 703 #define CONFIG_FMAN_ENET
 704 #define CONFIG_PHY_REALTEK
 705 #if defined(CONFIG_TARGET_T1024RDB)
 706 #define RGMII_PHY1_ADDR         0x2
 707 #define RGMII_PHY2_ADDR         0x6
 708 #define SGMII_AQR_PHY_ADDR      0x2
 709 #define FM1_10GEC1_PHY_ADDR     0x1
 710 #elif defined(CONFIG_TARGET_T1023RDB)
 711 #define RGMII_PHY1_ADDR         0x1
 712 #define SGMII_RTK_PHY_ADDR      0x3
 713 #define SGMII_AQR_PHY_ADDR      0x2
 714 #endif
 715 #endif
 716
 717 #ifdef CONFIG_FMAN_ENET
 718 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 719 #endif
 720
 721 /*
 722  * Dynamic MTD Partition support with mtdparts
 723  */
 724
 725 /*
 726  * Environment
 727  */
 728 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 729 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 730
 731 /*
 732  * Miscellaneous configurable options
 733  */
 734 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 735
 736 /*
 737  * For booting Linux, the board info and command line data
 738  * have to be in the first 64 MB of memory, since this is
 739  * the maximum mapped by the Linux kernel during initialization.
 740  */
 741 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 742 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 743
 744 #ifdef CONFIG_CMD_KGDB
 745 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 746 #endif
 747
 748 /*
 749  * Environment Configuration
 750  */
 751 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 752 #define CONFIG_BOOTFILE         "uImage"
 753 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 754 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 755 #define __USB_PHY_TYPE          utmi
 756
 757 #ifdef CONFIG_ARCH_T1024
 758 #define CONFIG_BOARDNAME t1024rdb
 759 #define BANK_INTLV cs0_cs1
 760 #else
 761 #define CONFIG_BOARDNAME t1023rdb
 762 #define BANK_INTLV  null
 763 #endif
 764
 765 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 766         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 767         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 768         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 769         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 770         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 771         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 772         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 773         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 774         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 775         "netdev=eth0\0"                                         \
 776         "tftpflash=tftpboot $loadaddr $uboot && "               \
 777         "protect off $ubootaddr +$filesize && "                 \
 778         "erase $ubootaddr +$filesize && "                       \
 779         "cp.b $loadaddr $ubootaddr $filesize && "               \
 780         "protect on $ubootaddr +$filesize && "                  \
 781         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 782         "consoledev=ttyS0\0"                                    \
 783         "ramdiskaddr=2000000\0"                                 \
 784         "fdtaddr=1e00000\0"                                     \
 785         "bdev=sda3\0"
 786
 787 #define CONFIG_LINUX                                    \
 788         "setenv bootargs root=/dev/ram rw "             \
 789         "console=$consoledev,$baudrate $othbootargs;"   \
 790         "setenv ramdiskaddr 0x02000000;"                \
 791         "setenv fdtaddr 0x00c00000;"                    \
 792         "setenv loadaddr 0x1000000;"                    \
 793         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 794
 795 #define CONFIG_NFSBOOTCOMMAND                   \
 796         "setenv bootargs root=/dev/nfs rw "     \
 797         "nfsroot=$serverip:$rootpath "          \
 798         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 799         "console=$consoledev,$baudrate $othbootargs;"   \
 800         "tftp $loadaddr $bootfile;"             \
 801         "tftp $fdtaddr $fdtfile;"               \
 802         "bootm $loadaddr - $fdtaddr"
 803
 804 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 805
 806 #include <asm/fsl_secure_boot.h>
 807
 808 #endif  /* __T1024RDB_H */