include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 /* support deep sleep */
  30 #ifdef CONFIG_ARCH_T1024
  31 #define CONFIG_DEEP_SLEEP
  32 #endif
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  36 #define CONFIG_SPL_FLUSH_IMAGE
  37 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  38 #define CONFIG_SYS_TEXT_BASE            0x30001000
  39 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  40 #define CONFIG_SPL_PAD_TO               0x40000
  41 #define CONFIG_SPL_MAX_SIZE             0x28000
  42 #define RESET_VECTOR_OFFSET             0x27FFC
  43 #define BOOT_PAGE_OFFSET                0x27000
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #ifdef CONFIG_NAND
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  56 #if defined(CONFIG_TARGET_T1024RDB)
  57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  58 #elif defined(CONFIG_TARGET_T1023RDB)
  59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  60 #endif
  61 #define CONFIG_SPL_NAND_BOOT
  62 #endif
  63
  64 #ifdef CONFIG_SPIFLASH
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  71 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  72 #ifndef CONFIG_SPL_BUILD
  73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  74 #endif
  75 #if defined(CONFIG_TARGET_T1024RDB)
  76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  77 #elif defined(CONFIG_TARGET_T1023RDB)
  78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  79 #endif
  80 #define CONFIG_SPL_SPI_BOOT
  81 #endif
  82
  83 #ifdef CONFIG_SDCARD
  84 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  85 #define CONFIG_SPL_MMC_MINIMAL
  86 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  87 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  88 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  89 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  90 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  91 #ifndef CONFIG_SPL_BUILD
  92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  93 #endif
  94 #if defined(CONFIG_TARGET_T1024RDB)
  95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  96 #elif defined(CONFIG_TARGET_T1023RDB)
  97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  98 #endif
  99 #define CONFIG_SPL_MMC_BOOT
 100 #endif
 101
 102 #endif /* CONFIG_RAMBOOT_PBL */
 103
 104 #ifndef CONFIG_SYS_TEXT_BASE
 105 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 106 #endif
 107
 108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 109 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 110 #endif
 111
 112 #ifdef CONFIG_MTD_NOR_FLASH
 113 #define CONFIG_FLASH_CFI_DRIVER
 114 #define CONFIG_SYS_FLASH_CFI
 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 116 #endif
 117
 118 /* PCIe Boot - Master */
 119 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 120 /*
 121  * for slave u-boot IMAGE instored in master memory space,
 122  * PHYS must be aligned based on the SIZE
 123  */
 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 129 #else
 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 132 #endif
 133 /*
 134  * for slave UCODE and ENV instored in master memory space,
 135  * PHYS must be aligned based on the SIZE
 136  */
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 140 #else
 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 143 #endif
 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 145 /* slave core release by master*/
 146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 148
 149 /* PCIe Boot - Slave */
 150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 153                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 154 /* Set 1M boot space for PCIe boot */
 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 157                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 159 #endif
 160
 161 #if defined(CONFIG_SPIFLASH)
 162 #define CONFIG_SYS_EXTRA_ENV_RELOC
 163 #define CONFIG_ENV_SPI_BUS              0
 164 #define CONFIG_ENV_SPI_CS               0
 165 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 166 #define CONFIG_ENV_SPI_MODE             0
 167 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 168 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 169 #if defined(CONFIG_TARGET_T1024RDB)
 170 #define CONFIG_ENV_SECT_SIZE            0x10000
 171 #elif defined(CONFIG_TARGET_T1023RDB)
 172 #define CONFIG_ENV_SECT_SIZE            0x40000
 173 #endif
 174 #elif defined(CONFIG_SDCARD)
 175 #define CONFIG_SYS_EXTRA_ENV_RELOC
 176 #define CONFIG_SYS_MMC_ENV_DEV          0
 177 #define CONFIG_ENV_SIZE                 0x2000
 178 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 179 #elif defined(CONFIG_NAND)
 180 #define CONFIG_SYS_EXTRA_ENV_RELOC
 181 #define CONFIG_ENV_SIZE                 0x2000
 182 #if defined(CONFIG_TARGET_T1024RDB)
 183 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 184 #elif defined(CONFIG_TARGET_T1023RDB)
 185 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 186 #endif
 187 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 188 #define CONFIG_ENV_ADDR         0xffe20000
 189 #define CONFIG_ENV_SIZE         0x2000
 190 #elif defined(CONFIG_ENV_IS_NOWHERE)
 191 #define CONFIG_ENV_SIZE         0x2000
 192 #else
 193 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 194 #define CONFIG_ENV_SIZE         0x2000
 195 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 196 #endif
 197
 198 #ifndef __ASSEMBLY__
 199 unsigned long get_board_sys_clk(void);
 200 unsigned long get_board_ddr_clk(void);
 201 #endif
 202
 203 #define CONFIG_SYS_CLK_FREQ     100000000
 204 #define CONFIG_DDR_CLK_FREQ     100000000
 205
 206 /*
 207  * These can be toggled for performance analysis, otherwise use default.
 208  */
 209 #define CONFIG_SYS_CACHE_STASHING
 210 #define CONFIG_BACKSIDE_L2_CACHE
 211 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 212 #define CONFIG_BTB                      /* toggle branch predition */
 213 #define CONFIG_DDR_ECC
 214 #ifdef CONFIG_DDR_ECC
 215 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 216 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 217 #endif
 218
 219 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 220 #define CONFIG_SYS_MEMTEST_END          0x00400000
 221 #define CONFIG_SYS_ALT_MEMTEST
 222 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 223
 224 /*
 225  *  Config the L3 Cache as L3 SRAM
 226  */
 227 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 228 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 229 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 230 #ifdef CONFIG_RAMBOOT_PBL
 231 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 232 #endif
 233 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 234 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 235 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 236 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 237
 238 #ifdef CONFIG_PHYS_64BIT
 239 #define CONFIG_SYS_DCSRBAR              0xf0000000
 240 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 241 #endif
 242
 243 /* EEPROM */
 244 #define CONFIG_ID_EEPROM
 245 #define CONFIG_SYS_I2C_EEPROM_NXID
 246 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 247 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 251
 252 /*
 253  * DDR Setup
 254  */
 255 #define CONFIG_VERY_BIG_RAM
 256 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 257 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 258 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 259 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 260 #define CONFIG_FSL_DDR_INTERACTIVE
 261 #if defined(CONFIG_TARGET_T1024RDB)
 262 #define CONFIG_DDR_SPD
 263 #define CONFIG_SYS_SPD_BUS_NUM  0
 264 #define SPD_EEPROM_ADDRESS      0x51
 265 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 266 #elif defined(CONFIG_TARGET_T1023RDB)
 267 #define CONFIG_SYS_DDR_RAW_TIMING
 268 #define CONFIG_SYS_SDRAM_SIZE   2048
 269 #endif
 270
 271 /*
 272  * IFC Definitions
 273  */
 274 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 275 #ifdef CONFIG_PHYS_64BIT
 276 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 277 #else
 278 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 279 #endif
 280
 281 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 282 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 283                                 CSPR_PORT_SIZE_16 | \
 284                                 CSPR_MSEL_NOR | \
 285                                 CSPR_V)
 286 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 287
 288 /* NOR Flash Timing Params */
 289 #if defined(CONFIG_TARGET_T1024RDB)
 290 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 291 #elif defined(CONFIG_TARGET_T1023RDB)
 292 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 293                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 294 #endif
 295 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 296                                 FTIM0_NOR_TEADC(0x5) | \
 297                                 FTIM0_NOR_TEAHC(0x5))
 298 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 299                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 300                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 301 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 302                                 FTIM2_NOR_TCH(0x4) | \
 303                                 FTIM2_NOR_TWPH(0x0E) | \
 304                                 FTIM2_NOR_TWP(0x1c))
 305 #define CONFIG_SYS_NOR_FTIM3    0x0
 306
 307 #define CONFIG_SYS_FLASH_QUIET_TEST
 308 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 309
 310 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 311 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 312 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 313 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 314
 315 #define CONFIG_SYS_FLASH_EMPTY_INFO
 316 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 317
 318 #ifdef CONFIG_TARGET_T1024RDB
 319 /* CPLD on IFC */
 320 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 321 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 322 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 323 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 324                                                 | CSPR_PORT_SIZE_8 \
 325                                                 | CSPR_MSEL_GPCM \
 326                                                 | CSPR_V)
 327 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 328 #define CONFIG_SYS_CSOR2                0x0
 329
 330 /* CPLD Timing parameters for IFC CS2 */
 331 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 332                                                 FTIM0_GPCM_TEADC(0x0e) | \
 333                                                 FTIM0_GPCM_TEAHC(0x0e))
 334 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 335                                                 FTIM1_GPCM_TRAD(0x1f))
 336 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 337                                                 FTIM2_GPCM_TCH(0x8) | \
 338                                                 FTIM2_GPCM_TWP(0x1f))
 339 #define CONFIG_SYS_CS2_FTIM3            0x0
 340 #endif
 341
 342 /* NAND Flash on IFC */
 343 #define CONFIG_NAND_FSL_IFC
 344 #define CONFIG_SYS_NAND_BASE            0xff800000
 345 #ifdef CONFIG_PHYS_64BIT
 346 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 347 #else
 348 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 349 #endif
 350 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 351 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 352                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 353                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 354                                 | CSPR_V)
 355 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 356
 357 #if defined(CONFIG_TARGET_T1024RDB)
 358 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 359                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 360                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 361                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 362                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 363                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 364                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 365 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 366 #elif defined(CONFIG_TARGET_T1023RDB)
 367 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 368                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 369                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 370                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 371                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 372                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 373                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 374 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 375 #endif
 376
 377 #define CONFIG_SYS_NAND_ONFI_DETECTION
 378 /* ONFI NAND Flash mode0 Timing Params */
 379 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 380                                         FTIM0_NAND_TWP(0x18)   | \
 381                                         FTIM0_NAND_TWCHT(0x07) | \
 382                                         FTIM0_NAND_TWH(0x0a))
 383 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 384                                         FTIM1_NAND_TWBE(0x39)  | \
 385                                         FTIM1_NAND_TRR(0x0e)   | \
 386                                         FTIM1_NAND_TRP(0x18))
 387 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 388                                         FTIM2_NAND_TREH(0x0a) | \
 389                                         FTIM2_NAND_TWHRE(0x1e))
 390 #define CONFIG_SYS_NAND_FTIM3           0x0
 391
 392 #define CONFIG_SYS_NAND_DDR_LAW         11
 393 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 394 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 395 #define CONFIG_CMD_NAND
 396
 397 #if defined(CONFIG_NAND)
 398 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 399 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 400 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 401 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 402 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 403 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 404 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 405 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 406 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 407 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 408 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 409 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 410 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 411 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 412 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 413 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 414 #else
 415 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 416 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 417 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 418 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 419 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 420 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 421 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 422 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 423 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 424 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 425 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 426 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 427 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 428 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 429 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 430 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 431 #endif
 432
 433 #ifdef CONFIG_SPL_BUILD
 434 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 435 #else
 436 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 437 #endif
 438
 439 #if defined(CONFIG_RAMBOOT_PBL)
 440 #define CONFIG_SYS_RAMBOOT
 441 #endif
 442
 443 #define CONFIG_BOARD_EARLY_INIT_R
 444 #define CONFIG_MISC_INIT_R
 445
 446 #define CONFIG_HWCONFIG
 447
 448 /* define to use L1 as initial stack */
 449 #define CONFIG_L1_INIT_RAM
 450 #define CONFIG_SYS_INIT_RAM_LOCK
 451 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 455 /* The assembler doesn't like typecast */
 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 457         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 458           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 459 #else
 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 463 #endif
 464 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 465
 466 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 467                                         GENERATED_GBL_DATA_SIZE)
 468 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 469
 470 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 471 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 472
 473 /* Serial Port */
 474 #define CONFIG_CONS_INDEX       1
 475 #define CONFIG_SYS_NS16550_SERIAL
 476 #define CONFIG_SYS_NS16550_REG_SIZE     1
 477 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 478
 479 #define CONFIG_SYS_BAUDRATE_TABLE       \
 480         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 481
 482 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 483 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 484 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 485 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 486
 487 /* Video */
 488 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 489 #ifdef CONFIG_FSL_DIU_FB
 490 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 491 #define CONFIG_VIDEO_LOGO
 492 #define CONFIG_VIDEO_BMP_LOGO
 493 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 494 /*
 495  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 496  * disable empty flash sector detection, which is I/O-intensive.
 497  */
 498 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 499 #endif
 500
 501 /* I2C */
 502 #define CONFIG_SYS_I2C
 503 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 504 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 505 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 506 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 507 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 508 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 509 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 510
 511 #define I2C_PCA6408_BUS_NUM             1
 512 #define I2C_PCA6408_ADDR                0x20
 513
 514 /* I2C bus multiplexer */
 515 #define I2C_MUX_CH_DEFAULT      0x8
 516
 517 /*
 518  * RTC configuration
 519  */
 520 #define RTC
 521 #define CONFIG_RTC_DS1337       1
 522 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 523
 524 /*
 525  * eSPI - Enhanced SPI
 526  */
 527 #define CONFIG_SPI_FLASH_BAR
 528 #define CONFIG_SF_DEFAULT_SPEED 10000000
 529 #define CONFIG_SF_DEFAULT_MODE  0
 530
 531 /*
 532  * General PCIe
 533  * Memory space is mapped 1-1, but I/O space must start from 0.
 534  */
 535 #define CONFIG_PCIE1            /* PCIE controller 1 */
 536 #define CONFIG_PCIE2            /* PCIE controller 2 */
 537 #define CONFIG_PCIE3            /* PCIE controller 3 */
 538 #ifdef CONFIG_ARCH_T1040
 539 #define CONFIG_PCIE4            /* PCIE controller 4 */
 540 #endif
 541 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 542 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 543 #define CONFIG_PCI_INDIRECT_BRIDGE
 544
 545 #ifdef CONFIG_PCI
 546 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 547 #ifdef CONFIG_PCIE1
 548 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 549 #ifdef CONFIG_PHYS_64BIT
 550 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 551 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 552 #else
 553 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 554 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 555 #endif
 556 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 557 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 558 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 559 #ifdef CONFIG_PHYS_64BIT
 560 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 561 #else
 562 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 563 #endif
 564 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 565 #endif
 566
 567 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 568 #ifdef CONFIG_PCIE2
 569 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 570 #ifdef CONFIG_PHYS_64BIT
 571 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 572 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 573 #else
 574 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 575 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 576 #endif
 577 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 578 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 579 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 580 #ifdef CONFIG_PHYS_64BIT
 581 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 582 #else
 583 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 584 #endif
 585 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 586 #endif
 587
 588 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 589 #ifdef CONFIG_PCIE3
 590 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 591 #ifdef CONFIG_PHYS_64BIT
 592 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 593 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 594 #else
 595 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 596 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 597 #endif
 598 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 599 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 600 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 601 #ifdef CONFIG_PHYS_64BIT
 602 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 603 #else
 604 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 605 #endif
 606 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 607 #endif
 608
 609 /* controller 4, Base address 203000, to be removed */
 610 #ifdef CONFIG_PCIE4
 611 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 612 #ifdef CONFIG_PHYS_64BIT
 613 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 614 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 615 #else
 616 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 617 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 618 #endif
 619 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 620 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 621 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 622 #ifdef CONFIG_PHYS_64BIT
 623 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 624 #else
 625 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 626 #endif
 627 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 628 #endif
 629
 630 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 631 #endif  /* CONFIG_PCI */
 632
 633 /*
 634  * USB
 635  */
 636 #define CONFIG_HAS_FSL_DR_USB
 637
 638 #ifdef CONFIG_HAS_FSL_DR_USB
 639 #define CONFIG_USB_EHCI_FSL
 640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 641 #endif
 642
 643 /*
 644  * SDHC
 645  */
 646 #ifdef CONFIG_MMC
 647 #define CONFIG_FSL_ESDHC
 648 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 649 #endif
 650
 651 /* Qman/Bman */
 652 #ifndef CONFIG_NOBQFMAN
 653 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 654 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 655 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 656 #ifdef CONFIG_PHYS_64BIT
 657 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 658 #else
 659 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 660 #endif
 661 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 662 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 663 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 664 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 665 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 666 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 667                                         CONFIG_SYS_BMAN_CENA_SIZE)
 668 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 669 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 670 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 671 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 672 #ifdef CONFIG_PHYS_64BIT
 673 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 674 #else
 675 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 676 #endif
 677 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 678 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 679 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 680 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 681 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 682 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 683                                         CONFIG_SYS_QMAN_CENA_SIZE)
 684 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 685 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 686
 687 #define CONFIG_SYS_DPAA_FMAN
 688
 689 #ifdef CONFIG_TARGET_T1024RDB
 690 #define CONFIG_QE
 691 #define CONFIG_U_QE
 692 #endif
 693 /* Default address of microcode for the Linux FMan driver */
 694 #if defined(CONFIG_SPIFLASH)
 695 /*
 696  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 697  * env, so we got 0x110000.
 698  */
 699 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 700 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 701 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 702 #elif defined(CONFIG_SDCARD)
 703 /*
 704  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 705  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 706  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 707  */
 708 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 709 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 710 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 711 #elif defined(CONFIG_NAND)
 712 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 713 #if defined(CONFIG_TARGET_T1024RDB)
 714 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 715 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 716 #elif defined(CONFIG_TARGET_T1023RDB)
 717 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 718 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 719 #endif
 720 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 721 /*
 722  * Slave has no ucode locally, it can fetch this from remote. When implementing
 723  * in two corenet boards, slave's ucode could be stored in master's memory
 724  * space, the address can be mapped from slave TLB->slave LAW->
 725  * slave SRIO or PCIE outbound window->master inbound window->
 726  * master LAW->the ucode address in master's memory space.
 727  */
 728 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 729 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 730 #else
 731 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 732 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 733 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 734 #endif
 735 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 736 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 737 #endif /* CONFIG_NOBQFMAN */
 738
 739 #ifdef CONFIG_SYS_DPAA_FMAN
 740 #define CONFIG_FMAN_ENET
 741 #define CONFIG_PHYLIB_10G
 742 #define CONFIG_PHY_REALTEK
 743 #define CONFIG_PHY_AQUANTIA
 744 #if defined(CONFIG_TARGET_T1024RDB)
 745 #define RGMII_PHY1_ADDR         0x2
 746 #define RGMII_PHY2_ADDR         0x6
 747 #define SGMII_AQR_PHY_ADDR      0x2
 748 #define FM1_10GEC1_PHY_ADDR     0x1
 749 #elif defined(CONFIG_TARGET_T1023RDB)
 750 #define RGMII_PHY1_ADDR         0x1
 751 #define SGMII_RTK_PHY_ADDR      0x3
 752 #define SGMII_AQR_PHY_ADDR      0x2
 753 #endif
 754 #endif
 755
 756 #ifdef CONFIG_FMAN_ENET
 757 #define CONFIG_MII              /* MII PHY management */
 758 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 759 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 760 #endif
 761
 762 /*
 763  * Dynamic MTD Partition support with mtdparts
 764  */
 765 #ifdef CONFIG_MTD_NOR_FLASH
 766 #define CONFIG_MTD_DEVICE
 767 #define CONFIG_MTD_PARTITIONS
 768 #define CONFIG_FLASH_CFI_MTD
 769 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 770                         "spi0=spife110000.1"
 771 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 772                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 773                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 774                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 775 #endif
 776
 777 /*
 778  * Environment
 779  */
 780 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 781 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 782
 783 /*
 784  * Command line configuration.
 785  */
 786 #define CONFIG_CMD_REGINFO
 787
 788 #ifdef CONFIG_PCI
 789 #define CONFIG_CMD_PCI
 790 #endif
 791
 792 /*
 793  * Miscellaneous configurable options
 794  */
 795 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 796 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 797 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 798 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 799 #ifdef CONFIG_CMD_KGDB
 800 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 801 #else
 802 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 803 #endif
 804 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 805 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 806 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 807
 808 /*
 809  * For booting Linux, the board info and command line data
 810  * have to be in the first 64 MB of memory, since this is
 811  * the maximum mapped by the Linux kernel during initialization.
 812  */
 813 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 814 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 815
 816 #ifdef CONFIG_CMD_KGDB
 817 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 818 #endif
 819
 820 /*
 821  * Environment Configuration
 822  */
 823 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 824 #define CONFIG_BOOTFILE         "uImage"
 825 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 826 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 827 #define __USB_PHY_TYPE          utmi
 828
 829 #ifdef CONFIG_ARCH_T1024
 830 #define CONFIG_BOARDNAME t1024rdb
 831 #define BANK_INTLV cs0_cs1
 832 #else
 833 #define CONFIG_BOARDNAME t1023rdb
 834 #define BANK_INTLV  null
 835 #endif
 836
 837 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 838         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 839         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 840         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 841         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 842         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 843         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 844         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 845         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 846         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 847         "netdev=eth0\0"                                         \
 848         "tftpflash=tftpboot $loadaddr $uboot && "               \
 849         "protect off $ubootaddr +$filesize && "                 \
 850         "erase $ubootaddr +$filesize && "                       \
 851         "cp.b $loadaddr $ubootaddr $filesize && "               \
 852         "protect on $ubootaddr +$filesize && "                  \
 853         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 854         "consoledev=ttyS0\0"                                    \
 855         "ramdiskaddr=2000000\0"                                 \
 856         "fdtaddr=1e00000\0"                                     \
 857         "bdev=sda3\0"
 858
 859 #define CONFIG_LINUX                                    \
 860         "setenv bootargs root=/dev/ram rw "             \
 861         "console=$consoledev,$baudrate $othbootargs;"   \
 862         "setenv ramdiskaddr 0x02000000;"                \
 863         "setenv fdtaddr 0x00c00000;"                    \
 864         "setenv loadaddr 0x1000000;"                    \
 865         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 866
 867 #define CONFIG_NFSBOOTCOMMAND                   \
 868         "setenv bootargs root=/dev/nfs rw "     \
 869         "nfsroot=$serverip:$rootpath "          \
 870         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 871         "console=$consoledev,$baudrate $othbootargs;"   \
 872         "tftp $loadaddr $bootfile;"             \
 873         "tftp $fdtaddr $fdtfile;"               \
 874         "bootm $loadaddr - $fdtaddr"
 875
 876 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 877
 878 #include <asm/fsl_secure_boot.h>
 879
 880 #endif  /* __T1024RDB_H */