include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 /* support deep sleep */
  30 #ifdef CONFIG_ARCH_T1024
  31 #define CONFIG_DEEP_SLEEP
  32 #endif
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  36 #define CONFIG_SPL_FLUSH_IMAGE
  37 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  38 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  39 #define CONFIG_SPL_PAD_TO               0x40000
  40 #define CONFIG_SPL_MAX_SIZE             0x28000
  41 #define RESET_VECTOR_OFFSET             0x27FFC
  42 #define BOOT_PAGE_OFFSET                0x27000
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SPL_SKIP_RELOCATE
  45 #define CONFIG_SPL_COMMON_INIT_DDR
  46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  47 #endif
  48
  49 #ifdef CONFIG_NAND
  50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  51 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  52 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  53 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  54 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  55 #if defined(CONFIG_TARGET_T1024RDB)
  56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  57 #elif defined(CONFIG_TARGET_T1023RDB)
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  59 #endif
  60 #define CONFIG_SPL_NAND_BOOT
  61 #endif
  62
  63 #ifdef CONFIG_SPIFLASH
  64 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  70 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #ifndef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #endif
  74 #if defined(CONFIG_TARGET_T1024RDB)
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  76 #elif defined(CONFIG_TARGET_T1023RDB)
  77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  78 #endif
  79 #define CONFIG_SPL_SPI_BOOT
  80 #endif
  81
  82 #ifdef CONFIG_SDCARD
  83 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  84 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  85 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  86 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  87 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  88 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  89 #ifndef CONFIG_SPL_BUILD
  90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  91 #endif
  92 #if defined(CONFIG_TARGET_T1024RDB)
  93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  94 #elif defined(CONFIG_TARGET_T1023RDB)
  95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  96 #endif
  97 #define CONFIG_SPL_MMC_BOOT
  98 #endif
  99
 100 #endif /* CONFIG_RAMBOOT_PBL */
 101
 102 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 103 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 104 #endif
 105
 106 #ifdef CONFIG_MTD_NOR_FLASH
 107 #define CONFIG_FLASH_CFI_DRIVER
 108 #define CONFIG_SYS_FLASH_CFI
 109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 110 #endif
 111
 112 /* PCIe Boot - Master */
 113 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 114 /*
 115  * for slave u-boot IMAGE instored in master memory space,
 116  * PHYS must be aligned based on the SIZE
 117  */
 118 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 120 #ifdef CONFIG_PHYS_64BIT
 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 123 #else
 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 126 #endif
 127 /*
 128  * for slave UCODE and ENV instored in master memory space,
 129  * PHYS must be aligned based on the SIZE
 130  */
 131 #ifdef CONFIG_PHYS_64BIT
 132 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 134 #else
 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 137 #endif
 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 139 /* slave core release by master*/
 140 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 141 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 142
 143 /* PCIe Boot - Slave */
 144 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 145 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 147                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 148 /* Set 1M boot space for PCIe boot */
 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 151                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 152 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 153 #endif
 154
 155 #if defined(CONFIG_SPIFLASH)
 156 #define CONFIG_SYS_EXTRA_ENV_RELOC
 157 #define CONFIG_ENV_SPI_BUS              0
 158 #define CONFIG_ENV_SPI_CS               0
 159 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 160 #define CONFIG_ENV_SPI_MODE             0
 161 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 162 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 163 #if defined(CONFIG_TARGET_T1024RDB)
 164 #define CONFIG_ENV_SECT_SIZE            0x10000
 165 #elif defined(CONFIG_TARGET_T1023RDB)
 166 #define CONFIG_ENV_SECT_SIZE            0x40000
 167 #endif
 168 #elif defined(CONFIG_SDCARD)
 169 #define CONFIG_SYS_EXTRA_ENV_RELOC
 170 #define CONFIG_SYS_MMC_ENV_DEV          0
 171 #define CONFIG_ENV_SIZE                 0x2000
 172 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 173 #elif defined(CONFIG_NAND)
 174 #define CONFIG_SYS_EXTRA_ENV_RELOC
 175 #define CONFIG_ENV_SIZE                 0x2000
 176 #if defined(CONFIG_TARGET_T1024RDB)
 177 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 178 #elif defined(CONFIG_TARGET_T1023RDB)
 179 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 180 #endif
 181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 182 #define CONFIG_ENV_ADDR         0xffe20000
 183 #define CONFIG_ENV_SIZE         0x2000
 184 #elif defined(CONFIG_ENV_IS_NOWHERE)
 185 #define CONFIG_ENV_SIZE         0x2000
 186 #else
 187 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 188 #define CONFIG_ENV_SIZE         0x2000
 189 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 190 #endif
 191
 192 #ifndef __ASSEMBLY__
 193 unsigned long get_board_sys_clk(void);
 194 unsigned long get_board_ddr_clk(void);
 195 #endif
 196
 197 #define CONFIG_SYS_CLK_FREQ     100000000
 198 #define CONFIG_DDR_CLK_FREQ     100000000
 199
 200 /*
 201  * These can be toggled for performance analysis, otherwise use default.
 202  */
 203 #define CONFIG_SYS_CACHE_STASHING
 204 #define CONFIG_BACKSIDE_L2_CACHE
 205 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 206 #define CONFIG_BTB                      /* toggle branch predition */
 207 #define CONFIG_DDR_ECC
 208 #ifdef CONFIG_DDR_ECC
 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 210 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 211 #endif
 212
 213 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 214 #define CONFIG_SYS_MEMTEST_END          0x00400000
 215 #define CONFIG_SYS_ALT_MEMTEST
 216
 217 /*
 218  *  Config the L3 Cache as L3 SRAM
 219  */
 220 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 221 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 222 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 223 #ifdef CONFIG_RAMBOOT_PBL
 224 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 225 #endif
 226 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 227 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 228 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 229 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 230
 231 #ifdef CONFIG_PHYS_64BIT
 232 #define CONFIG_SYS_DCSRBAR              0xf0000000
 233 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 234 #endif
 235
 236 /* EEPROM */
 237 #define CONFIG_ID_EEPROM
 238 #define CONFIG_SYS_I2C_EEPROM_NXID
 239 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 240 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 244
 245 /*
 246  * DDR Setup
 247  */
 248 #define CONFIG_VERY_BIG_RAM
 249 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 250 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 251 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 252 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 253 #define CONFIG_FSL_DDR_INTERACTIVE
 254 #if defined(CONFIG_TARGET_T1024RDB)
 255 #define CONFIG_DDR_SPD
 256 #define CONFIG_SYS_SPD_BUS_NUM  0
 257 #define SPD_EEPROM_ADDRESS      0x51
 258 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 259 #elif defined(CONFIG_TARGET_T1023RDB)
 260 #define CONFIG_SYS_DDR_RAW_TIMING
 261 #define CONFIG_SYS_SDRAM_SIZE   2048
 262 #endif
 263
 264 /*
 265  * IFC Definitions
 266  */
 267 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 268 #ifdef CONFIG_PHYS_64BIT
 269 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 270 #else
 271 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 272 #endif
 273
 274 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 275 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 276                                 CSPR_PORT_SIZE_16 | \
 277                                 CSPR_MSEL_NOR | \
 278                                 CSPR_V)
 279 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 280
 281 /* NOR Flash Timing Params */
 282 #if defined(CONFIG_TARGET_T1024RDB)
 283 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 284 #elif defined(CONFIG_TARGET_T1023RDB)
 285 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 286                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 287 #endif
 288 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 289                                 FTIM0_NOR_TEADC(0x5) | \
 290                                 FTIM0_NOR_TEAHC(0x5))
 291 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 292                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 293                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 294 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 295                                 FTIM2_NOR_TCH(0x4) | \
 296                                 FTIM2_NOR_TWPH(0x0E) | \
 297                                 FTIM2_NOR_TWP(0x1c))
 298 #define CONFIG_SYS_NOR_FTIM3    0x0
 299
 300 #define CONFIG_SYS_FLASH_QUIET_TEST
 301 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 302
 303 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 304 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 305 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 306 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 307
 308 #define CONFIG_SYS_FLASH_EMPTY_INFO
 309 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 310
 311 #ifdef CONFIG_TARGET_T1024RDB
 312 /* CPLD on IFC */
 313 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 314 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 315 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 316 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 317                                                 | CSPR_PORT_SIZE_8 \
 318                                                 | CSPR_MSEL_GPCM \
 319                                                 | CSPR_V)
 320 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 321 #define CONFIG_SYS_CSOR2                0x0
 322
 323 /* CPLD Timing parameters for IFC CS2 */
 324 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 325                                                 FTIM0_GPCM_TEADC(0x0e) | \
 326                                                 FTIM0_GPCM_TEAHC(0x0e))
 327 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 328                                                 FTIM1_GPCM_TRAD(0x1f))
 329 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 330                                                 FTIM2_GPCM_TCH(0x8) | \
 331                                                 FTIM2_GPCM_TWP(0x1f))
 332 #define CONFIG_SYS_CS2_FTIM3            0x0
 333 #endif
 334
 335 /* NAND Flash on IFC */
 336 #define CONFIG_NAND_FSL_IFC
 337 #define CONFIG_SYS_NAND_BASE            0xff800000
 338 #ifdef CONFIG_PHYS_64BIT
 339 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 340 #else
 341 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 342 #endif
 343 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 344 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 345                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 346                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 347                                 | CSPR_V)
 348 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 349
 350 #if defined(CONFIG_TARGET_T1024RDB)
 351 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 352                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 353                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 354                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 355                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 356                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 357                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 358 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 359 #elif defined(CONFIG_TARGET_T1023RDB)
 360 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 361                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 362                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 363                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 364                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 365                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 366                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 367 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 368 #endif
 369
 370 #define CONFIG_SYS_NAND_ONFI_DETECTION
 371 /* ONFI NAND Flash mode0 Timing Params */
 372 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 373                                         FTIM0_NAND_TWP(0x18)   | \
 374                                         FTIM0_NAND_TWCHT(0x07) | \
 375                                         FTIM0_NAND_TWH(0x0a))
 376 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 377                                         FTIM1_NAND_TWBE(0x39)  | \
 378                                         FTIM1_NAND_TRR(0x0e)   | \
 379                                         FTIM1_NAND_TRP(0x18))
 380 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 381                                         FTIM2_NAND_TREH(0x0a) | \
 382                                         FTIM2_NAND_TWHRE(0x1e))
 383 #define CONFIG_SYS_NAND_FTIM3           0x0
 384
 385 #define CONFIG_SYS_NAND_DDR_LAW         11
 386 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 387 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 388
 389 #if defined(CONFIG_NAND)
 390 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 391 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 392 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 393 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 394 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 395 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 396 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 397 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 398 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 399 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 400 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 401 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 402 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 403 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 404 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 405 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 406 #else
 407 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 408 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 409 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 410 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 411 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 412 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 413 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 414 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 415 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 416 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 417 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 418 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 419 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 420 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 421 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 422 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 423 #endif
 424
 425 #ifdef CONFIG_SPL_BUILD
 426 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 427 #else
 428 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 429 #endif
 430
 431 #if defined(CONFIG_RAMBOOT_PBL)
 432 #define CONFIG_SYS_RAMBOOT
 433 #endif
 434
 435 #define CONFIG_BOARD_EARLY_INIT_R
 436 #define CONFIG_MISC_INIT_R
 437
 438 #define CONFIG_HWCONFIG
 439
 440 /* define to use L1 as initial stack */
 441 #define CONFIG_L1_INIT_RAM
 442 #define CONFIG_SYS_INIT_RAM_LOCK
 443 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 444 #ifdef CONFIG_PHYS_64BIT
 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 447 /* The assembler doesn't like typecast */
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 449         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 450           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 451 #else
 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 455 #endif
 456 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 457
 458 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 459                                         GENERATED_GBL_DATA_SIZE)
 460 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 461
 462 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 463 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 464
 465 /* Serial Port */
 466 #define CONFIG_SYS_NS16550_SERIAL
 467 #define CONFIG_SYS_NS16550_REG_SIZE     1
 468 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 469
 470 #define CONFIG_SYS_BAUDRATE_TABLE       \
 471         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 472
 473 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 474 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 475 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 476 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 477
 478 /* Video */
 479 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 480 #ifdef CONFIG_FSL_DIU_FB
 481 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 482 #define CONFIG_VIDEO_LOGO
 483 #define CONFIG_VIDEO_BMP_LOGO
 484 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 485 /*
 486  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 487  * disable empty flash sector detection, which is I/O-intensive.
 488  */
 489 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 490 #endif
 491
 492 /* I2C */
 493 #define CONFIG_SYS_I2C
 494 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 495 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 496 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 497 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 498 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 499 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 500 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 501
 502 #define I2C_PCA6408_BUS_NUM             1
 503 #define I2C_PCA6408_ADDR                0x20
 504
 505 /* I2C bus multiplexer */
 506 #define I2C_MUX_CH_DEFAULT      0x8
 507
 508 /*
 509  * RTC configuration
 510  */
 511 #define RTC
 512 #define CONFIG_RTC_DS1337       1
 513 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 514
 515 /*
 516  * eSPI - Enhanced SPI
 517  */
 518 #define CONFIG_SPI_FLASH_BAR
 519 #define CONFIG_SF_DEFAULT_SPEED 10000000
 520 #define CONFIG_SF_DEFAULT_MODE  0
 521
 522 /*
 523  * General PCIe
 524  * Memory space is mapped 1-1, but I/O space must start from 0.
 525  */
 526 #define CONFIG_PCIE1            /* PCIE controller 1 */
 527 #define CONFIG_PCIE2            /* PCIE controller 2 */
 528 #define CONFIG_PCIE3            /* PCIE controller 3 */
 529 #ifdef CONFIG_ARCH_T1040
 530 #define CONFIG_PCIE4            /* PCIE controller 4 */
 531 #endif
 532 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 533 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 534 #define CONFIG_PCI_INDIRECT_BRIDGE
 535
 536 #ifdef CONFIG_PCI
 537 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 538 #ifdef CONFIG_PCIE1
 539 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 542 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 543 #else
 544 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 545 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 546 #endif
 547 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 548 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 549 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 552 #else
 553 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 554 #endif
 555 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 556 #endif
 557
 558 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 559 #ifdef CONFIG_PCIE2
 560 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 561 #ifdef CONFIG_PHYS_64BIT
 562 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 563 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 564 #else
 565 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 566 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 567 #endif
 568 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 569 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 570 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 571 #ifdef CONFIG_PHYS_64BIT
 572 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 573 #else
 574 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 575 #endif
 576 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 577 #endif
 578
 579 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 580 #ifdef CONFIG_PCIE3
 581 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 582 #ifdef CONFIG_PHYS_64BIT
 583 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 584 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 585 #else
 586 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 587 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 588 #endif
 589 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 590 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 591 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 592 #ifdef CONFIG_PHYS_64BIT
 593 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 594 #else
 595 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 596 #endif
 597 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 598 #endif
 599
 600 /* controller 4, Base address 203000, to be removed */
 601 #ifdef CONFIG_PCIE4
 602 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 603 #ifdef CONFIG_PHYS_64BIT
 604 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 605 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 606 #else
 607 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 608 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 609 #endif
 610 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 611 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 612 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 613 #ifdef CONFIG_PHYS_64BIT
 614 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 615 #else
 616 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 617 #endif
 618 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 619 #endif
 620
 621 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 622 #endif  /* CONFIG_PCI */
 623
 624 /*
 625  * USB
 626  */
 627 #define CONFIG_HAS_FSL_DR_USB
 628
 629 #ifdef CONFIG_HAS_FSL_DR_USB
 630 #define CONFIG_USB_EHCI_FSL
 631 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 632 #endif
 633
 634 /*
 635  * SDHC
 636  */
 637 #ifdef CONFIG_MMC
 638 #define CONFIG_FSL_ESDHC
 639 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 640 #endif
 641
 642 /* Qman/Bman */
 643 #ifndef CONFIG_NOBQFMAN
 644 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 645 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 646 #ifdef CONFIG_PHYS_64BIT
 647 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 648 #else
 649 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 650 #endif
 651 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 652 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 653 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 654 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 655 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 656 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 657                                         CONFIG_SYS_BMAN_CENA_SIZE)
 658 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 659 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 660 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 661 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 662 #ifdef CONFIG_PHYS_64BIT
 663 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 664 #else
 665 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 666 #endif
 667 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 668 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 669 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 670 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 671 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 672 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 673                                         CONFIG_SYS_QMAN_CENA_SIZE)
 674 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 675 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 676
 677 #define CONFIG_SYS_DPAA_FMAN
 678
 679 #ifdef CONFIG_TARGET_T1024RDB
 680 #define CONFIG_QE
 681 #define CONFIG_U_QE
 682 #endif
 683 /* Default address of microcode for the Linux FMan driver */
 684 #if defined(CONFIG_SPIFLASH)
 685 /*
 686  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 687  * env, so we got 0x110000.
 688  */
 689 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 690 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 691 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 692 #elif defined(CONFIG_SDCARD)
 693 /*
 694  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 695  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 696  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 697  */
 698 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 699 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 700 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 701 #elif defined(CONFIG_NAND)
 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 703 #if defined(CONFIG_TARGET_T1024RDB)
 704 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 705 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 706 #elif defined(CONFIG_TARGET_T1023RDB)
 707 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 708 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 709 #endif
 710 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 711 /*
 712  * Slave has no ucode locally, it can fetch this from remote. When implementing
 713  * in two corenet boards, slave's ucode could be stored in master's memory
 714  * space, the address can be mapped from slave TLB->slave LAW->
 715  * slave SRIO or PCIE outbound window->master inbound window->
 716  * master LAW->the ucode address in master's memory space.
 717  */
 718 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 719 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 720 #else
 721 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 722 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 723 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 724 #endif
 725 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 726 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 727 #endif /* CONFIG_NOBQFMAN */
 728
 729 #ifdef CONFIG_SYS_DPAA_FMAN
 730 #define CONFIG_FMAN_ENET
 731 #define CONFIG_PHYLIB_10G
 732 #define CONFIG_PHY_REALTEK
 733 #define CONFIG_PHY_AQUANTIA
 734 #if defined(CONFIG_TARGET_T1024RDB)
 735 #define RGMII_PHY1_ADDR         0x2
 736 #define RGMII_PHY2_ADDR         0x6
 737 #define SGMII_AQR_PHY_ADDR      0x2
 738 #define FM1_10GEC1_PHY_ADDR     0x1
 739 #elif defined(CONFIG_TARGET_T1023RDB)
 740 #define RGMII_PHY1_ADDR         0x1
 741 #define SGMII_RTK_PHY_ADDR      0x3
 742 #define SGMII_AQR_PHY_ADDR      0x2
 743 #endif
 744 #endif
 745
 746 #ifdef CONFIG_FMAN_ENET
 747 #define CONFIG_MII              /* MII PHY management */
 748 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 749 #endif
 750
 751 /*
 752  * Dynamic MTD Partition support with mtdparts
 753  */
 754 #ifdef CONFIG_MTD_NOR_FLASH
 755 #define CONFIG_MTD_DEVICE
 756 #define CONFIG_MTD_PARTITIONS
 757 #define CONFIG_FLASH_CFI_MTD
 758 #endif
 759
 760 /*
 761  * Environment
 762  */
 763 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 764 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 765
 766 /*
 767  * Miscellaneous configurable options
 768  */
 769 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 770
 771 /*
 772  * For booting Linux, the board info and command line data
 773  * have to be in the first 64 MB of memory, since this is
 774  * the maximum mapped by the Linux kernel during initialization.
 775  */
 776 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 777 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 778
 779 #ifdef CONFIG_CMD_KGDB
 780 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 781 #endif
 782
 783 /*
 784  * Environment Configuration
 785  */
 786 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 787 #define CONFIG_BOOTFILE         "uImage"
 788 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 789 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 790 #define __USB_PHY_TYPE          utmi
 791
 792 #ifdef CONFIG_ARCH_T1024
 793 #define CONFIG_BOARDNAME t1024rdb
 794 #define BANK_INTLV cs0_cs1
 795 #else
 796 #define CONFIG_BOARDNAME t1023rdb
 797 #define BANK_INTLV  null
 798 #endif
 799
 800 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 801         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 802         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 803         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 804         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 805         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 806         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 807         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 808         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 809         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 810         "netdev=eth0\0"                                         \
 811         "tftpflash=tftpboot $loadaddr $uboot && "               \
 812         "protect off $ubootaddr +$filesize && "                 \
 813         "erase $ubootaddr +$filesize && "                       \
 814         "cp.b $loadaddr $ubootaddr $filesize && "               \
 815         "protect on $ubootaddr +$filesize && "                  \
 816         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 817         "consoledev=ttyS0\0"                                    \
 818         "ramdiskaddr=2000000\0"                                 \
 819         "fdtaddr=1e00000\0"                                     \
 820         "bdev=sda3\0"
 821
 822 #define CONFIG_LINUX                                    \
 823         "setenv bootargs root=/dev/ram rw "             \
 824         "console=$consoledev,$baudrate $othbootargs;"   \
 825         "setenv ramdiskaddr 0x02000000;"                \
 826         "setenv fdtaddr 0x00c00000;"                    \
 827         "setenv loadaddr 0x1000000;"                    \
 828         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 829
 830 #define CONFIG_NFSBOOTCOMMAND                   \
 831         "setenv bootargs root=/dev/nfs rw "     \
 832         "nfsroot=$serverip:$rootpath "          \
 833         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 834         "console=$consoledev,$baudrate $othbootargs;"   \
 835         "tftp $loadaddr $bootfile;"             \
 836         "tftp $fdtaddr $fdtfile;"               \
 837         "bootm $loadaddr - $fdtaddr"
 838
 839 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 840
 841 #include <asm/fsl_secure_boot.h>
 842
 843 #endif  /* __T1024RDB_H */