373cb2a81c91125ad88602fd618a96848f17f52e
[platform/kernel/u-boot.git] / include / configs / T102xRDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T1024/T1023 RDB board configuration file
9  */
10
11 #ifndef __T1024RDB_H
12 #define __T1024RDB_H
13
14 /* High Level Configuration Options */
15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
16 #define CONFIG_MP                       /* support multiple processors */
17 #define CONFIG_ENABLE_36BIT_PHYS
18
19 #ifdef CONFIG_PHYS_64BIT
20 #define CONFIG_ADDR_MAP         1
21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
22 #endif
23
24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
26
27 #define CONFIG_ENV_OVERWRITE
28
29 /* support deep sleep */
30 #ifdef CONFIG_ARCH_T1024
31 #define CONFIG_DEEP_SLEEP
32 #endif
33
34 #ifdef CONFIG_RAMBOOT_PBL
35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
36 #define CONFIG_SPL_FLUSH_IMAGE
37 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
38 #define CONFIG_SYS_TEXT_BASE            0x30001000
39 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
40 #define CONFIG_SPL_PAD_TO               0x40000
41 #define CONFIG_SPL_MAX_SIZE             0x28000
42 #define RESET_VECTOR_OFFSET             0x27FFC
43 #define BOOT_PAGE_OFFSET                0x27000
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48 #endif
49
50 #ifdef CONFIG_NAND
51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
53 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
56 #if defined(CONFIG_TARGET_T1024RDB)
57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
58 #elif defined(CONFIG_TARGET_T1023RDB)
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
60 #endif
61 #define CONFIG_SPL_NAND_BOOT
62 #endif
63
64 #ifdef CONFIG_SPIFLASH
65 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
71 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72 #ifndef CONFIG_SPL_BUILD
73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #endif
75 #if defined(CONFIG_TARGET_T1024RDB)
76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
77 #elif defined(CONFIG_TARGET_T1023RDB)
78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
79 #endif
80 #define CONFIG_SPL_SPI_BOOT
81 #endif
82
83 #ifdef CONFIG_SDCARD
84 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
85 #define CONFIG_SPL_MMC_MINIMAL
86 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
87 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
88 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
89 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
90 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91 #ifndef CONFIG_SPL_BUILD
92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
93 #endif
94 #if defined(CONFIG_TARGET_T1024RDB)
95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
96 #elif defined(CONFIG_TARGET_T1023RDB)
97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
98 #endif
99 #define CONFIG_SPL_MMC_BOOT
100 #endif
101
102 #endif /* CONFIG_RAMBOOT_PBL */
103
104 #ifndef CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_TEXT_BASE    0xeff40000
106 #endif
107
108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
109 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
110 #endif
111
112 #ifdef CONFIG_MTD_NOR_FLASH
113 #define CONFIG_FLASH_CFI_DRIVER
114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #endif
117
118 /* PCIe Boot - Master */
119 #define CONFIG_SRIO_PCIE_BOOT_MASTER
120 /*
121  * for slave u-boot IMAGE instored in master memory space,
122  * PHYS must be aligned based on the SIZE
123  */
124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
129 #else
130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
132 #endif
133 /*
134  * for slave UCODE and ENV instored in master memory space,
135  * PHYS must be aligned based on the SIZE
136  */
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
140 #else
141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
143 #endif
144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
145 /* slave core release by master*/
146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
148
149 /* PCIe Boot - Slave */
150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
153                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
154 /* Set 1M boot space for PCIe boot */
155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
157                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
159 #endif
160
161 #if defined(CONFIG_SPIFLASH)
162 #define CONFIG_SYS_EXTRA_ENV_RELOC
163 #define CONFIG_ENV_IS_IN_SPI_FLASH
164 #define CONFIG_ENV_SPI_BUS              0
165 #define CONFIG_ENV_SPI_CS               0
166 #define CONFIG_ENV_SPI_MAX_HZ           10000000
167 #define CONFIG_ENV_SPI_MODE             0
168 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
169 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
170 #if defined(CONFIG_TARGET_T1024RDB)
171 #define CONFIG_ENV_SECT_SIZE            0x10000
172 #elif defined(CONFIG_TARGET_T1023RDB)
173 #define CONFIG_ENV_SECT_SIZE            0x40000
174 #endif
175 #elif defined(CONFIG_SDCARD)
176 #define CONFIG_SYS_EXTRA_ENV_RELOC
177 #define CONFIG_ENV_IS_IN_MMC
178 #define CONFIG_SYS_MMC_ENV_DEV          0
179 #define CONFIG_ENV_SIZE                 0x2000
180 #define CONFIG_ENV_OFFSET               (512 * 0x800)
181 #elif defined(CONFIG_NAND)
182 #define CONFIG_SYS_EXTRA_ENV_RELOC
183 #define CONFIG_ENV_IS_IN_NAND
184 #define CONFIG_ENV_SIZE                 0x2000
185 #if defined(CONFIG_TARGET_T1024RDB)
186 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
187 #elif defined(CONFIG_TARGET_T1023RDB)
188 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
189 #endif
190 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
191 #define CONFIG_ENV_IS_IN_REMOTE
192 #define CONFIG_ENV_ADDR         0xffe20000
193 #define CONFIG_ENV_SIZE         0x2000
194 #elif defined(CONFIG_ENV_IS_NOWHERE)
195 #define CONFIG_ENV_SIZE         0x2000
196 #else
197 #define CONFIG_ENV_IS_IN_FLASH
198 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
199 #define CONFIG_ENV_SIZE         0x2000
200 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
201 #endif
202
203 #ifndef __ASSEMBLY__
204 unsigned long get_board_sys_clk(void);
205 unsigned long get_board_ddr_clk(void);
206 #endif
207
208 #define CONFIG_SYS_CLK_FREQ     100000000
209 #define CONFIG_DDR_CLK_FREQ     100000000
210
211 /*
212  * These can be toggled for performance analysis, otherwise use default.
213  */
214 #define CONFIG_SYS_CACHE_STASHING
215 #define CONFIG_BACKSIDE_L2_CACHE
216 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
217 #define CONFIG_BTB                      /* toggle branch predition */
218 #define CONFIG_DDR_ECC
219 #ifdef CONFIG_DDR_ECC
220 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
221 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
222 #endif
223
224 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
225 #define CONFIG_SYS_MEMTEST_END          0x00400000
226 #define CONFIG_SYS_ALT_MEMTEST
227 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
228
229 /*
230  *  Config the L3 Cache as L3 SRAM
231  */
232 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
233 #define CONFIG_SYS_L3_SIZE              (256 << 10)
234 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
235 #ifdef CONFIG_RAMBOOT_PBL
236 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
237 #endif
238 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
239 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
240 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
241 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
242
243 #ifdef CONFIG_PHYS_64BIT
244 #define CONFIG_SYS_DCSRBAR              0xf0000000
245 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
246 #endif
247
248 /* EEPROM */
249 #define CONFIG_ID_EEPROM
250 #define CONFIG_SYS_I2C_EEPROM_NXID
251 #define CONFIG_SYS_EEPROM_BUS_NUM       0
252 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
256
257 /*
258  * DDR Setup
259  */
260 #define CONFIG_VERY_BIG_RAM
261 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
262 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
263 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
264 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
265 #define CONFIG_FSL_DDR_INTERACTIVE
266 #if defined(CONFIG_TARGET_T1024RDB)
267 #define CONFIG_DDR_SPD
268 #define CONFIG_SYS_SPD_BUS_NUM  0
269 #define SPD_EEPROM_ADDRESS      0x51
270 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
271 #elif defined(CONFIG_TARGET_T1023RDB)
272 #define CONFIG_SYS_DDR_RAW_TIMING
273 #define CONFIG_SYS_SDRAM_SIZE   2048
274 #endif
275
276 /*
277  * IFC Definitions
278  */
279 #define CONFIG_SYS_FLASH_BASE   0xe8000000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282 #else
283 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
284 #endif
285
286 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
287 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
288                                 CSPR_PORT_SIZE_16 | \
289                                 CSPR_MSEL_NOR | \
290                                 CSPR_V)
291 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
292
293 /* NOR Flash Timing Params */
294 #if defined(CONFIG_TARGET_T1024RDB)
295 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
296 #elif defined(CONFIG_TARGET_T1023RDB)
297 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
298                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
299 #endif
300 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
301                                 FTIM0_NOR_TEADC(0x5) | \
302                                 FTIM0_NOR_TEAHC(0x5))
303 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
304                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
305                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
306 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
307                                 FTIM2_NOR_TCH(0x4) | \
308                                 FTIM2_NOR_TWPH(0x0E) | \
309                                 FTIM2_NOR_TWP(0x1c))
310 #define CONFIG_SYS_NOR_FTIM3    0x0
311
312 #define CONFIG_SYS_FLASH_QUIET_TEST
313 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
314
315 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
316 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
317 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
318 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
319
320 #define CONFIG_SYS_FLASH_EMPTY_INFO
321 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
322
323 #ifdef CONFIG_TARGET_T1024RDB
324 /* CPLD on IFC */
325 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
326 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
327 #define CONFIG_SYS_CSPR2_EXT            (0xf)
328 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
329                                                 | CSPR_PORT_SIZE_8 \
330                                                 | CSPR_MSEL_GPCM \
331                                                 | CSPR_V)
332 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
333 #define CONFIG_SYS_CSOR2                0x0
334
335 /* CPLD Timing parameters for IFC CS2 */
336 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
337                                                 FTIM0_GPCM_TEADC(0x0e) | \
338                                                 FTIM0_GPCM_TEAHC(0x0e))
339 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
340                                                 FTIM1_GPCM_TRAD(0x1f))
341 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
342                                                 FTIM2_GPCM_TCH(0x8) | \
343                                                 FTIM2_GPCM_TWP(0x1f))
344 #define CONFIG_SYS_CS2_FTIM3            0x0
345 #endif
346
347 /* NAND Flash on IFC */
348 #define CONFIG_NAND_FSL_IFC
349 #define CONFIG_SYS_NAND_BASE            0xff800000
350 #ifdef CONFIG_PHYS_64BIT
351 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
352 #else
353 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
354 #endif
355 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
356 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
357                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
358                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
359                                 | CSPR_V)
360 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
361
362 #if defined(CONFIG_TARGET_T1024RDB)
363 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
364                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
365                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
366                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
367                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
368                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
369                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
370 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
371 #elif defined(CONFIG_TARGET_T1023RDB)
372 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
373                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
374                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
375                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
376                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
377                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
378                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
379 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
380 #endif
381
382 #define CONFIG_SYS_NAND_ONFI_DETECTION
383 /* ONFI NAND Flash mode0 Timing Params */
384 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
385                                         FTIM0_NAND_TWP(0x18)   | \
386                                         FTIM0_NAND_TWCHT(0x07) | \
387                                         FTIM0_NAND_TWH(0x0a))
388 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
389                                         FTIM1_NAND_TWBE(0x39)  | \
390                                         FTIM1_NAND_TRR(0x0e)   | \
391                                         FTIM1_NAND_TRP(0x18))
392 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
393                                         FTIM2_NAND_TREH(0x0a) | \
394                                         FTIM2_NAND_TWHRE(0x1e))
395 #define CONFIG_SYS_NAND_FTIM3           0x0
396
397 #define CONFIG_SYS_NAND_DDR_LAW         11
398 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
399 #define CONFIG_SYS_MAX_NAND_DEVICE      1
400 #define CONFIG_CMD_NAND
401
402 #if defined(CONFIG_NAND)
403 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
404 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
405 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
406 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
407 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
408 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
409 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
410 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
411 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
412 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
413 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
414 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
415 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
416 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
417 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
418 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
419 #else
420 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
421 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
422 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
423 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
424 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
425 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
426 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
427 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
428 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
429 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
430 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
431 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
432 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
433 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
434 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
435 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
436 #endif
437
438 #ifdef CONFIG_SPL_BUILD
439 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
440 #else
441 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
442 #endif
443
444 #if defined(CONFIG_RAMBOOT_PBL)
445 #define CONFIG_SYS_RAMBOOT
446 #endif
447
448 #define CONFIG_BOARD_EARLY_INIT_R
449 #define CONFIG_MISC_INIT_R
450
451 #define CONFIG_HWCONFIG
452
453 /* define to use L1 as initial stack */
454 #define CONFIG_L1_INIT_RAM
455 #define CONFIG_SYS_INIT_RAM_LOCK
456 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
460 /* The assembler doesn't like typecast */
461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
462         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
463           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
464 #else
465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
468 #endif
469 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
470
471 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
472                                         GENERATED_GBL_DATA_SIZE)
473 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
474
475 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
476 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
477
478 /* Serial Port */
479 #define CONFIG_CONS_INDEX       1
480 #define CONFIG_SYS_NS16550_SERIAL
481 #define CONFIG_SYS_NS16550_REG_SIZE     1
482 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
483
484 #define CONFIG_SYS_BAUDRATE_TABLE       \
485         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486
487 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
488 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
489 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
490 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
491
492 /* Video */
493 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
494 #ifdef CONFIG_FSL_DIU_FB
495 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
496 #define CONFIG_VIDEO_LOGO
497 #define CONFIG_VIDEO_BMP_LOGO
498 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
499 /*
500  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
501  * disable empty flash sector detection, which is I/O-intensive.
502  */
503 #undef CONFIG_SYS_FLASH_EMPTY_INFO
504 #endif
505
506 /* I2C */
507 #define CONFIG_SYS_I2C
508 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
509 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
510 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
511 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
512 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
513 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
514 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
515
516 #define I2C_PCA6408_BUS_NUM             1
517 #define I2C_PCA6408_ADDR                0x20
518
519 /* I2C bus multiplexer */
520 #define I2C_MUX_CH_DEFAULT      0x8
521
522 /*
523  * RTC configuration
524  */
525 #define RTC
526 #define CONFIG_RTC_DS1337       1
527 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
528
529 /*
530  * eSPI - Enhanced SPI
531  */
532 #define CONFIG_SPI_FLASH_BAR
533 #define CONFIG_SF_DEFAULT_SPEED 10000000
534 #define CONFIG_SF_DEFAULT_MODE  0
535
536 /*
537  * General PCIe
538  * Memory space is mapped 1-1, but I/O space must start from 0.
539  */
540 #define CONFIG_PCIE1            /* PCIE controller 1 */
541 #define CONFIG_PCIE2            /* PCIE controller 2 */
542 #define CONFIG_PCIE3            /* PCIE controller 3 */
543 #ifdef CONFIG_ARCH_T1040
544 #define CONFIG_PCIE4            /* PCIE controller 4 */
545 #endif
546 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
547 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
548 #define CONFIG_PCI_INDIRECT_BRIDGE
549
550 #ifdef CONFIG_PCI
551 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
552 #ifdef CONFIG_PCIE1
553 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
554 #ifdef CONFIG_PHYS_64BIT
555 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
556 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
557 #else
558 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
559 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
560 #endif
561 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
562 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
563 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
564 #ifdef CONFIG_PHYS_64BIT
565 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
566 #else
567 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
568 #endif
569 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
570 #endif
571
572 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
573 #ifdef CONFIG_PCIE2
574 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
575 #ifdef CONFIG_PHYS_64BIT
576 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
577 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
578 #else
579 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
580 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
581 #endif
582 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
583 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
584 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
585 #ifdef CONFIG_PHYS_64BIT
586 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
587 #else
588 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
589 #endif
590 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
591 #endif
592
593 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
594 #ifdef CONFIG_PCIE3
595 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
596 #ifdef CONFIG_PHYS_64BIT
597 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
598 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
599 #else
600 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
601 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
602 #endif
603 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
604 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
605 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
606 #ifdef CONFIG_PHYS_64BIT
607 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
608 #else
609 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
610 #endif
611 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
612 #endif
613
614 /* controller 4, Base address 203000, to be removed */
615 #ifdef CONFIG_PCIE4
616 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
617 #ifdef CONFIG_PHYS_64BIT
618 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
619 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
620 #else
621 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
622 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
623 #endif
624 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
625 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
626 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
627 #ifdef CONFIG_PHYS_64BIT
628 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
629 #else
630 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
631 #endif
632 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
633 #endif
634
635 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
636 #endif  /* CONFIG_PCI */
637
638 /*
639  * USB
640  */
641 #define CONFIG_HAS_FSL_DR_USB
642
643 #ifdef CONFIG_HAS_FSL_DR_USB
644 #define CONFIG_USB_EHCI_FSL
645 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
646 #endif
647
648 /*
649  * SDHC
650  */
651 #ifdef CONFIG_MMC
652 #define CONFIG_FSL_ESDHC
653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
654 #endif
655
656 /* Qman/Bman */
657 #ifndef CONFIG_NOBQFMAN
658 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
659 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
660 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
661 #ifdef CONFIG_PHYS_64BIT
662 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
663 #else
664 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
665 #endif
666 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
667 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
668 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
669 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
670 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
671 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
672                                         CONFIG_SYS_BMAN_CENA_SIZE)
673 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
674 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
675 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
676 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
677 #ifdef CONFIG_PHYS_64BIT
678 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
679 #else
680 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
681 #endif
682 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
683 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
684 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
685 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
686 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
687 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
688                                         CONFIG_SYS_QMAN_CENA_SIZE)
689 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
690 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
691
692 #define CONFIG_SYS_DPAA_FMAN
693
694 #ifdef CONFIG_TARGET_T1024RDB
695 #define CONFIG_QE
696 #define CONFIG_U_QE
697 #endif
698 /* Default address of microcode for the Linux FMan driver */
699 #if defined(CONFIG_SPIFLASH)
700 /*
701  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
702  * env, so we got 0x110000.
703  */
704 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
705 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
706 #define CONFIG_SYS_QE_FW_ADDR   0x130000
707 #elif defined(CONFIG_SDCARD)
708 /*
709  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
710  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
711  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
712  */
713 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
714 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
715 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
716 #elif defined(CONFIG_NAND)
717 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
718 #if defined(CONFIG_TARGET_T1024RDB)
719 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
720 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
721 #elif defined(CONFIG_TARGET_T1023RDB)
722 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
723 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
724 #endif
725 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
726 /*
727  * Slave has no ucode locally, it can fetch this from remote. When implementing
728  * in two corenet boards, slave's ucode could be stored in master's memory
729  * space, the address can be mapped from slave TLB->slave LAW->
730  * slave SRIO or PCIE outbound window->master inbound window->
731  * master LAW->the ucode address in master's memory space.
732  */
733 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
734 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
735 #else
736 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
737 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
738 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
739 #endif
740 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
741 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
742 #endif /* CONFIG_NOBQFMAN */
743
744 #ifdef CONFIG_SYS_DPAA_FMAN
745 #define CONFIG_FMAN_ENET
746 #define CONFIG_PHYLIB_10G
747 #define CONFIG_PHY_REALTEK
748 #define CONFIG_PHY_AQUANTIA
749 #if defined(CONFIG_TARGET_T1024RDB)
750 #define RGMII_PHY1_ADDR         0x2
751 #define RGMII_PHY2_ADDR         0x6
752 #define SGMII_AQR_PHY_ADDR      0x2
753 #define FM1_10GEC1_PHY_ADDR     0x1
754 #elif defined(CONFIG_TARGET_T1023RDB)
755 #define RGMII_PHY1_ADDR         0x1
756 #define SGMII_RTK_PHY_ADDR      0x3
757 #define SGMII_AQR_PHY_ADDR      0x2
758 #endif
759 #endif
760
761 #ifdef CONFIG_FMAN_ENET
762 #define CONFIG_MII              /* MII PHY management */
763 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
764 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
765 #endif
766
767 /*
768  * Dynamic MTD Partition support with mtdparts
769  */
770 #ifdef CONFIG_MTD_NOR_FLASH
771 #define CONFIG_MTD_DEVICE
772 #define CONFIG_MTD_PARTITIONS
773 #define CONFIG_CMD_MTDPARTS
774 #define CONFIG_FLASH_CFI_MTD
775 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
776                         "spi0=spife110000.1"
777 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
778                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
779                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
780                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
781 #endif
782
783 /*
784  * Environment
785  */
786 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
787 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
788
789 /*
790  * Command line configuration.
791  */
792 #define CONFIG_CMD_EEPROM
793 #define CONFIG_CMD_ERRATA
794 #define CONFIG_CMD_IRQ
795 #define CONFIG_CMD_REGINFO
796
797 #ifdef CONFIG_PCI
798 #define CONFIG_CMD_PCI
799 #endif
800
801 /*
802  * Miscellaneous configurable options
803  */
804 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
805 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
806 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
807 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
808 #ifdef CONFIG_CMD_KGDB
809 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
810 #else
811 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
812 #endif
813 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
814 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
815 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
816
817 /*
818  * For booting Linux, the board info and command line data
819  * have to be in the first 64 MB of memory, since this is
820  * the maximum mapped by the Linux kernel during initialization.
821  */
822 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
823 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
824
825 #ifdef CONFIG_CMD_KGDB
826 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
827 #endif
828
829 /*
830  * Environment Configuration
831  */
832 #define CONFIG_ROOTPATH         "/opt/nfsroot"
833 #define CONFIG_BOOTFILE         "uImage"
834 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
835 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
836 #define __USB_PHY_TYPE          utmi
837
838 #ifdef CONFIG_ARCH_T1024
839 #define CONFIG_BOARDNAME t1024rdb
840 #define BANK_INTLV cs0_cs1
841 #else
842 #define CONFIG_BOARDNAME t1023rdb
843 #define BANK_INTLV  null
844 #endif
845
846 #define CONFIG_EXTRA_ENV_SETTINGS                               \
847         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
848         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
849         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
850         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
851         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
852         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
853         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
854         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
855         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
856         "netdev=eth0\0"                                         \
857         "tftpflash=tftpboot $loadaddr $uboot && "               \
858         "protect off $ubootaddr +$filesize && "                 \
859         "erase $ubootaddr +$filesize && "                       \
860         "cp.b $loadaddr $ubootaddr $filesize && "               \
861         "protect on $ubootaddr +$filesize && "                  \
862         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
863         "consoledev=ttyS0\0"                                    \
864         "ramdiskaddr=2000000\0"                                 \
865         "fdtaddr=1e00000\0"                                     \
866         "bdev=sda3\0"
867
868 #define CONFIG_LINUX                                    \
869         "setenv bootargs root=/dev/ram rw "             \
870         "console=$consoledev,$baudrate $othbootargs;"   \
871         "setenv ramdiskaddr 0x02000000;"                \
872         "setenv fdtaddr 0x00c00000;"                    \
873         "setenv loadaddr 0x1000000;"                    \
874         "bootm $loadaddr $ramdiskaddr $fdtaddr"
875
876 #define CONFIG_NFSBOOTCOMMAND                   \
877         "setenv bootargs root=/dev/nfs rw "     \
878         "nfsroot=$serverip:$rootpath "          \
879         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
880         "console=$consoledev,$baudrate $othbootargs;"   \
881         "tftp $loadaddr $bootfile;"             \
882         "tftp $fdtaddr $fdtfile;"               \
883         "bootm $loadaddr - $fdtaddr"
884
885 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
886
887 /* Hash command with SHA acceleration supported in hardware */
888 #ifdef CONFIG_FSL_CAAM
889 #define CONFIG_CMD_HASH
890 #endif
891
892 #include <asm/fsl_secure_boot.h>
893
894 #endif  /* __T1024RDB_H */