include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #define CONFIG_DEEP_SLEEP
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  33 #define CONFIG_SPL_FLUSH_IMAGE
  34 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  35 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  36 #define CONFIG_SPL_PAD_TO               0x40000
  37 #define CONFIG_SPL_MAX_SIZE             0x28000
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #ifdef CONFIG_NAND
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  53 #define CONFIG_SPL_NAND_BOOT
  54 #endif
  55
  56 #ifdef CONFIG_SPIFLASH
  57 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  58 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  63 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #endif
  67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  68 #define CONFIG_SPL_SPI_BOOT
  69 #endif
  70
  71 #ifdef CONFIG_SDCARD
  72 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  73 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  74 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  75 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  76 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  77 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  78 #ifndef CONFIG_SPL_BUILD
  79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  80 #endif
  81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  82 #define CONFIG_SPL_MMC_BOOT
  83 #endif
  84
  85 #endif /* CONFIG_RAMBOOT_PBL */
  86
  87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  88 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  89 #endif
  90
  91 #ifdef CONFIG_MTD_NOR_FLASH
  92 #define CONFIG_FLASH_CFI_DRIVER
  93 #define CONFIG_SYS_FLASH_CFI
  94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  95 #endif
  96
  97 /* PCIe Boot - Master */
  98 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  99 /*
 100  * for slave u-boot IMAGE instored in master memory space,
 101  * PHYS must be aligned based on the SIZE
 102  */
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 105 #ifdef CONFIG_PHYS_64BIT
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 108 #else
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 111 #endif
 112 /*
 113  * for slave UCODE and ENV instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 119 #else
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 122 #endif
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 124 /* slave core release by master*/
 125 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 126 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 127
 128 /* PCIe Boot - Slave */
 129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 132                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 133 /* Set 1M boot space for PCIe boot */
 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 135 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 136                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 137 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 138 #endif
 139
 140 #if defined(CONFIG_SPIFLASH)
 141 #define CONFIG_SYS_EXTRA_ENV_RELOC
 142 #define CONFIG_ENV_SPI_BUS              0
 143 #define CONFIG_ENV_SPI_CS               0
 144 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 145 #define CONFIG_ENV_SPI_MODE             0
 146 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 147 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 148 #define CONFIG_ENV_SECT_SIZE            0x10000
 149 #elif defined(CONFIG_SDCARD)
 150 #define CONFIG_SYS_EXTRA_ENV_RELOC
 151 #define CONFIG_SYS_MMC_ENV_DEV          0
 152 #define CONFIG_ENV_SIZE                 0x2000
 153 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 154 #elif defined(CONFIG_NAND)
 155 #define CONFIG_SYS_EXTRA_ENV_RELOC
 156 #define CONFIG_ENV_SIZE                 0x2000
 157 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 158 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 159 #define CONFIG_ENV_ADDR         0xffe20000
 160 #define CONFIG_ENV_SIZE         0x2000
 161 #elif defined(CONFIG_ENV_IS_NOWHERE)
 162 #define CONFIG_ENV_SIZE         0x2000
 163 #else
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 167 #endif
 168
 169 #ifndef __ASSEMBLY__
 170 unsigned long get_board_sys_clk(void);
 171 unsigned long get_board_ddr_clk(void);
 172 #endif
 173
 174 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 175 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 176
 177 /*
 178  * These can be toggled for performance analysis, otherwise use default.
 179  */
 180 #define CONFIG_SYS_CACHE_STASHING
 181 #define CONFIG_BACKSIDE_L2_CACHE
 182 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 183 #define CONFIG_BTB                      /* toggle branch predition */
 184 #define CONFIG_DDR_ECC
 185 #ifdef CONFIG_DDR_ECC
 186 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 187 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 188 #endif
 189
 190 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 191 #define CONFIG_SYS_MEMTEST_END          0x00400000
 192
 193 /*
 194  *  Config the L3 Cache as L3 SRAM
 195  */
 196 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 197 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 198 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 199 #ifdef CONFIG_RAMBOOT_PBL
 200 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 201 #endif
 202 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 203 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 204 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 205 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 206
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CONFIG_SYS_DCSRBAR              0xf0000000
 209 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 210 #endif
 211
 212 /* EEPROM */
 213 #define CONFIG_ID_EEPROM
 214 #define CONFIG_SYS_I2C_EEPROM_NXID
 215 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 216 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 220
 221 /*
 222  * DDR Setup
 223  */
 224 #define CONFIG_VERY_BIG_RAM
 225 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 226 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 227 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 228 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 229 #define CONFIG_DDR_SPD
 230
 231 #define CONFIG_SYS_SPD_BUS_NUM  0
 232 #define SPD_EEPROM_ADDRESS      0x51
 233
 234 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 235
 236 /*
 237  * IFC Definitions
 238  */
 239 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 240 #ifdef CONFIG_PHYS_64BIT
 241 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 242 #else
 243 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 244 #endif
 245
 246 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 247 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 248                                 + 0x8000000) | \
 249                                 CSPR_PORT_SIZE_16 | \
 250                                 CSPR_MSEL_NOR | \
 251                                 CSPR_V)
 252 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 253 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 254                                 CSPR_PORT_SIZE_16 | \
 255                                 CSPR_MSEL_NOR | \
 256                                 CSPR_V)
 257 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 258 /* NOR Flash Timing Params */
 259 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 260 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 261                                 FTIM0_NOR_TEADC(0x5) | \
 262                                 FTIM0_NOR_TEAHC(0x5))
 263 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 264                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 265                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 266 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 267                                 FTIM2_NOR_TCH(0x4) | \
 268                                 FTIM2_NOR_TWPH(0x0E) | \
 269                                 FTIM2_NOR_TWP(0x1c))
 270 #define CONFIG_SYS_NOR_FTIM3    0x0
 271
 272 #define CONFIG_SYS_FLASH_QUIET_TEST
 273 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 274
 275 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 276 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 277 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 278 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 279
 280 #define CONFIG_SYS_FLASH_EMPTY_INFO
 281 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 282                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 283 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 284 #define QIXIS_BASE              0xffdf0000
 285 #ifdef CONFIG_PHYS_64BIT
 286 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 287 #else
 288 #define QIXIS_BASE_PHYS         QIXIS_BASE
 289 #endif
 290 #define QIXIS_LBMAP_SWITCH              0x06
 291 #define QIXIS_LBMAP_MASK                0x0f
 292 #define QIXIS_LBMAP_SHIFT               0
 293 #define QIXIS_LBMAP_DFLTBANK            0x00
 294 #define QIXIS_LBMAP_ALTBANK             0x04
 295 #define QIXIS_RST_CTL_RESET             0x31
 296 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 297 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 298 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 299 #define QIXIS_RST_FORCE_MEM             0x01
 300
 301 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 302 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 303                                 | CSPR_PORT_SIZE_8 \
 304                                 | CSPR_MSEL_GPCM \
 305                                 | CSPR_V)
 306 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 307 #define CONFIG_SYS_CSOR3        0x0
 308 /* QIXIS Timing parameters for IFC CS3 */
 309 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 310                                         FTIM0_GPCM_TEADC(0x0e) | \
 311                                         FTIM0_GPCM_TEAHC(0x0e))
 312 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 313                                         FTIM1_GPCM_TRAD(0x3f))
 314 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 315                                         FTIM2_GPCM_TCH(0x8) | \
 316                                         FTIM2_GPCM_TWP(0x1f))
 317 #define CONFIG_SYS_CS3_FTIM3            0x0
 318
 319 #define CONFIG_NAND_FSL_IFC
 320 #define CONFIG_SYS_NAND_BASE            0xff800000
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 323 #else
 324 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 325 #endif
 326 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 327 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 328                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 329                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 330                                 | CSPR_V)
 331 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 332
 333 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 334                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 335                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 336                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 337                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 338                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 339                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 340
 341 #define CONFIG_SYS_NAND_ONFI_DETECTION
 342
 343 /* ONFI NAND Flash mode0 Timing Params */
 344 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 345                                         FTIM0_NAND_TWP(0x18)   | \
 346                                         FTIM0_NAND_TWCHT(0x07) | \
 347                                         FTIM0_NAND_TWH(0x0a))
 348 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 349                                         FTIM1_NAND_TWBE(0x39)  | \
 350                                         FTIM1_NAND_TRR(0x0e)   | \
 351                                         FTIM1_NAND_TRP(0x18))
 352 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 353                                         FTIM2_NAND_TREH(0x0a) | \
 354                                         FTIM2_NAND_TWHRE(0x1e))
 355 #define CONFIG_SYS_NAND_FTIM3           0x0
 356
 357 #define CONFIG_SYS_NAND_DDR_LAW         11
 358 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 359 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 360
 361 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 362
 363 #if defined(CONFIG_NAND)
 364 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 365 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 366 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 367 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 368 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 369 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 370 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 371 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 372 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 373 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 374 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 375 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 376 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 377 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 378 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 379 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 380 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 381 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 382 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 383 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 384 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 385 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 386 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 387 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 388 #else
 389 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 390 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 391 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 392 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 393 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 394 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 395 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 396 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 397 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 398 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 399 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 400 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 401 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 402 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 403 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 404 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 405 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 406 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 407 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 408 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 409 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 410 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 411 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 412 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 413 #endif
 414
 415 #ifdef CONFIG_SPL_BUILD
 416 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 417 #else
 418 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 419 #endif
 420
 421 #if defined(CONFIG_RAMBOOT_PBL)
 422 #define CONFIG_SYS_RAMBOOT
 423 #endif
 424
 425 #define CONFIG_MISC_INIT_R
 426
 427 #define CONFIG_HWCONFIG
 428
 429 /* define to use L1 as initial stack */
 430 #define CONFIG_L1_INIT_RAM
 431 #define CONFIG_SYS_INIT_RAM_LOCK
 432 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 433 #ifdef CONFIG_PHYS_64BIT
 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 436 /* The assembler doesn't like typecast */
 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 438         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 439           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 440 #else
 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 444 #endif
 445 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 446
 447 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 448                                         GENERATED_GBL_DATA_SIZE)
 449 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 450
 451 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 452 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 453
 454 /* Serial Port */
 455 #define CONFIG_SYS_NS16550_SERIAL
 456 #define CONFIG_SYS_NS16550_REG_SIZE     1
 457 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 458
 459 #define CONFIG_SYS_BAUDRATE_TABLE       \
 460         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 461
 462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 464 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 465 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 466
 467 /* Video */
 468 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 469 #define CONFIG_FSL_DIU_FB
 470 #ifdef CONFIG_FSL_DIU_FB
 471 #define CONFIG_FSL_DIU_CH7301
 472 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 473 #define CONFIG_VIDEO_LOGO
 474 #define CONFIG_VIDEO_BMP_LOGO
 475 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 476 /*
 477  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 478  * disable empty flash sector detection, which is I/O-intensive.
 479  */
 480 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 481 #endif
 482 #endif
 483
 484 /* I2C */
 485 #define CONFIG_SYS_I2C
 486 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 487 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 488 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 489 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 490 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 491 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 492 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 493
 494 #define I2C_MUX_PCA_ADDR                0x77
 495 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 496 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 497 #define I2C_RETIMER_ADDR                0x18
 498
 499 /* I2C bus multiplexer */
 500 #define I2C_MUX_CH_DEFAULT      0x8
 501 #define I2C_MUX_CH_DIU          0xC
 502 #define I2C_MUX_CH5             0xD
 503 #define I2C_MUX_CH7             0xF
 504
 505 /* LDI/DVI Encoder for display */
 506 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 507 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 508
 509 /*
 510  * RTC configuration
 511  */
 512 #define RTC
 513 #define CONFIG_RTC_DS3231       1
 514 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 515
 516 /*
 517  * eSPI - Enhanced SPI
 518  */
 519 #ifndef CONFIG_SPL_BUILD
 520 #endif
 521 #define CONFIG_SPI_FLASH_BAR
 522 #define CONFIG_SF_DEFAULT_SPEED  10000000
 523 #define CONFIG_SF_DEFAULT_MODE    0
 524
 525 /*
 526  * General PCIe
 527  * Memory space is mapped 1-1, but I/O space must start from 0.
 528  */
 529 #define CONFIG_PCIE1            /* PCIE controller 1 */
 530 #define CONFIG_PCIE2            /* PCIE controller 2 */
 531 #define CONFIG_PCIE3            /* PCIE controller 3 */
 532 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 533 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 534 #define CONFIG_PCI_INDIRECT_BRIDGE
 535
 536 #ifdef CONFIG_PCI
 537 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 538 #ifdef CONFIG_PCIE1
 539 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 542 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 543 #else
 544 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 545 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 546 #endif
 547 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 548 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 549 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 552 #else
 553 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 554 #endif
 555 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 556 #endif
 557
 558 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 559 #ifdef CONFIG_PCIE2
 560 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 561 #ifdef CONFIG_PHYS_64BIT
 562 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 563 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 564 #else
 565 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 566 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 567 #endif
 568 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 569 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 570 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 571 #ifdef CONFIG_PHYS_64BIT
 572 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 573 #else
 574 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 575 #endif
 576 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 577 #endif
 578
 579 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 580 #ifdef CONFIG_PCIE3
 581 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 582 #ifdef CONFIG_PHYS_64BIT
 583 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 584 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 585 #else
 586 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 587 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 588 #endif
 589 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 590 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 591 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 592 #ifdef CONFIG_PHYS_64BIT
 593 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 594 #else
 595 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 596 #endif
 597 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 598 #endif
 599
 600 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 601 #endif  /* CONFIG_PCI */
 602
 603 /*
 604  *SATA
 605  */
 606 #define CONFIG_FSL_SATA_V2
 607 #ifdef CONFIG_FSL_SATA_V2
 608 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 609 #define CONFIG_SATA1
 610 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 611 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 612 #define CONFIG_LBA48
 613 #endif
 614
 615 /*
 616  * USB
 617  */
 618 #define CONFIG_HAS_FSL_DR_USB
 619
 620 #ifdef CONFIG_HAS_FSL_DR_USB
 621 #define CONFIG_USB_EHCI_FSL
 622 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 623 #endif
 624
 625 /*
 626  * SDHC
 627  */
 628 #ifdef CONFIG_MMC
 629 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 630 #endif
 631
 632 /* Qman/Bman */
 633 #ifndef CONFIG_NOBQFMAN
 634 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 635 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 636 #ifdef CONFIG_PHYS_64BIT
 637 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 638 #else
 639 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 640 #endif
 641 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 642 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 643 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 644 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 645 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 646 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 647                                         CONFIG_SYS_BMAN_CENA_SIZE)
 648 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 649 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 650 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 651 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 652 #ifdef CONFIG_PHYS_64BIT
 653 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 654 #else
 655 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 656 #endif
 657 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 658 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 659 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 660 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 661 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 662 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 663                                         CONFIG_SYS_QMAN_CENA_SIZE)
 664 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 665 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 666
 667 #define CONFIG_SYS_DPAA_FMAN
 668
 669 #define CONFIG_QE
 670 #define CONFIG_U_QE
 671 /* Default address of microcode for the Linux FMan driver */
 672 #if defined(CONFIG_SPIFLASH)
 673 /*
 674  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 675  * env, so we got 0x110000.
 676  */
 677 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 678 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 679 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 680 #elif defined(CONFIG_SDCARD)
 681 /*
 682  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 683  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 684  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 685  */
 686 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 687 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 688 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 689 #elif defined(CONFIG_NAND)
 690 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 691 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 692 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 693 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 694 /*
 695  * Slave has no ucode locally, it can fetch this from remote. When implementing
 696  * in two corenet boards, slave's ucode could be stored in master's memory
 697  * space, the address can be mapped from slave TLB->slave LAW->
 698  * slave SRIO or PCIE outbound window->master inbound window->
 699  * master LAW->the ucode address in master's memory space.
 700  */
 701 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 702 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 703 #else
 704 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 705 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 706 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 707 #endif
 708 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 709 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 710 #endif /* CONFIG_NOBQFMAN */
 711
 712 #ifdef CONFIG_SYS_DPAA_FMAN
 713 #define CONFIG_FMAN_ENET
 714 #define CONFIG_PHYLIB_10G
 715 #define CONFIG_PHY_VITESSE
 716 #define CONFIG_PHY_REALTEK
 717 #define CONFIG_PHY_TERANETICS
 718 #define RGMII_PHY1_ADDR         0x1
 719 #define RGMII_PHY2_ADDR         0x2
 720 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 721 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 722 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 723 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 724 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 725 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 726 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 727 #endif
 728
 729 #ifdef CONFIG_FMAN_ENET
 730 #define CONFIG_MII              /* MII PHY management */
 731 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 732 #endif
 733
 734 /*
 735  * Dynamic MTD Partition support with mtdparts
 736  */
 737 #ifdef CONFIG_MTD_NOR_FLASH
 738 #define CONFIG_MTD_DEVICE
 739 #define CONFIG_MTD_PARTITIONS
 740 #define CONFIG_FLASH_CFI_MTD
 741 #endif
 742
 743 /*
 744  * Environment
 745  */
 746 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 747 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 748
 749 /*
 750  * Miscellaneous configurable options
 751  */
 752 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 753
 754 /*
 755  * For booting Linux, the board info and command line data
 756  * have to be in the first 64 MB of memory, since this is
 757  * the maximum mapped by the Linux kernel during initialization.
 758  */
 759 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 760 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 761
 762 #ifdef CONFIG_CMD_KGDB
 763 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 764 #endif
 765
 766 /*
 767  * Environment Configuration
 768  */
 769 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 770 #define CONFIG_BOOTFILE         "uImage"
 771 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 772 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 773 #define __USB_PHY_TYPE          utmi
 774
 775 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 776         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 777         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 778         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 779         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 780         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 781         "netdev=eth0\0"                                         \
 782         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 783         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 784         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 785         "tftpflash=tftpboot $loadaddr $uboot && "               \
 786         "protect off $ubootaddr +$filesize && "                 \
 787         "erase $ubootaddr +$filesize && "                       \
 788         "cp.b $loadaddr $ubootaddr $filesize && "               \
 789         "protect on $ubootaddr +$filesize && "                  \
 790         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 791         "consoledev=ttyS0\0"                                    \
 792         "ramdiskaddr=2000000\0"                                 \
 793         "fdtaddr=d00000\0"                                      \
 794         "bdev=sda3\0"
 795
 796 #define CONFIG_LINUX                                    \
 797         "setenv bootargs root=/dev/ram rw "             \
 798         "console=$consoledev,$baudrate $othbootargs;"   \
 799         "setenv ramdiskaddr 0x02000000;"                \
 800         "setenv fdtaddr 0x00c00000;"                    \
 801         "setenv loadaddr 0x1000000;"                    \
 802         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 803
 804 #define CONFIG_NFSBOOTCOMMAND                   \
 805         "setenv bootargs root=/dev/nfs rw "     \
 806         "nfsroot=$serverip:$rootpath "          \
 807         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 808         "console=$consoledev,$baudrate $othbootargs;"   \
 809         "tftp $loadaddr $bootfile;"             \
 810         "tftp $fdtaddr $fdtfile;"               \
 811         "bootm $loadaddr - $fdtaddr"
 812
 813 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 814
 815 #include <asm/fsl_secure_boot.h>
 816
 817 #endif  /* __T1024QDS_H */