include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 QDS board configuration file
   8  */
   9
  10 #ifndef __T1024QDS_H
  11 #define __T1024QDS_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 #define CONFIG_DEEP_SLEEP
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_PAD_TO               0x40000
  33 #define CONFIG_SPL_MAX_SIZE             0x28000
  34 #define RESET_VECTOR_OFFSET             0x27FFC
  35 #define BOOT_PAGE_OFFSET                0x27000
  36 #ifdef CONFIG_SPL_BUILD
  37 #define CONFIG_SPL_SKIP_RELOCATE
  38 #define CONFIG_SPL_COMMON_INIT_DDR
  39 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  40 #endif
  41
  42 #ifdef CONFIG_NAND
  43 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  44 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  45 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  47 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  49 #endif
  50
  51 #ifdef CONFIG_SPIFLASH
  52 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  58 #ifndef CONFIG_SPL_BUILD
  59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60 #endif
  61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  62 #endif
  63
  64 #ifdef CONFIG_SDCARD
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  66 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  67 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  68 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  70 #ifndef CONFIG_SPL_BUILD
  71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72 #endif
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  74 #endif
  75
  76 #endif /* CONFIG_RAMBOOT_PBL */
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /* PCIe Boot - Master */
  83 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  84 /*
  85  * for slave u-boot IMAGE instored in master memory space,
  86  * PHYS must be aligned based on the SIZE
  87  */
  88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  89 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  92 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  93 #else
  94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  96 #endif
  97 /*
  98  * for slave UCODE and ENV instored in master memory space,
  99  * PHYS must be aligned based on the SIZE
 100  */
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 103 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 104 #else
 105 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 106 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 107 #endif
 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 109 /* slave core release by master*/
 110 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 111 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 112
 113 /* PCIe Boot - Slave */
 114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 117                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 118 /* Set 1M boot space for PCIe boot */
 119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 121                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 123 #endif
 124
 125 #if defined(CONFIG_SPIFLASH)
 126 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 127 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 128 #define CONFIG_ENV_SECT_SIZE            0x10000
 129 #elif defined(CONFIG_SDCARD)
 130 #define CONFIG_SYS_MMC_ENV_DEV          0
 131 #define CONFIG_ENV_SIZE                 0x2000
 132 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 133 #elif defined(CONFIG_NAND)
 134 #define CONFIG_ENV_SIZE                 0x2000
 135 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 136 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 137 #define CONFIG_ENV_ADDR         0xffe20000
 138 #define CONFIG_ENV_SIZE         0x2000
 139 #elif defined(CONFIG_ENV_IS_NOWHERE)
 140 #define CONFIG_ENV_SIZE         0x2000
 141 #else
 142 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 143 #define CONFIG_ENV_SIZE         0x2000
 144 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 145 #endif
 146
 147 #ifndef __ASSEMBLY__
 148 unsigned long get_board_sys_clk(void);
 149 unsigned long get_board_ddr_clk(void);
 150 #endif
 151
 152 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 153 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 154
 155 /*
 156  * These can be toggled for performance analysis, otherwise use default.
 157  */
 158 #define CONFIG_SYS_CACHE_STASHING
 159 #define CONFIG_BACKSIDE_L2_CACHE
 160 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 161 #define CONFIG_BTB                      /* toggle branch predition */
 162 #define CONFIG_DDR_ECC
 163 #ifdef CONFIG_DDR_ECC
 164 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 165 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 166 #endif
 167
 168 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 169 #define CONFIG_SYS_MEMTEST_END          0x00400000
 170
 171 /*
 172  *  Config the L3 Cache as L3 SRAM
 173  */
 174 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 175 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 176 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 177 #ifdef CONFIG_RAMBOOT_PBL
 178 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 179 #endif
 180 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 181 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 182 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 183
 184 #ifdef CONFIG_PHYS_64BIT
 185 #define CONFIG_SYS_DCSRBAR              0xf0000000
 186 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 187 #endif
 188
 189 /* EEPROM */
 190 #define CONFIG_ID_EEPROM
 191 #define CONFIG_SYS_I2C_EEPROM_NXID
 192 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 193 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 197
 198 /*
 199  * DDR Setup
 200  */
 201 #define CONFIG_VERY_BIG_RAM
 202 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 203 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 204 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 205 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 206 #define CONFIG_DDR_SPD
 207
 208 #define CONFIG_SYS_SPD_BUS_NUM  0
 209 #define SPD_EEPROM_ADDRESS      0x51
 210
 211 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 212
 213 /*
 214  * IFC Definitions
 215  */
 216 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 217 #ifdef CONFIG_PHYS_64BIT
 218 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 219 #else
 220 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 221 #endif
 222
 223 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 224 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 225                                 + 0x8000000) | \
 226                                 CSPR_PORT_SIZE_16 | \
 227                                 CSPR_MSEL_NOR | \
 228                                 CSPR_V)
 229 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 230 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 231                                 CSPR_PORT_SIZE_16 | \
 232                                 CSPR_MSEL_NOR | \
 233                                 CSPR_V)
 234 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 235 /* NOR Flash Timing Params */
 236 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 237 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 238                                 FTIM0_NOR_TEADC(0x5) | \
 239                                 FTIM0_NOR_TEAHC(0x5))
 240 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 241                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 242                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 243 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 244                                 FTIM2_NOR_TCH(0x4) | \
 245                                 FTIM2_NOR_TWPH(0x0E) | \
 246                                 FTIM2_NOR_TWP(0x1c))
 247 #define CONFIG_SYS_NOR_FTIM3    0x0
 248
 249 #define CONFIG_SYS_FLASH_QUIET_TEST
 250 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 251
 252 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 253 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 254 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 255 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 256
 257 #define CONFIG_SYS_FLASH_EMPTY_INFO
 258 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 259                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 260 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 261 #define QIXIS_BASE              0xffdf0000
 262 #ifdef CONFIG_PHYS_64BIT
 263 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 264 #else
 265 #define QIXIS_BASE_PHYS         QIXIS_BASE
 266 #endif
 267 #define QIXIS_LBMAP_SWITCH              0x06
 268 #define QIXIS_LBMAP_MASK                0x0f
 269 #define QIXIS_LBMAP_SHIFT               0
 270 #define QIXIS_LBMAP_DFLTBANK            0x00
 271 #define QIXIS_LBMAP_ALTBANK             0x04
 272 #define QIXIS_RST_CTL_RESET             0x31
 273 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 274 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 275 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 276 #define QIXIS_RST_FORCE_MEM             0x01
 277
 278 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 279 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 280                                 | CSPR_PORT_SIZE_8 \
 281                                 | CSPR_MSEL_GPCM \
 282                                 | CSPR_V)
 283 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 284 #define CONFIG_SYS_CSOR3        0x0
 285 /* QIXIS Timing parameters for IFC CS3 */
 286 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 287                                         FTIM0_GPCM_TEADC(0x0e) | \
 288                                         FTIM0_GPCM_TEAHC(0x0e))
 289 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 290                                         FTIM1_GPCM_TRAD(0x3f))
 291 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 292                                         FTIM2_GPCM_TCH(0x8) | \
 293                                         FTIM2_GPCM_TWP(0x1f))
 294 #define CONFIG_SYS_CS3_FTIM3            0x0
 295
 296 #define CONFIG_NAND_FSL_IFC
 297 #define CONFIG_SYS_NAND_BASE            0xff800000
 298 #ifdef CONFIG_PHYS_64BIT
 299 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 300 #else
 301 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 302 #endif
 303 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 304 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 305                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 306                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 307                                 | CSPR_V)
 308 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 309
 310 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 311                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 312                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 313                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 314                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 315                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 316                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 317
 318 #define CONFIG_SYS_NAND_ONFI_DETECTION
 319
 320 /* ONFI NAND Flash mode0 Timing Params */
 321 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 322                                         FTIM0_NAND_TWP(0x18)   | \
 323                                         FTIM0_NAND_TWCHT(0x07) | \
 324                                         FTIM0_NAND_TWH(0x0a))
 325 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 326                                         FTIM1_NAND_TWBE(0x39)  | \
 327                                         FTIM1_NAND_TRR(0x0e)   | \
 328                                         FTIM1_NAND_TRP(0x18))
 329 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 330                                         FTIM2_NAND_TREH(0x0a) | \
 331                                         FTIM2_NAND_TWHRE(0x1e))
 332 #define CONFIG_SYS_NAND_FTIM3           0x0
 333
 334 #define CONFIG_SYS_NAND_DDR_LAW         11
 335 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 336 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 337
 338 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 339
 340 #if defined(CONFIG_NAND)
 341 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 342 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 343 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 344 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 345 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 346 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 347 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 348 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 349 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 350 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 351 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 352 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 353 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 354 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 355 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 356 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 357 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 358 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 359 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 360 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 361 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 362 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 363 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 364 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 365 #else
 366 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 367 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 368 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 369 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 370 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 371 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 372 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 373 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 374 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 375 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 376 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 377 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 378 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 379 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 380 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 381 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 382 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 383 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 384 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 385 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 386 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 387 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 388 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 389 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 390 #endif
 391
 392 #ifdef CONFIG_SPL_BUILD
 393 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 394 #else
 395 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 396 #endif
 397
 398 #if defined(CONFIG_RAMBOOT_PBL)
 399 #define CONFIG_SYS_RAMBOOT
 400 #endif
 401
 402 #define CONFIG_HWCONFIG
 403
 404 /* define to use L1 as initial stack */
 405 #define CONFIG_L1_INIT_RAM
 406 #define CONFIG_SYS_INIT_RAM_LOCK
 407 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 408 #ifdef CONFIG_PHYS_64BIT
 409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 411 /* The assembler doesn't like typecast */
 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 413         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 414           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 415 #else
 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 419 #endif
 420 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 421
 422 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 423                                         GENERATED_GBL_DATA_SIZE)
 424 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 425
 426 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 427 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 428
 429 /* Serial Port */
 430 #define CONFIG_SYS_NS16550_SERIAL
 431 #define CONFIG_SYS_NS16550_REG_SIZE     1
 432 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 433
 434 #define CONFIG_SYS_BAUDRATE_TABLE       \
 435         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 436
 437 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 438 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 439 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 440 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 441
 442 /* Video */
 443 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 444 #define CONFIG_FSL_DIU_FB
 445 #ifdef CONFIG_FSL_DIU_FB
 446 #define CONFIG_FSL_DIU_CH7301
 447 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 448 #define CONFIG_VIDEO_LOGO
 449 #define CONFIG_VIDEO_BMP_LOGO
 450 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 451 /*
 452  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 453  * disable empty flash sector detection, which is I/O-intensive.
 454  */
 455 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 456 #endif
 457 #endif
 458
 459 /* I2C */
 460 #define CONFIG_SYS_I2C
 461 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 462 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 463 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 464 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 465 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 466 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 467 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 468
 469 #define I2C_MUX_PCA_ADDR                0x77
 470 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 471 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 472 #define I2C_RETIMER_ADDR                0x18
 473
 474 /* I2C bus multiplexer */
 475 #define I2C_MUX_CH_DEFAULT      0x8
 476 #define I2C_MUX_CH_DIU          0xC
 477 #define I2C_MUX_CH5             0xD
 478 #define I2C_MUX_CH7             0xF
 479
 480 /* LDI/DVI Encoder for display */
 481 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 482 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 483
 484 /*
 485  * RTC configuration
 486  */
 487 #define RTC
 488 #define CONFIG_RTC_DS3231       1
 489 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 490
 491 /*
 492  * eSPI - Enhanced SPI
 493  */
 494
 495 /*
 496  * General PCIe
 497  * Memory space is mapped 1-1, but I/O space must start from 0.
 498  */
 499 #define CONFIG_PCIE1            /* PCIE controller 1 */
 500 #define CONFIG_PCIE2            /* PCIE controller 2 */
 501 #define CONFIG_PCIE3            /* PCIE controller 3 */
 502 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 503 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 504 #define CONFIG_PCI_INDIRECT_BRIDGE
 505
 506 #ifdef CONFIG_PCI
 507 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 508 #ifdef CONFIG_PCIE1
 509 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 510 #ifdef CONFIG_PHYS_64BIT
 511 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 512 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 513 #else
 514 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 515 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 516 #endif
 517 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 518 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 519 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 520 #ifdef CONFIG_PHYS_64BIT
 521 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 522 #else
 523 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 524 #endif
 525 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 526 #endif
 527
 528 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 529 #ifdef CONFIG_PCIE2
 530 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 533 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 534 #else
 535 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 536 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 537 #endif
 538 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 539 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 540 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 541 #ifdef CONFIG_PHYS_64BIT
 542 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 543 #else
 544 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 545 #endif
 546 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 547 #endif
 548
 549 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 550 #ifdef CONFIG_PCIE3
 551 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 552 #ifdef CONFIG_PHYS_64BIT
 553 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 554 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 555 #else
 556 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 557 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 558 #endif
 559 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 560 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 561 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 562 #ifdef CONFIG_PHYS_64BIT
 563 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 564 #else
 565 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 566 #endif
 567 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 568 #endif
 569
 570 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 571 #endif  /* CONFIG_PCI */
 572
 573 /*
 574  *SATA
 575  */
 576 #define CONFIG_FSL_SATA_V2
 577 #ifdef CONFIG_FSL_SATA_V2
 578 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 579 #define CONFIG_SATA1
 580 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 581 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 582 #define CONFIG_LBA48
 583 #endif
 584
 585 /*
 586  * USB
 587  */
 588 #define CONFIG_HAS_FSL_DR_USB
 589
 590 #ifdef CONFIG_HAS_FSL_DR_USB
 591 #define CONFIG_USB_EHCI_FSL
 592 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 593 #endif
 594
 595 /*
 596  * SDHC
 597  */
 598 #ifdef CONFIG_MMC
 599 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 600 #endif
 601
 602 /* Qman/Bman */
 603 #ifndef CONFIG_NOBQFMAN
 604 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 605 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 606 #ifdef CONFIG_PHYS_64BIT
 607 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 608 #else
 609 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 610 #endif
 611 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 612 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 613 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 614 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 615 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 616 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 617                                         CONFIG_SYS_BMAN_CENA_SIZE)
 618 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 619 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 620 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 621 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 622 #ifdef CONFIG_PHYS_64BIT
 623 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 624 #else
 625 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 626 #endif
 627 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 628 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 629 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 630 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 631 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 632 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 633                                         CONFIG_SYS_QMAN_CENA_SIZE)
 634 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 635 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 636
 637 #define CONFIG_SYS_DPAA_FMAN
 638
 639 /* Default address of microcode for the Linux FMan driver */
 640 #if defined(CONFIG_SPIFLASH)
 641 /*
 642  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 643  * env, so we got 0x110000.
 644  */
 645 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 646 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 647 #elif defined(CONFIG_SDCARD)
 648 /*
 649  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 650  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 651  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 652  */
 653 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 654 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 655 #elif defined(CONFIG_NAND)
 656 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 657 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 658 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 659 /*
 660  * Slave has no ucode locally, it can fetch this from remote. When implementing
 661  * in two corenet boards, slave's ucode could be stored in master's memory
 662  * space, the address can be mapped from slave TLB->slave LAW->
 663  * slave SRIO or PCIE outbound window->master inbound window->
 664  * master LAW->the ucode address in master's memory space.
 665  */
 666 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 667 #else
 668 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 669 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 670 #endif
 671 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 672 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 673 #endif /* CONFIG_NOBQFMAN */
 674
 675 #ifdef CONFIG_SYS_DPAA_FMAN
 676 #define CONFIG_PHYLIB_10G
 677 #define CONFIG_PHY_VITESSE
 678 #define CONFIG_PHY_REALTEK
 679 #define CONFIG_PHY_TERANETICS
 680 #define RGMII_PHY1_ADDR         0x1
 681 #define RGMII_PHY2_ADDR         0x2
 682 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 683 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 684 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 685 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 686 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 687 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 688 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 689 #endif
 690
 691 #ifdef CONFIG_FMAN_ENET
 692 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 693 #endif
 694
 695 /*
 696  * Dynamic MTD Partition support with mtdparts
 697  */
 698
 699 /*
 700  * Environment
 701  */
 702 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 703 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 704
 705 /*
 706  * Miscellaneous configurable options
 707  */
 708 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 709
 710 /*
 711  * For booting Linux, the board info and command line data
 712  * have to be in the first 64 MB of memory, since this is
 713  * the maximum mapped by the Linux kernel during initialization.
 714  */
 715 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 716 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 717
 718 #ifdef CONFIG_CMD_KGDB
 719 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 720 #endif
 721
 722 /*
 723  * Environment Configuration
 724  */
 725 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 726 #define CONFIG_BOOTFILE         "uImage"
 727 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 728 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 729 #define __USB_PHY_TYPE          utmi
 730
 731 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 732         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 733         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 734         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 735         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 736         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 737         "netdev=eth0\0"                                         \
 738         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 739         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 740         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 741         "tftpflash=tftpboot $loadaddr $uboot && "               \
 742         "protect off $ubootaddr +$filesize && "                 \
 743         "erase $ubootaddr +$filesize && "                       \
 744         "cp.b $loadaddr $ubootaddr $filesize && "               \
 745         "protect on $ubootaddr +$filesize && "                  \
 746         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 747         "consoledev=ttyS0\0"                                    \
 748         "ramdiskaddr=2000000\0"                                 \
 749         "fdtaddr=d00000\0"                                      \
 750         "bdev=sda3\0"
 751
 752 #define CONFIG_LINUX                                    \
 753         "setenv bootargs root=/dev/ram rw "             \
 754         "console=$consoledev,$baudrate $othbootargs;"   \
 755         "setenv ramdiskaddr 0x02000000;"                \
 756         "setenv fdtaddr 0x00c00000;"                    \
 757         "setenv loadaddr 0x1000000;"                    \
 758         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 759
 760 #define CONFIG_NFSBOOTCOMMAND                   \
 761         "setenv bootargs root=/dev/nfs rw "     \
 762         "nfsroot=$serverip:$rootpath "          \
 763         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 764         "console=$consoledev,$baudrate $othbootargs;"   \
 765         "tftp $loadaddr $bootfile;"             \
 766         "tftp $fdtaddr $fdtfile;"               \
 767         "bootm $loadaddr - $fdtaddr"
 768
 769 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 770
 771 #include <asm/fsl_secure_boot.h>
 772
 773 #endif  /* __T1024QDS_H */