include/configs/SIMPC8313.h

   1 /*
   2  * Copyright (C) Sheldon Instruments, Inc. 2008
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * simpc8313 board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_NAND_U_BOOT
  33
  34 #define CONFIG_E300                     1
  35 #define CONFIG_MPC83xx                  1
  36 #define CONFIG_MPC831x                  1
  37 #define CONFIG_MPC8313                  1
  38
  39 #ifndef CONFIG_SYS_TEXT_BASE
  40 #define CONFIG_SYS_TEXT_BASE    0x00100000
  41 #endif
  42
  43 #define CONFIG_PCI
  44 #define CONFIG_FSL_ELBC                 1
  45
  46 #define CONFIG_MISC_INIT_R
  47
  48 /*
  49  * On-board devices
  50  *
  51  * TSEC1 is Marvell PHY 88E1118
  52  */
  53
  54 #define CONFIG_SYS_33MHZ
  55
  56 #define CONFIG_83XX_CLKIN               33333333        /* in Hz */
  57
  58 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  59
  60 #define CONFIG_SYS_IMMR                 0xE0000000
  61
  62 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  63 #define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
  64 #endif
  65
  66 #define CONFIG_SYS_MEMTEST_START        0x00001000
  67 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  68
  69 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth (0-3) */
  70 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  71
  72 /*
  73  * Device configurations
  74  */
  75 #define CONFIG_TSEC1
  76
  77 /*
  78  * DDR Setup
  79  */
  80 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  83
  84 #define CONFIG_VERY_BIG_RAM
  85 #define CONFIG_MAX_MEM_MAPPED           (512 << 20)
  86
  87 #define CONFIG_SYS_DDRCDR               ( DDRCDR_EN \
  88                                         | DDRCDR_PZ_NOMZ \
  89                                         | DDRCDR_NZ_NOMZ \
  90                                         | DDRCDR_M_ODR )
  91                                         /* 0x73000002 TODO ODR & DRN ? */
  92
  93 /*
  94  * FLASH on the Local Bus
  95  */
  96 #define CONFIG_SYS_NO_FLASH
  97
  98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  99
 100 #if !defined(CONFIG_NAND_SPL)
 101 #define CONFIG_SYS_RAMBOOT
 102 #endif
 103
 104 #define CONFIG_SYS_INIT_RAM_LOCK        1
 105 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
 106 #define CONFIG_SYS_INIT_RAM_END         0x1000          /* End of used area in RAM*/
 107
 108 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 109 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 110 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 111
 112 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 113 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 114 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 115
 116 /*
 117  * Local Bus LCRR and LBCR regs
 118  */
 119 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 120 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 121 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 122 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 123                                 | (0xFF << LBCR_BMT_SHIFT) \
 124                                 | 0xF ) /* 0x0004ff0f */
 125
 126 #define CONFIG_SYS_LBC_MRTPR    0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 127
 128 /* drivers/mtd/nand/nand.c */
 129 #ifdef CONFIG_NAND_SPL
 130 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 131 #else
 132 #define CONFIG_SYS_NAND_BASE            0xE2800000
 133 #endif
 134 #define CONFIG_SYS_FPGA_BASE            0xFF000000
 135
 136 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 137 #define NAND_MAX_CHIPS                  1
 138 #define CONFIG_MTD_NAND_VERIFY_WRITE
 139 #define CONFIG_CMD_NAND                 1
 140 #define CONFIG_NAND_FSL_ELBC            1
 141
 142 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
 143 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
 144 #define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
 145 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
 146 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 147
 148 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
 149                                         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 150                                         | BR_PS_8               /* Port Size = 8 bit */ \
 151                                         | BR_MS_FCM             /* MSEL = FCM */ \
 152                                         | BR_V )                /* valid */
 153
 154 #ifdef CONFIG_NAND_SP
 155 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFF8000    /* length 32K */ \
 156                                         | OR_FCM_CSCT \
 157                                         | OR_FCM_CST \
 158                                         | OR_FCM_CHT \
 159                                         | OR_FCM_SCY_1 \
 160                                         | OR_FCM_TRLX \
 161                                         | OR_FCM_EHTR )
 162 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000000E      /* 32KB */
 163 #define CONFIG_SYS_NAND_PAGE_SIZE       (512)           /* NAND chip page size */
 164 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size */
 165 #define NAND_CACHE_PAGES                32
 166 #elif defined(CONFIG_NAND_LP)
 167 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFC0000    /* length 256K */ \
 168                                         | OR_FCM_PGS \
 169                                         | OR_FCM_CSCT \
 170                                         | OR_FCM_CST \
 171                                         | OR_FCM_CHT \
 172                                         | OR_FCM_SCY_1 \
 173                                         | OR_FCM_TRLX \
 174                                         | OR_FCM_EHTR )
 175 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000011      /* 256KB */
 176 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)          /* NAND chip page size */
 177 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size */
 178 #define NAND_CACHE_PAGES                64
 179 #else
 180 #error Page size of NAND not defined.
 181 #endif /* CONFIG_NAND_SP */
 182
 183 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 184
 185 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 186 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 187
 188 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 189
 190 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 191 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 192
 193 #define CONFIG_SYS_BR1_PRELIM           ( CONFIG_SYS_FPGA_BASE \
 194                                         | BR_PS_16 \
 195                                         | BR_MS_UPMA \
 196                                         | BR_V )
 197 #define CONFIG_SYS_OR1_PRELIM           ( OR_AM_2MB \
 198                                         | OR_UPM_BCTLD)
 199
 200 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA_BASE
 201 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_2MB)
 202
 203 /*
 204  * JFFS2 configuration
 205  */
 206 #define CONFIG_JFFS2_NAND
 207 #define CONFIG_JFFS2_DEV        "nand0"
 208
 209 /* mtdparts command line support */
 210 #define CONFIG_CMD_MTDPARTS
 211 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 212 #define MTDIDS_DEFAULT          "nand0=nand0"
 213 #define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 214
 215 /* pass open firmware flat tree */
 216 #define CONFIG_OF_LIBFDT                1
 217 #define CONFIG_OF_BOARD_SETUP           1
 218 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 219
 220 /*
 221  * Serial Port
 222  */
 223 #define CONFIG_CONS_INDEX               1
 224 #define CONFIG_SYS_NS16550
 225 #define CONFIG_SYS_NS16550_SERIAL
 226 #define CONFIG_SYS_NS16550_REG_SIZE     1
 227 #ifdef CONFIG_NAND_SPL
 228 #define CONFIG_NS16550_MIN_FUNCTIONS
 229 #endif
 230
 231 #define CONFIG_SYS_BAUDRATE_TABLE       \
 232         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 233
 234 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 235 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 236
 237 /* Use the HUSH parser */
 238 #define CONFIG_SYS_HUSH_PARSER
 239 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 240
 241 /* I2C */
 242 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 243 #define CONFIG_FSL_I2C
 244 #define CONFIG_I2C_MULTI_BUS
 245 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 246 #define CONFIG_SYS_I2C_SLAVE            0x7F
 247 #define CONFIG_SYS_I2C_NOPROBES         {{0,0x69}} /* Don't probe these addrs */
 248 #define CONFIG_SYS_I2C_OFFSET           0x3000
 249 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 250
 251 /*
 252  * General PCI
 253  * Addresses are mapped 1-1.
 254  */
 255 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 256 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 257 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 258 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 259 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 260 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 261 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 262 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 263 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 264
 265 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 266 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 267
 268 /*
 269  * TSEC
 270  */
 271 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 272
 273 #define CONFIG_NET_MULTI
 274 #define CONFIG_GMII                     /* MII PHY management */
 275
 276 #ifdef CONFIG_TSEC1
 277 #define CONFIG_HAS_ETH0
 278 #define CONFIG_TSEC1_NAME               "TSEC0"
 279 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 280 #define TSEC1_PHY_ADDR                  0x0
 281 #define TSEC1_FLAGS                     TSEC_GIGABIT
 282 #define TSEC1_PHYIDX                    0
 283 #endif
 284
 285 #ifdef CONFIG_TSEC2
 286 #define CONFIG_HAS_ETH1
 287 #define CONFIG_TSEC2_NAME               "TSEC1"
 288 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 289 #define TSEC2_PHY_ADDR                  4
 290 #define TSEC2_FLAGS                     TSEC_GIGABIT
 291 #define TSEC2_PHYIDX                    0
 292 #endif
 293
 294
 295 /* Options are: TSEC[0-1] */
 296 #define CONFIG_ETHPRIME                 "TSEC1"
 297
 298 /*
 299  * Configure on-board RTC
 300  */
 301 #define CONFIG_RTC_DS1337
 302 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 303
 304 /*
 305  * Environment
 306  */
 307 #if defined(CONFIG_NAND_U_BOOT)
 308         #define CONFIG_ENV_IS_IN_NAND           1
 309         #define CONFIG_ENV_OFFSET               (768 * 1024)
 310         #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_NAND_BLOCK_SIZE
 311         #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
 312         #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 313         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 314         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 315 #elif !defined(CONFIG_SYS_RAMBOOT)
 316         #define CONFIG_ENV_IS_IN_FLASH          1
 317         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 318         #define CONFIG_ENV_SECT_SIZE            0x10000 /* 64K(one sector) for env */
 319         #define CONFIG_ENV_SIZE                 0x2000
 320
 321 /* Address and size of Redundant Environment Sector */
 322 #else
 323         #define CONFIG_ENV_IS_NOWHERE           1       /* Store ENV in memory only */
 324         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 325         #define CONFIG_ENV_SIZE                 0x2000
 326 #endif
 327
 328 #define CONFIG_LOADS_ECHO                       1       /* echo on for serial download */
 329 #define CONFIG_SYS_LOADS_BAUD_CHANGE            1       /* allow baudrate change */
 330
 331 /*
 332  * BOOTP options
 333  */
 334 #define CONFIG_BOOTP_BOOTFILESIZE
 335 #define CONFIG_BOOTP_BOOTPATH
 336 #define CONFIG_BOOTP_GATEWAY
 337 #define CONFIG_BOOTP_HOSTNAME
 338
 339
 340 /*
 341  * Command line configuration.
 342  */
 343 #include <config_cmd_default.h>
 344 #undef CONFIG_CMD_IMLS
 345 #undef CONFIG_CMD_FLASH
 346
 347 #define CONFIG_CMD_PING
 348 #define CONFIG_CMD_DHCP
 349 #define CONFIG_CMD_I2C
 350 #define CONFIG_CMD_MII
 351 #define CONFIG_CMD_DATE
 352 #define CONFIG_CMD_PCI
 353 #define CONFIG_CMD_JFFS2
 354
 355 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 356         #undef CONFIG_CMD_SAVEENV
 357         #undef CONFIG_CMD_LOADS
 358 #endif
 359
 360 #define CONFIG_CMDLINE_EDITING          1
 361 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 362
 363 /*
 364  * Miscellaneous configurable options
 365  */
 366 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 367 #define CONFIG_SYS_LOAD_ADDR            0x2000000       /* default load address */
 368 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 369 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size */
 370
 371 #define CONFIG_SYS_PBSIZE               ( CONFIG_SYS_CBSIZE             \
 372                                         + sizeof(CONFIG_SYS_PROMPT)     \
 373                                         + 16 )  /* Print Buffer Size */
 374 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 375 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 376 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1ms ticks */
 377
 378 /*
 379  * For booting Linux, the board info and command line data
 380  * have to be in the first 256 MB of memory, since this is
 381  * the maximum mapped by the Linux kernel during initialization.
 382  */
 383 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)     /* Initial Memory map for Linux*/
 384
 385 #define CONFIG_SYS_RCWH_PCIHOST         0x80000000      /* PCIHOST */
 386
 387 #define CONFIG_SYS_HRCW_LOW             ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1  \
 388                                         | 0x20000000 /* reserved */     \
 389                                         | HRCWL_DDR_TO_SCB_CLK_2X1      \
 390                                         | HRCWL_CSB_TO_CLKIN_4X1        \
 391                                         | HRCWL_CORE_TO_CSB_2_5X1 )
 392
 393 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 4)
 394
 395 #define CONFIG_SYS_HRCW_HIGH_BASE       ( HRCWH_PCI_HOST                \
 396                                         | HRCWH_PCI1_ARBITER_ENABLE     \
 397                                         | HRCWH_CORE_ENABLE             \
 398                                         | HRCWH_BOOTSEQ_DISABLE         \
 399                                         | HRCWH_SW_WATCHDOG_DISABLE     \
 400                                         | HRCWH_TSEC1M_IN_RGMII         \
 401                                         | HRCWH_TSEC2M_IN_RGMII         \
 402                                         | HRCWH_BIG_ENDIAN              \
 403                                         | HRCWH_LALE_NORMAL )
 404
 405 #ifdef CONFIG_NAND_LP
 406 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 407                                 | HRCWH_FROM_0XFFF00100                 \
 408                                 | HRCWH_ROM_LOC_NAND_LP_8BIT            \
 409                                 | HRCWH_RL_EXT_NAND)
 410 #else
 411 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 412                                 | HRCWH_FROM_0XFFF00100                 \
 413                                 | HRCWH_ROM_LOC_NAND_SP_8BIT            \
 414                                 | HRCWH_RL_EXT_NAND )
 415 #endif
 416
 417 /* System IO Config */
 418 #define CONFIG_SYS_SICRH        ( SICRH_ETSEC2_B        \
 419                                 | SICRH_ETSEC2_C        \
 420                                 | SICRH_ETSEC2_D        \
 421                                 | SICRH_ETSEC2_E        \
 422                                 | SICRH_ETSEC2_F        \
 423                                 | SICRH_ETSEC2_G        \
 424                                 | SICRH_TSOBI1          \
 425                                 | SICRH_TSOBI2 )
 426 #define CONFIG_SYS_SICRL        ( SICRL_LBC             \
 427                                 | SICRL_USBDR_10        \
 428                                 | SICRL_ETSEC2_A )
 429
 430 #define CONFIG_SYS_HID0_INIT    0x000000000
 431 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 432                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 433                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 434
 435 #define CONFIG_SYS_HID2         HID2_HBE
 436
 437 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 438
 439 /* DDR @ 0x00000000 */
 440 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 441 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 442 #define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
 443 #define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
 444
 445 /* PCI @ 0x80000000 */
 446 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 447 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 448 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 449 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 450
 451 /* PCI2 not supported on 8313 */
 452 #define CONFIG_SYS_IBAT4L       (0)
 453 #define CONFIG_SYS_IBAT4U       (0)
 454
 455 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 456 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 457 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 458
 459 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 460 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 461 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 462
 463 #define CONFIG_SYS_IBAT7L       (0)
 464 #define CONFIG_SYS_IBAT7U       (0)
 465
 466 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 467 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 468 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 469 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 470 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 471 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 472 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 473 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 474 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 475 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 476 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 477 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 478 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 479 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 480 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 481 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 482
 483 /*
 484  * Environment Configuration
 485  */
 486 #define CONFIG_ENV_OVERWRITE
 487
 488 #define CONFIG_NETDEV           eth1
 489
 490 #define CONFIG_HOSTNAME         simpc8313
 491 #define CONFIG_ROOTPATH         /tftpboot/
 492 #define CONFIG_BOOTFILE         /tftpboot/uImage
 493 #define CONFIG_UBOOTPATH        u-boot-nand.bin /* U-Boot image on TFTP server */
 494 #define CONFIG_FDTFILE          simpc8313.dtb
 495
 496 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 497 #define CONFIG_BOOTDELAY        5       /* 5 second delay */
 498 #define CONFIG_BAUDRATE         115200
 499
 500 #define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
 501
 502 #define XMK_STR(x)      #x
 503 #define MK_STR(x)       XMK_STR(x)
 504
 505 #define CONFIG_EXTRA_ENV_SETTINGS \
 506         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 507         "ethprime=TSEC1\0"                                              \
 508         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 509         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 510                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 511                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 512                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 513                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 514                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 515         "fdtaddr=ae0000\0"                                              \
 516         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 517         "console=ttyS0\0"                                               \
 518         "setbootargs=setenv bootargs "                                  \
 519                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 520         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 521                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 522                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"    \
 523         "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 524         "burn_uboot=nand erase u-boot 80000; "                          \
 525                 "nand write 100000 u-boot $filesize\0"                  \
 526         "update_uboot=run load_uboot;run burn_uboot\0"                  \
 527         "mtdids=nand0=nand0\0"                                          \
 528         "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 529         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 530                 "nfsroot=${serverip}:${rootpath}\0"                     \
 531         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 532         "addip=setenv bootargs ${bootargs} "                            \
 533                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 534                 ":${hostname}:${netdev}:off panic=1\0"                  \
 535         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"        \
 536         "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 537                 "console=ttyS0,115200\0"                                \
 538         ""
 539
 540 #define CONFIG_NFSBOOTCOMMAND                                           \
 541         "setenv rootdev /dev/nfs;"                                      \
 542         "run setbootargs;"                                              \
 543         "run setipargs;"                                                \
 544         "tftp $loadaddr $bootfile;"                                     \
 545         "tftp $fdtaddr $fdtfile;"                                       \
 546         "bootm $loadaddr - $fdtaddr"
 547
 548 #define CONFIG_RAMBOOTCOMMAND                                           \
 549         "setenv rootdev /dev/ram;"                                      \
 550         "run setbootargs;"                                              \
 551         "tftp $ramdiskaddr $ramdiskfile;"                               \
 552         "tftp $loadaddr $bootfile;"                                     \
 553         "tftp $fdtaddr $fdtfile;"                                       \
 554         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 555
 556 #undef MK_STR
 557 #undef XMK_STR
 558
 559 #endif  /* __CONFIG_H */