include/configs/P3G4.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #ifndef __ASSEMBLY__
  16 #include <galileo/core.h>
  17 #endif
  18
  19 #include "../board/evb64260/local.h"
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25
  26 #define CONFIG_P3G4             1       /* this is a P3G4  board        */
  27 #define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
  28
  29 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  30
  31 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115200    */
  32
  33 #undef  CONFIG_ECC                      /* enable ECC support */
  34 /* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
  35
  36 /* which initialization functions to call for this board */
  37 #define CONFIG_MISC_INIT_R      1
  38 #define CONFIG_BOARD_EARLY_INIT_F 1
  39
  40 #define CONFIG_SYS_BOARD_NAME           "P3G4"
  41
  42 #undef CONFIG_SYS_HUSH_PARSER
  43
  44 /*
  45  * The following defines let you select what serial you want to use
  46  * for your console driver.
  47  *
  48  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  49  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  50  */
  51 #define CONFIG_MPSC
  52 #define CONFIG_MPSC_PORT        0
  53
  54
  55 /* define this if you want to enable GT MAC filtering */
  56 #define CONFIG_GT_USE_MAC_HASH_TABLE
  57
  58 #undef CONFIG_ETHER_PORT_MII    /* use RMII */
  59
  60 #if 0
  61 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  62 #else
  63 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  64 #endif
  65 #define CONFIG_ZERO_BOOTDELAY_CHECK
  66
  67 #define CONFIG_PREBOOT  "echo;" \
  68         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  69         "echo"
  70
  71 #undef  CONFIG_BOOTARGS
  72
  73 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  74         "netdev=eth0\0"                                                 \
  75         "hostname=p3g4\0"                                               \
  76         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  77                 "nfsroot=${serverip}:${rootpath}\0"                     \
  78         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  79         "addip=setenv bootargs ${bootargs} "                            \
  80                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  81                 ":${hostname}:${netdev}:off panic=1\0"                  \
  82         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  83         "flash_nfs=run nfsargs addip addtty;"                           \
  84                 "bootm ${kernel_addr}\0"                                \
  85         "flash_self=run ramargs addip addtty;"                          \
  86                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  87         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
  88                 "bootm\0"                                               \
  89         "rootpath=/opt/eldk/ppc_74xx\0"                                 \
  90         "bootfile=/tftpboot/p3g4/uImage\0"                              \
  91         "kernel_addr=ff000000\0"                                        \
  92         "ramdisk_addr=ff010000\0"                                       \
  93         "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"                  \
  94         "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"   \
  95                 "cp.b 100000 fff00000 ${filesize};"                     \
  96                 "setenv filesize;saveenv\0"                             \
  97         "upd=run load update\0"                                         \
  98         ""
  99 #define CONFIG_BOOTCOMMAND      "run flash_self"
 100
 101 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 102 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate changes       */
 103
 104 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 105 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 106
 107 /*
 108  * BOOTP options
 109  */
 110 #define CONFIG_BOOTP_SUBNETMASK
 111 #define CONFIG_BOOTP_GATEWAY
 112 #define CONFIG_BOOTP_HOSTNAME
 113 #define CONFIG_BOOTP_BOOTPATH
 114 #define CONFIG_BOOTP_BOOTFILESIZE
 115
 116
 117 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125 #define CONFIG_CMD_ASKENV
 126 #define CONFIG_CMD_DHCP
 127 #define CONFIG_CMD_PCI
 128 #define CONFIG_CMD_ELF
 129 #define CONFIG_CMD_MII
 130 #define CONFIG_CMD_PING
 131 #define CONFIG_CMD_UNIVERSE
 132 #define CONFIG_CMD_BSP
 133
 134
 135 /*
 136  * Miscellaneous configurable options
 137  */
 138 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 139 #if defined(CONFIG_CMD_KGDB)
 140 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 141 #else
 142 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 143 #endif
 144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 145 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 146 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 147
 148 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 149 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
 150
 151 #define CONFIG_SYS_LOAD_ADDR            0x00300000      /* default load address */
 152
 153 #define CONFIG_SYS_HZ                   1000            /* decr freq: 1ms ticks */
 154 #define CONFIG_SYS_BUS_CLK              133000000       /* 133 MHz              */
 155
 156 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 157
 158
 159 /*
 160  * Low Level Configuration Settings
 161  * (address mappings, register initial values, etc.)
 162  * You should know what you are doing if you make changes here.
 163  */
 164
 165 /*-----------------------------------------------------------------------
 166  * Definitions for initial stack pointer and data area
 167  */
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 169 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_RAM_LOCK
 172
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_FLASH_BASE           0xff000000
 181 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 182 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 183 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 184 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc */
 185
 186 /* areas to map different things with the GT in physical space */
 187 #define CONFIG_SYS_DRAM_BANKS           1
 188 #define CONFIG_SYS_DFL_GT_REGS          0x14000000      /* boot time GT_REGS */
 189
 190 /* What to put in the bats. */
 191 #define CONFIG_SYS_MISC_REGION_BASE     0xf0000000
 192
 193 /* Peripheral Device section */
 194 #define CONFIG_SYS_GT_REGS              0xf8000000
 195 #define CONFIG_SYS_DEV_BASE             0xff000000
 196
 197 #define CONFIG_SYS_DEV0_SPACE           CONFIG_SYS_DEV_BASE
 198 #define CONFIG_SYS_DEV1_SPACE           (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
 199 #define CONFIG_SYS_DEV2_SPACE           (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
 200 #define CONFIG_SYS_DEV3_SPACE           (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 201
 202 #define CONFIG_SYS_DEV0_SIZE             _8M /* Flash bank */
 203 #define CONFIG_SYS_DEV1_SIZE             0   /* unused */
 204 #define CONFIG_SYS_DEV2_SIZE             0   /* unused */
 205 #define CONFIG_SYS_DEV3_SIZE             0   /* unused */
 206
 207 #define CONFIG_SYS_16BIT_BOOT_PAR       0xc01b5e7c
 208 #define CONFIG_SYS_DEV0_PAR             CONFIG_SYS_16BIT_BOOT_PAR
 209
 210 #if 0 /* Wrong?? NTL */
 211 #define CONFIG_SYS_MPP_CONTROL_0        0x53541717      /* InitAct EOT[4] DBurst TCEn[1] */
 212                                                 /* DMAAck[1:0] GNT0[1:0] */
 213 #else
 214 #define CONFIG_SYS_MPP_CONTROL_0        0x53547777      /* InitAct EOT[4] DBurst TCEn[1] */
 215                                                 /* REQ0[1:0] GNT0[1:0] */
 216 #endif
 217 #define CONFIG_SYS_MPP_CONTROL_1        0x44009911      /* TCEn[4] TCTcnt[4] GPP[13:12] */
 218                                                 /* DMAReq[4] DMAAck[4] WDNMI WDE */
 219 #if 0 /* Wrong?? NTL */
 220 #define CONFIG_SYS_MPP_CONTROL_2        0x40091818      /* TCTcnt[0] GPP[22:21] BClkIn */
 221                                                 /* DMAAck[1:0] GNT1[1:0] */
 222 #else
 223 #define CONFIG_SYS_MPP_CONTROL_2        0x40098888      /* TCTcnt[0] */
 224                                                 /* GPP[22] (RS232IntB or PCI1Int) */
 225                                                 /* GPP[21] (RS323IntA) */
 226                                                 /* BClkIn */
 227                                                 /* REQ1[1:0] GNT1[1:0] */
 228 #endif
 229
 230 #if 0 /* Wrong?? NTL */
 231 # define CONFIG_SYS_MPP_CONTROL_3       0x00090066      /* GPP[31:29] BClkOut0 */
 232                                                 /* GPP[27:26] Int[1:0] */
 233 #else
 234 # define CONFIG_SYS_MPP_CONTROL_3       0x22090066      /* MREQ MGNT */
 235                                                 /* GPP[29]    (PCI1Int) */
 236                                                 /* BClkOut0 */
 237                                                 /* GPP[27]    (PCI0Int) */
 238                                                 /* GPP[26]    (RtcInt or PCI1Int) */
 239                                                 /* CPUInt[25:24] */
 240 #endif
 241
 242 #define CONFIG_SYS_SERIAL_PORT_MUX      0x00001102      /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
 243
 244 #if 0 /* Wrong?? - NTL */
 245 # define CONFIG_SYS_GPP_LEVEL_CONTROL   0x000002c6
 246 #else
 247 # define CONFIG_SYS_GPP_LEVEL_CONTROL   0x2c600000      /* 0010 1100 0110 0000 */
 248                                                 /* gpp[29] */
 249                                                 /* gpp[27:26] */
 250                                                 /* gpp[22:21] */
 251
 252 # define CONFIG_SYS_SDRAM_CONFIG        0xd8e18200      /* 0x448 */
 253                                 /* idmas use buffer 1,1
 254                                    comm use buffer 0
 255                                    pci use buffer 1,1
 256                                    cpu use buffer 0
 257                                    normal load (see also ifdef HVL)
 258                                    standard SDRAM (see also ifdef REG)
 259                                    non staggered refresh */
 260                                 /* 31:26  25 23  20 19 18 16 */
 261                                 /* 110110 00 111 0  0  00 1 */
 262                                 /* refresh_count=0x200
 263                                    phisical interleaving disable
 264                                    virtual interleaving enable */
 265                                 /* 15 14 13:0 */
 266                                 /* 1  0  0x200 */
 267 #endif
 268
 269 #if 0
 270 #define CONFIG_SYS_DUART_IO             CONFIG_SYS_DEV2_SPACE
 271 #define CONFIG_SYS_DUART_CHAN           1               /* channel to use for console */
 272 #endif
 273 #undef CONFIG_SYS_INIT_CHAN1
 274 #undef CONFIG_SYS_INIT_CHAN2
 275 #if 0
 276 #define SRAM_BASE               CONFIG_SYS_DEV0_SPACE
 277 #define SRAM_SIZE               0x00100000              /* 1 MB of sram */
 278 #endif
 279
 280
 281 /*-----------------------------------------------------------------------
 282  * PCI stuff
 283  *-----------------------------------------------------------------------
 284  */
 285
 286 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 287 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 288 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 289
 290 #define CONFIG_PCI                      /* include pci support          */
 291 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 292 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 293
 294 /* PCI MEMORY MAP section */
 295 #define CONFIG_SYS_PCI0_MEM_BASE        0x80000000
 296 #define CONFIG_SYS_PCI0_MEM_SIZE        _128M
 297 #define CONFIG_SYS_PCI0_0_MEM_SPACE     (CONFIG_SYS_PCI0_MEM_BASE)
 298
 299 #define CONFIG_SYS_PCI1_MEM_BASE        0x88000000
 300 #define CONFIG_SYS_PCI1_MEM_SIZE        _128M
 301 #define CONFIG_SYS_PCI1_0_MEM_SPACE     (CONFIG_SYS_PCI1_MEM_BASE)
 302
 303 /* PCI I/O MAP section */
 304 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
 305 #define CONFIG_SYS_PCI0_IO_SIZE _16M
 306 #define CONFIG_SYS_PCI0_IO_SPACE        (CONFIG_SYS_PCI0_IO_BASE)
 307 #define CONFIG_SYS_PCI0_IO_SPACE_PCI    0x00000000
 308
 309 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
 310 #define CONFIG_SYS_PCI1_IO_SIZE _16M
 311 #define CONFIG_SYS_PCI1_IO_SPACE        (CONFIG_SYS_PCI1_IO_BASE)
 312 #define CONFIG_SYS_PCI1_IO_SPACE_PCI    0x00000000
 313
 314 /*----------------------------------------------------------------------
 315  * Initial BAT mappings
 316  */
 317
 318 /* NOTES:
 319  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 320  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 321  */
 322
 323 /* SDRAM */
 324 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 325 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 326 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 327 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 328
 329 /* init ram */
 330 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 331 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 332 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 333 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 334
 335 /* PCI0, PCI1 in one BAT */
 336 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
 337 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
 338 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 339 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 340
 341 /* GT regs, bootrom, all the devices, PCI I/O */
 342 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 343 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 344 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 345 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 346
 347 /* I2C speed and slave address (for compatability) defaults */
 348 #define CONFIG_SYS_I2C_SPEED    400000
 349 #define CONFIG_SYS_I2C_SLAVE    0x7F
 350
 351 /* I2C addresses for the two DIMM SPD chips */
 352 #ifndef CONFIG_EVB64260_750CX
 353 #define DIMM0_I2C_ADDR  0x56
 354 #define DIMM1_I2C_ADDR  0x54
 355 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
 356 #define DIMM0_I2C_ADDR  0x54
 357 #define DIMM1_I2C_ADDR  0x54
 358 #endif
 359
 360 /*
 361  * For booting Linux, the board info and command line data
 362  * have to be in the first 8 MB of memory, since this is
 363  * the maximum mapped by the Linux kernel during initialization.
 364  */
 365 #define CONFIG_SYS_BOOTMAPSZ            (8<<20) /* Initial Memory map for Linux */
 366
 367 /*-----------------------------------------------------------------------
 368  * FLASH organization
 369  */
 370 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks   */
 371 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip */
 372
 373 #define CONFIG_SYS_EXTRA_FLASH_DEVICE   BOOT_DEVICE
 374 #define CONFIG_SYS_EXTRA_FLASH_WIDTH    2       /* 16 bit */
 375 #define CONFIG_SYS_BOOT_FLASH_WIDTH     2       /* 16 bit */
 376
 377 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 378 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 379 #define CONFIG_SYS_FLASH_CFI            1
 380
 381 #define CONFIG_ENV_IS_IN_FLASH  1
 382 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector */
 383 #define CONFIG_ENV_SECT_SIZE    0x20000
 384 #define CONFIG_ENV_ADDR         0xFFFE0000
 385
 386 /*-----------------------------------------------------------------------
 387  * Cache Configuration
 388  */
 389 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For all MPC74xx CPUs          */
 390 #if defined(CONFIG_CMD_KGDB)
 391 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 392 #endif
 393
 394 /*-----------------------------------------------------------------------
 395  * L2CR setup -- make sure this is right for your board!
 396  * look in include/74xx_7xx.h for the defines used here
 397  */
 398
 399 #define CONFIG_SYS_L2
 400
 401 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 402                          L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 403
 404 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 405
 406 #define CONFIG_SYS_BOARD_ASM_INIT      1
 407
 408
 409 #endif  /* __CONFIG_H */