include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28
  29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  31 #endif
  32
  33 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
  34
  35 #define CONFIG_SYS_SRIO
  36 #define CONFIG_SRIO1                    /* SRIO port 1 */
  37 #define CONFIG_SRIO2                    /* SRIO port 2 */
  38 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  39
  40 #ifndef __ASSEMBLY__
  41 #include <linux/stringify.h>
  42 #endif
  43
  44 /*
  45  * These can be toggled for performance analysis, otherwise use default.
  46  */
  47 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  48
  49 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  50
  51 /*
  52  *  Config the L3 Cache as L3 SRAM
  53  */
  54 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  55 #ifdef CONFIG_PHYS_64BIT
  56 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  57                 CONFIG_RAMBOOT_TEXT_BASE)
  58 #else
  59 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  60 #endif
  61
  62 #ifdef CONFIG_PHYS_64BIT
  63 #define CONFIG_SYS_DCSRBAR              0xf0000000
  64 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  65 #endif
  66
  67 /*
  68  * DDR Setup
  69  */
  70 #define CONFIG_VERY_BIG_RAM
  71 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  72 #define CFG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_SDRAM_BASE
  73
  74 #define SPD_EEPROM_ADDRESS      0x52
  75 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
  76
  77 /*
  78  * Local Bus Definitions
  79  */
  80
  81 /* Set the local bus clock 1/8 of platform clock */
  82 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  83
  84 /*
  85  * This board doesn't have a promjet connector.
  86  * However, it uses commone corenet board LAW and TLB.
  87  * It is necessary to use the same start address with proper offset.
  88  */
  89 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
  92 #else
  93 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  94 #endif
  95
  96 #define CONFIG_FSL_CPLD
  97 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
  98 #ifdef CONFIG_PHYS_64BIT
  99 #define CPLD_BASE_PHYS          0xfffdf0000ull
 100 #else
 101 #define CPLD_BASE_PHYS          CPLD_BASE
 102 #endif
 103
 104 #define PIXIS_LBMAP_SWITCH      7
 105 #define PIXIS_LBMAP_MASK        0xf0
 106 #define PIXIS_LBMAP_SHIFT       4
 107 #define PIXIS_LBMAP_ALTBANK     0x40
 108
 109 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 110
 111 /* Nand Flash */
 112 #ifdef CONFIG_NAND_FSL_ELBC
 113 #define CFG_SYS_NAND_BASE               0xffa00000
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CFG_SYS_NAND_BASE_PHYS  0xfffa00000ull
 116 #else
 117 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 118 #endif
 119
 120 #define CFG_SYS_NAND_BASE_LIST     {CFG_SYS_NAND_BASE}
 121
 122 /* NAND flash config */
 123 #define CFG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 124                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 125                                | BR_PS_8               /* Port Size = 8 bit */ \
 126                                | BR_MS_FCM             /* MSEL = FCM */ \
 127                                | BR_V)                 /* valid */
 128 #define CFG_SYS_NAND_OR_PRELIM  (0xFFFC0000           /* length 256K */ \
 129                                | OR_FCM_PGS            /* Large Page*/ \
 130                                | OR_FCM_CSCT \
 131                                | OR_FCM_CST \
 132                                | OR_FCM_CHT \
 133                                | OR_FCM_SCY_1 \
 134                                | OR_FCM_TRLX \
 135                                | OR_FCM_EHTR)
 136 #endif /* CONFIG_NAND_FSL_ELBC */
 137
 138 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 139
 140 #define CONFIG_HWCONFIG
 141
 142 /* define to use L1 as initial stack */
 143 #define CONFIG_L1_INIT_RAM
 144 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 145 #ifdef CONFIG_PHYS_64BIT
 146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 147 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 148 /* The assembler doesn't like typecast */
 149 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 150         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 151           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 152 #else
 153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 156 #endif
 157 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 158
 159 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 160
 161 /* Serial Port - controlled on board with jumper J8
 162  * open - index 2
 163  * shorted - index 1
 164  */
 165 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 166
 167 #define CONFIG_SYS_BAUDRATE_TABLE       \
 168         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 169
 170 #define CFG_SYS_NS16550_COM1    (CONFIG_SYS_CCSRBAR+0x11C500)
 171 #define CFG_SYS_NS16550_COM2    (CONFIG_SYS_CCSRBAR+0x11C600)
 172 #define CFG_SYS_NS16550_COM3    (CONFIG_SYS_CCSRBAR+0x11D500)
 173 #define CFG_SYS_NS16550_COM4    (CONFIG_SYS_CCSRBAR+0x11D600)
 174
 175 /* I2C */
 176
 177
 178 /*
 179  * RapidIO
 180  */
 181 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 184 #else
 185 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 186 #endif
 187 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 188
 189 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 190 #ifdef CONFIG_PHYS_64BIT
 191 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 192 #else
 193 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 194 #endif
 195 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 196
 197 /*
 198  * for slave u-boot IMAGE instored in master memory space,
 199  * PHYS must be aligned based on the SIZE
 200  */
 201 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 202 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 203 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 204 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 205 /*
 206  * for slave UCODE and ENV instored in master memory space,
 207  * PHYS must be aligned based on the SIZE
 208  */
 209 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 210 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 211 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 212
 213 /* slave core release by master*/
 214 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 215 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 216
 217 /*
 218  * SRIO_PCIE_BOOT - SLAVE
 219  */
 220 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 221 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 222 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 223                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 224 #endif
 225
 226 /*
 227  * eSPI - Enhanced SPI
 228  */
 229
 230 /*
 231  * General PCI
 232  * Memory space is mapped 1-1, but I/O space must start from 0.
 233  */
 234
 235 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 236 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 237 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 238 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 239 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 240
 241 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 242 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 243 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 244 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 245 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 246
 247 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 248 #define CFG_SYS_PCIE3_MEM_VIRT  0xc0000000
 249 #define CFG_SYS_PCIE3_MEM_PHYS  0xc40000000ull
 250
 251 /* Qman/Bman */
 252 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 253 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 254 #ifdef CONFIG_PHYS_64BIT
 255 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 256 #else
 257 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 258 #endif
 259 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 260 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 261 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 262 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 263 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 264 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 265                                         CONFIG_SYS_BMAN_CENA_SIZE)
 266 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 267 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 268 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 269 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 270 #ifdef CONFIG_PHYS_64BIT
 271 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 272 #else
 273 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 274 #endif
 275 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 276 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 277 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 278 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 279                                         CONFIG_SYS_QMAN_CENA_SIZE)
 280 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 281 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 282
 283 #ifdef CONFIG_FMAN_ENET
 284 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 285 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 286 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 287 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 288 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 289
 290 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 291 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 292 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 293 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 294
 295 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 296
 297 #define CONFIG_SYS_TBIPA_VALUE  8
 298 #endif
 299
 300 #ifdef CONFIG_MMC
 301 #define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 302 #endif
 303
 304 /*
 305  * Miscellaneous configurable options
 306  */
 307
 308 /*
 309  * For booting Linux, the board info and command line data
 310  * have to be in the first 64 MB of memory, since this is
 311  * the maximum mapped by the Linux kernel during initialization.
 312  */
 313 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 314
 315 /*
 316  * Environment Configuration
 317  */
 318 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 319 #define CONFIG_UBOOTPATH        u-boot.bin
 320
 321 #define __USB_PHY_TYPE  utmi
 322
 323 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 324         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 325         "bank_intlv=cs0_cs1\0"                                  \
 326         "netdev=eth0\0"                                         \
 327         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 328         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"         \
 329         "tftpflash=tftpboot $loadaddr $uboot && "               \
 330         "protect off $ubootaddr +$filesize && "                 \
 331         "erase $ubootaddr +$filesize && "                       \
 332         "cp.b $loadaddr $ubootaddr $filesize && "               \
 333         "protect on $ubootaddr +$filesize && "                  \
 334         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 335         "consoledev=ttyS0\0"                                    \
 336         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 337         "usb_dr_mode=host\0"                                    \
 338         "ramdiskaddr=2000000\0"                                 \
 339         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 340         "fdtaddr=1e00000\0"                                     \
 341         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 342         "bdev=sda3\0"
 343
 344 #include <asm/fsl_secure_boot.h>
 345
 346 #endif  /* __CONFIG_H */