include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  39 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  40
  41 #define CONFIG_SYS_SRIO
  42 #define CONFIG_SRIO1                    /* SRIO port 1 */
  43 #define CONFIG_SRIO2                    /* SRIO port 2 */
  44 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  45 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  46
  47 #if defined(CONFIG_SPIFLASH)
  48 #elif defined(CONFIG_SDCARD)
  49         #define CONFIG_FSL_FIXED_MMC_LOCATION
  50 #endif
  51
  52 #ifndef __ASSEMBLY__
  53 unsigned long get_board_sys_clk(unsigned long dummy);
  54 #include <linux/stringify.h>
  55 #endif
  56 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  57
  58 /*
  59  * These can be toggled for performance analysis, otherwise use default.
  60  */
  61 #define CONFIG_SYS_CACHE_STASHING
  62 #define CONFIG_BACKSIDE_L2_CACHE
  63 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  64 #define CONFIG_BTB                      /* toggle branch predition */
  65
  66 #define CONFIG_ENABLE_36BIT_PHYS
  67
  68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  69
  70 /*
  71  *  Config the L3 Cache as L3 SRAM
  72  */
  73 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  74 #ifdef CONFIG_PHYS_64BIT
  75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  76                 CONFIG_RAMBOOT_TEXT_BASE)
  77 #else
  78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  79 #endif
  80 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  82
  83 #ifdef CONFIG_PHYS_64BIT
  84 #define CONFIG_SYS_DCSRBAR              0xf0000000
  85 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  86 #endif
  87
  88 /* EEPROM */
  89 #define CONFIG_SYS_I2C_EEPROM_NXID
  90 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 100 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 101
 102 #define CONFIG_SYS_SPD_BUS_NUM  0
 103 #define SPD_EEPROM_ADDRESS      0x52
 104 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 105
 106 /*
 107  * Local Bus Definitions
 108  */
 109
 110 /* Set the local bus clock 1/8 of platform clock */
 111 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 112
 113 /*
 114  * This board doesn't have a promjet connector.
 115  * However, it uses commone corenet board LAW and TLB.
 116  * It is necessary to use the same start address with proper offset.
 117  */
 118 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 121 #else
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 123 #endif
 124
 125 #define CONFIG_SYS_FLASH_BR_PRELIM \
 126                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 127                 BR_PS_16 | BR_V)
 128 #define CONFIG_SYS_FLASH_OR_PRELIM \
 129                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 130                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 131
 132 #define CONFIG_FSL_CPLD
 133 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 134 #ifdef CONFIG_PHYS_64BIT
 135 #define CPLD_BASE_PHYS          0xfffdf0000ull
 136 #else
 137 #define CPLD_BASE_PHYS          CPLD_BASE
 138 #endif
 139
 140 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 141 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 142
 143 #define PIXIS_LBMAP_SWITCH      7
 144 #define PIXIS_LBMAP_MASK        0xf0
 145 #define PIXIS_LBMAP_SHIFT       4
 146 #define PIXIS_LBMAP_ALTBANK     0x40
 147
 148 #define CONFIG_SYS_FLASH_QUIET_TEST
 149 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 150
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 152 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 155
 156 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 157
 158 #if defined(CONFIG_RAMBOOT_PBL)
 159 #define CONFIG_SYS_RAMBOOT
 160 #endif
 161
 162 #define CONFIG_NAND_FSL_ELBC
 163 /* Nand Flash */
 164 #ifdef CONFIG_NAND_FSL_ELBC
 165 #define CONFIG_SYS_NAND_BASE            0xffa00000
 166 #ifdef CONFIG_PHYS_64BIT
 167 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 168 #else
 169 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 170 #endif
 171
 172 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 173 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 174 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 175
 176 /* NAND flash config */
 177 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 178                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 179                                | BR_PS_8               /* Port Size = 8 bit */ \
 180                                | BR_MS_FCM             /* MSEL = FCM */ \
 181                                | BR_V)                 /* valid */
 182 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 183                                | OR_FCM_PGS            /* Large Page*/ \
 184                                | OR_FCM_CSCT \
 185                                | OR_FCM_CST \
 186                                | OR_FCM_CHT \
 187                                | OR_FCM_SCY_1 \
 188                                | OR_FCM_TRLX \
 189                                | OR_FCM_EHTR)
 190
 191 #ifdef CONFIG_MTD_RAW_NAND
 192 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 193 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 194 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 195 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 196 #else
 197 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 198 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 199 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 200 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 201 #endif
 202 #else
 203 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 204 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 205 #endif /* CONFIG_NAND_FSL_ELBC */
 206
 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
 208 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 209 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 210
 211 #define CONFIG_HWCONFIG
 212
 213 /* define to use L1 as initial stack */
 214 #define CONFIG_L1_INIT_RAM
 215 #define CONFIG_SYS_INIT_RAM_LOCK
 216 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 217 #ifdef CONFIG_PHYS_64BIT
 218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 220 /* The assembler doesn't like typecast */
 221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 222         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 223           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 224 #else
 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 228 #endif
 229 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 230
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 232                                         GENERATED_GBL_DATA_SIZE)
 233 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 234
 235 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 236
 237 /* Serial Port - controlled on board with jumper J8
 238  * open - index 2
 239  * shorted - index 1
 240  */
 241 #define CONFIG_SYS_NS16550_SERIAL
 242 #define CONFIG_SYS_NS16550_REG_SIZE     1
 243 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 244
 245 #define CONFIG_SYS_BAUDRATE_TABLE       \
 246         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 247
 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 250 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 251 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 252
 253 /* I2C */
 254
 255
 256 /*
 257  * RapidIO
 258  */
 259 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 260 #ifdef CONFIG_PHYS_64BIT
 261 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 262 #else
 263 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 264 #endif
 265 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 266
 267 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 268 #ifdef CONFIG_PHYS_64BIT
 269 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 270 #else
 271 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 272 #endif
 273 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 274
 275 /*
 276  * for slave u-boot IMAGE instored in master memory space,
 277  * PHYS must be aligned based on the SIZE
 278  */
 279 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 280 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 281 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 282 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 283 /*
 284  * for slave UCODE and ENV instored in master memory space,
 285  * PHYS must be aligned based on the SIZE
 286  */
 287 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 288 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 289 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 290
 291 /* slave core release by master*/
 292 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 293 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 294
 295 /*
 296  * SRIO_PCIE_BOOT - SLAVE
 297  */
 298 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 299 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 300 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 301                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 302 #endif
 303
 304 /*
 305  * eSPI - Enhanced SPI
 306  */
 307
 308 /*
 309  * General PCI
 310  * Memory space is mapped 1-1, but I/O space must start from 0.
 311  */
 312
 313 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 314 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 315 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 316 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 317 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 318
 319 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 320 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 321 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 322 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 323 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 324
 325 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 326 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 327 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 328 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 329 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 330
 331 /* Qman/Bman */
 332 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 333 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 334 #ifdef CONFIG_PHYS_64BIT
 335 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 336 #else
 337 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 338 #endif
 339 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 340 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 341 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 342 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 343 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 344 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 345                                         CONFIG_SYS_BMAN_CENA_SIZE)
 346 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 347 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 348 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 349 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 350 #ifdef CONFIG_PHYS_64BIT
 351 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 352 #else
 353 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 354 #endif
 355 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 356 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 357 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 358 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 359 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 360 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 361                                         CONFIG_SYS_QMAN_CENA_SIZE)
 362 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 363 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 364
 365 #define CONFIG_SYS_DPAA_FMAN
 366 #define CONFIG_SYS_DPAA_PME
 367 /* Default address of microcode for the Linux Fman driver */
 368 #if defined(CONFIG_SPIFLASH)
 369 /*
 370  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 371  * env, so we got 0x110000.
 372  */
 373 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 374 #elif defined(CONFIG_SDCARD)
 375 /*
 376  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 377  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 378  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 379  */
 380 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 381 #elif defined(CONFIG_MTD_RAW_NAND)
 382 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 383 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 384 /*
 385  * Slave has no ucode locally, it can fetch this from remote. When implementing
 386  * in two corenet boards, slave's ucode could be stored in master's memory
 387  * space, the address can be mapped from slave TLB->slave LAW->
 388  * slave SRIO or PCIE outbound window->master inbound window->
 389  * master LAW->the ucode address in master's memory space.
 390  */
 391 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 392 #else
 393 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 394 #endif
 395 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 396 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 397
 398 #ifdef CONFIG_PCI
 399 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 400 #endif  /* CONFIG_PCI */
 401
 402 /* SATA */
 403 #define CONFIG_FSL_SATA_V2
 404
 405 #ifdef CONFIG_FSL_SATA_V2
 406 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 407 #define CONFIG_SATA1
 408 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 409 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 410 #define CONFIG_SATA2
 411 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 412 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 413
 414 #define CONFIG_LBA48
 415 #endif
 416
 417 #ifdef CONFIG_FMAN_ENET
 418 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 419 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 420 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 421 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 422 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 423
 424 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 425 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 426 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 427 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 428
 429 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 430
 431 #define CONFIG_SYS_TBIPA_VALUE  8
 432 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 433 #endif
 434
 435 /*
 436  * Environment
 437  */
 438 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 439 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 440
 441 /*
 442 * USB
 443 */
 444 #define CONFIG_HAS_FSL_DR_USB
 445 #define CONFIG_HAS_FSL_MPH_USB
 446
 447 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 448 #define CONFIG_USB_EHCI_FSL
 449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 450 #endif
 451
 452 #ifdef CONFIG_MMC
 453 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 454 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 455 #endif
 456
 457 /*
 458  * Miscellaneous configurable options
 459  */
 460
 461 /*
 462  * For booting Linux, the board info and command line data
 463  * have to be in the first 64 MB of memory, since this is
 464  * the maximum mapped by the Linux kernel during initialization.
 465  */
 466 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 467 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 468
 469 #ifdef CONFIG_CMD_KGDB
 470 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 471 #endif
 472
 473 /*
 474  * Environment Configuration
 475  */
 476 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 477 #define CONFIG_BOOTFILE         "uImage"
 478 #define CONFIG_UBOOTPATH        u-boot.bin
 479
 480 #define __USB_PHY_TYPE  utmi
 481
 482 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 483         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 484         "bank_intlv=cs0_cs1\0"                                  \
 485         "netdev=eth0\0"                                         \
 486         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 487         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 488         "tftpflash=tftpboot $loadaddr $uboot && "               \
 489         "protect off $ubootaddr +$filesize && "                 \
 490         "erase $ubootaddr +$filesize && "                       \
 491         "cp.b $loadaddr $ubootaddr $filesize && "               \
 492         "protect on $ubootaddr +$filesize && "                  \
 493         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 494         "consoledev=ttyS0\0"                                    \
 495         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 496         "usb_dr_mode=host\0"                                    \
 497         "ramdiskaddr=2000000\0"                                 \
 498         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 499         "fdtaddr=1e00000\0"                                     \
 500         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 501         "bdev=sda3\0"
 502
 503 #define HDBOOT                                  \
 504         "setenv bootargs root=/dev/$bdev rw "           \
 505         "console=$consoledev,$baudrate $othbootargs;"   \
 506         "tftp $loadaddr $bootfile;"                     \
 507         "tftp $fdtaddr $fdtfile;"                       \
 508         "bootm $loadaddr - $fdtaddr"
 509
 510 #define NFSBOOTCOMMAND                  \
 511         "setenv bootargs root=/dev/nfs rw "     \
 512         "nfsroot=$serverip:$rootpath "          \
 513         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 514         "console=$consoledev,$baudrate $othbootargs;"   \
 515         "tftp $loadaddr $bootfile;"             \
 516         "tftp $fdtaddr $fdtfile;"               \
 517         "bootm $loadaddr - $fdtaddr"
 518
 519 #define RAMBOOTCOMMAND                          \
 520         "setenv bootargs root=/dev/ram rw "             \
 521         "console=$consoledev,$baudrate $othbootargs;"   \
 522         "tftp $ramdiskaddr $ramdiskfile;"               \
 523         "tftp $loadaddr $bootfile;"                     \
 524         "tftp $fdtaddr $fdtfile;"                       \
 525         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 526
 527 #define CONFIG_BOOTCOMMAND              HDBOOT
 528
 529 #include <asm/fsl_secure_boot.h>
 530
 531 #endif  /* __CONFIG_H */