1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
33 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
35 #define CONFIG_SYS_SRIO
36 #define CONFIG_SRIO1 /* SRIO port 1 */
37 #define CONFIG_SRIO2 /* SRIO port 2 */
38 #define CONFIG_SRIO_PCIE_BOOT_MASTER
39 #define CONFIG_SYS_DPAA_RMAN /* RMan */
42 #include <linux/stringify.h>
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
50 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
53 * Config the L3 Cache as L3 SRAM
55 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
56 #ifdef CONFIG_PHYS_64BIT
57 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
58 CONFIG_RAMBOOT_TEXT_BASE)
60 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
62 #define CONFIG_SYS_L3_SIZE (1024 << 10)
63 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
65 #ifdef CONFIG_PHYS_64BIT
66 #define CONFIG_SYS_DCSRBAR 0xf0000000
67 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
71 #define CONFIG_SYS_I2C_EEPROM_NXID
72 #define CONFIG_SYS_EEPROM_BUS_NUM 0
77 #define CONFIG_VERY_BIG_RAM
78 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
81 #define SPD_EEPROM_ADDRESS 0x52
82 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
85 * Local Bus Definitions
88 /* Set the local bus clock 1/8 of platform clock */
89 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
92 * This board doesn't have a promjet connector.
93 * However, it uses commone corenet board LAW and TLB.
94 * It is necessary to use the same start address with proper offset.
96 #define CONFIG_SYS_FLASH_BASE 0xe0000000
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
100 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
103 #define CONFIG_SYS_FLASH_BR_PRELIM \
104 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
106 #define CONFIG_SYS_FLASH_OR_PRELIM \
107 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
108 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
110 #define CONFIG_FSL_CPLD
111 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
112 #ifdef CONFIG_PHYS_64BIT
113 #define CPLD_BASE_PHYS 0xfffdf0000ull
115 #define CPLD_BASE_PHYS CPLD_BASE
118 #define PIXIS_LBMAP_SWITCH 7
119 #define PIXIS_LBMAP_MASK 0xf0
120 #define PIXIS_LBMAP_SHIFT 4
121 #define PIXIS_LBMAP_ALTBANK 0x40
123 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
126 #ifdef CONFIG_NAND_FSL_ELBC
127 #define CONFIG_SYS_NAND_BASE 0xffa00000
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
131 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
134 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
135 #define CONFIG_SYS_MAX_NAND_DEVICE 1
137 /* NAND flash config */
138 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
139 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
140 | BR_PS_8 /* Port Size = 8 bit */ \
141 | BR_MS_FCM /* MSEL = FCM */ \
143 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
144 | OR_FCM_PGS /* Large Page*/ \
151 #endif /* CONFIG_NAND_FSL_ELBC */
153 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
155 #define CONFIG_HWCONFIG
157 /* define to use L1 as initial stack */
158 #define CONFIG_L1_INIT_RAM
159 #define CONFIG_SYS_INIT_RAM_LOCK
160 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
161 #ifdef CONFIG_PHYS_64BIT
162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
164 /* The assembler doesn't like typecast */
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
166 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
167 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
175 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
179 /* Serial Port - controlled on board with jumper J8
183 #define CONFIG_SYS_NS16550_SERIAL
184 #define CONFIG_SYS_NS16550_REG_SIZE 1
185 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
187 #define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
192 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
193 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
201 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
202 #ifdef CONFIG_PHYS_64BIT
203 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
205 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
207 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
209 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
213 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
215 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
218 * for slave u-boot IMAGE instored in master memory space,
219 * PHYS must be aligned based on the SIZE
221 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
222 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
223 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
224 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
226 * for slave UCODE and ENV instored in master memory space,
227 * PHYS must be aligned based on the SIZE
229 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
230 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
231 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
233 /* slave core release by master*/
234 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
235 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
238 * SRIO_PCIE_BOOT - SLAVE
240 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
241 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
242 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
243 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
247 * eSPI - Enhanced SPI
252 * Memory space is mapped 1-1, but I/O space must start from 0.
255 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
256 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
257 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
258 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
259 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
261 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
262 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
263 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
264 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
265 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
267 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
268 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
269 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
270 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
271 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
274 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
275 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
279 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
281 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
282 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
283 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
284 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
285 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
286 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
287 CONFIG_SYS_BMAN_CENA_SIZE)
288 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
289 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
290 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
291 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
292 #ifdef CONFIG_PHYS_64BIT
293 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
295 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
297 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
298 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
299 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
300 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
301 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
302 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
303 CONFIG_SYS_QMAN_CENA_SIZE)
304 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
305 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
307 #define CONFIG_SYS_DPAA_FMAN
308 #define CONFIG_SYS_DPAA_PME
309 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
311 #ifdef CONFIG_FMAN_ENET
312 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
313 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
314 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
315 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
316 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
318 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
319 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
320 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
321 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
323 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
325 #define CONFIG_SYS_TBIPA_VALUE 8
331 #define CONFIG_LOADS_ECHO /* echo on for serial download */
332 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
335 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
336 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
340 * Miscellaneous configurable options
344 * For booting Linux, the board info and command line data
345 * have to be in the first 64 MB of memory, since this is
346 * the maximum mapped by the Linux kernel during initialization.
348 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
351 * Environment Configuration
353 #define CONFIG_ROOTPATH "/opt/nfsroot"
354 #define CONFIG_UBOOTPATH u-boot.bin
356 #define __USB_PHY_TYPE utmi
358 #define CONFIG_EXTRA_ENV_SETTINGS \
359 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
360 "bank_intlv=cs0_cs1\0" \
362 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
363 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
364 "tftpflash=tftpboot $loadaddr $uboot && " \
365 "protect off $ubootaddr +$filesize && " \
366 "erase $ubootaddr +$filesize && " \
367 "cp.b $loadaddr $ubootaddr $filesize && " \
368 "protect on $ubootaddr +$filesize && " \
369 "cmp.b $loadaddr $ubootaddr $filesize\0" \
370 "consoledev=ttyS0\0" \
371 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
372 "usb_dr_mode=host\0" \
373 "ramdiskaddr=2000000\0" \
374 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
375 "fdtaddr=1e00000\0" \
376 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
379 #include <asm/fsl_secure_boot.h>
381 #endif /* __CONFIG_H */