include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  37 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  38 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  39 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  40 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  41 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_SYS_SRIO
  44 #define CONFIG_SRIO1                    /* SRIO port 1 */
  45 #define CONFIG_SRIO2                    /* SRIO port 2 */
  46 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 #if defined(CONFIG_SPIFLASH)
  50 #elif defined(CONFIG_SDCARD)
  51         #define CONFIG_FSL_FIXED_MMC_LOCATION
  52         #define CONFIG_SYS_MMC_ENV_DEV          0
  53 #endif
  54
  55 #ifndef __ASSEMBLY__
  56 unsigned long get_board_sys_clk(unsigned long dummy);
  57 #include <linux/stringify.h>
  58 #endif
  59 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  60
  61 /*
  62  * These can be toggled for performance analysis, otherwise use default.
  63  */
  64 #define CONFIG_SYS_CACHE_STASHING
  65 #define CONFIG_BACKSIDE_L2_CACHE
  66 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 #define CONFIG_ENABLE_36BIT_PHYS
  70
  71 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  72
  73 /*
  74  *  Config the L3 Cache as L3 SRAM
  75  */
  76 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  77 #ifdef CONFIG_PHYS_64BIT
  78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  79                 CONFIG_RAMBOOT_TEXT_BASE)
  80 #else
  81 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  82 #endif
  83 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  84 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  85
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_DCSRBAR              0xf0000000
  88 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  89 #endif
  90
  91 /* EEPROM */
  92 #define CONFIG_ID_EEPROM
  93 #define CONFIG_SYS_I2C_EEPROM_NXID
  94 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  95 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
  96 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_VERY_BIG_RAM
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104
 105 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 106 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 107
 108 #define CONFIG_DDR_SPD
 109
 110 #define CONFIG_SYS_SPD_BUS_NUM  0
 111 #define SPD_EEPROM_ADDRESS      0x52
 112 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 113
 114 /*
 115  * Local Bus Definitions
 116  */
 117
 118 /* Set the local bus clock 1/8 of platform clock */
 119 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 120
 121 /*
 122  * This board doesn't have a promjet connector.
 123  * However, it uses commone corenet board LAW and TLB.
 124  * It is necessary to use the same start address with proper offset.
 125  */
 126 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 127 #ifdef CONFIG_PHYS_64BIT
 128 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 129 #else
 130 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 131 #endif
 132
 133 #define CONFIG_SYS_FLASH_BR_PRELIM \
 134                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 135                 BR_PS_16 | BR_V)
 136 #define CONFIG_SYS_FLASH_OR_PRELIM \
 137                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 138                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 139
 140 #define CONFIG_FSL_CPLD
 141 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CPLD_BASE_PHYS          0xfffdf0000ull
 144 #else
 145 #define CPLD_BASE_PHYS          CPLD_BASE
 146 #endif
 147
 148 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 149 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 150
 151 #define PIXIS_LBMAP_SWITCH      7
 152 #define PIXIS_LBMAP_MASK        0xf0
 153 #define PIXIS_LBMAP_SHIFT       4
 154 #define PIXIS_LBMAP_ALTBANK     0x40
 155
 156 #define CONFIG_SYS_FLASH_QUIET_TEST
 157 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 158
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 165
 166 #if defined(CONFIG_RAMBOOT_PBL)
 167 #define CONFIG_SYS_RAMBOOT
 168 #endif
 169
 170 #define CONFIG_NAND_FSL_ELBC
 171 /* Nand Flash */
 172 #ifdef CONFIG_NAND_FSL_ELBC
 173 #define CONFIG_SYS_NAND_BASE            0xffa00000
 174 #ifdef CONFIG_PHYS_64BIT
 175 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 176 #else
 177 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 178 #endif
 179
 180 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 181 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 182 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 183
 184 /* NAND flash config */
 185 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 186                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 187                                | BR_PS_8               /* Port Size = 8 bit */ \
 188                                | BR_MS_FCM             /* MSEL = FCM */ \
 189                                | BR_V)                 /* valid */
 190 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 191                                | OR_FCM_PGS            /* Large Page*/ \
 192                                | OR_FCM_CSCT \
 193                                | OR_FCM_CST \
 194                                | OR_FCM_CHT \
 195                                | OR_FCM_SCY_1 \
 196                                | OR_FCM_TRLX \
 197                                | OR_FCM_EHTR)
 198
 199 #ifdef CONFIG_MTD_RAW_NAND
 200 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 201 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 202 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 203 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 204 #else
 205 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 206 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 207 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 208 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 209 #endif
 210 #else
 211 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 212 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 213 #endif /* CONFIG_NAND_FSL_ELBC */
 214
 215 #define CONFIG_SYS_FLASH_EMPTY_INFO
 216 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 217 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 218
 219 #define CONFIG_HWCONFIG
 220
 221 /* define to use L1 as initial stack */
 222 #define CONFIG_L1_INIT_RAM
 223 #define CONFIG_SYS_INIT_RAM_LOCK
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 225 #ifdef CONFIG_PHYS_64BIT
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 228 /* The assembler doesn't like typecast */
 229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 230         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 231           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 232 #else
 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 236 #endif
 237 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 238
 239 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 240                                         GENERATED_GBL_DATA_SIZE)
 241 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 242
 243 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 244 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 245
 246 /* Serial Port - controlled on board with jumper J8
 247  * open - index 2
 248  * shorted - index 1
 249  */
 250 #define CONFIG_SYS_NS16550_SERIAL
 251 #define CONFIG_SYS_NS16550_REG_SIZE     1
 252 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 253
 254 #define CONFIG_SYS_BAUDRATE_TABLE       \
 255         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 256
 257 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 258 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 259 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 260 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 261
 262 /* I2C */
 263 #ifndef CONFIG_DM_I2C
 264 #define CONFIG_SYS_I2C
 265 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 266 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 267 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 268 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 269 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 270 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 271 #else
 272 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 273 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 274 #endif
 275 #define CONFIG_SYS_I2C_FSL
 276
 277
 278 /*
 279  * RapidIO
 280  */
 281 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 282 #ifdef CONFIG_PHYS_64BIT
 283 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 284 #else
 285 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 286 #endif
 287 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 288
 289 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 290 #ifdef CONFIG_PHYS_64BIT
 291 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 292 #else
 293 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 294 #endif
 295 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 296
 297 /*
 298  * for slave u-boot IMAGE instored in master memory space,
 299  * PHYS must be aligned based on the SIZE
 300  */
 301 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 302 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 303 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 304 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 305 /*
 306  * for slave UCODE and ENV instored in master memory space,
 307  * PHYS must be aligned based on the SIZE
 308  */
 309 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 310 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 311 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 312
 313 /* slave core release by master*/
 314 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 315 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 316
 317 /*
 318  * SRIO_PCIE_BOOT - SLAVE
 319  */
 320 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 321 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 322 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 323                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 324 #endif
 325
 326 /*
 327  * eSPI - Enhanced SPI
 328  */
 329
 330 /*
 331  * General PCI
 332  * Memory space is mapped 1-1, but I/O space must start from 0.
 333  */
 334
 335 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 336 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 337 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 338 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 339 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 340
 341 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 342 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 343 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 344 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 345 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 346
 347 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 348 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 349 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 350 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 351 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 352
 353 /* Qman/Bman */
 354 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 355 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 356 #ifdef CONFIG_PHYS_64BIT
 357 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 358 #else
 359 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 360 #endif
 361 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 362 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 363 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 364 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 365 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 366 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 367                                         CONFIG_SYS_BMAN_CENA_SIZE)
 368 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 370 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 371 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 372 #ifdef CONFIG_PHYS_64BIT
 373 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 374 #else
 375 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 376 #endif
 377 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 378 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 379 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 380 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 381 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 382 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 383                                         CONFIG_SYS_QMAN_CENA_SIZE)
 384 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 385 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 386
 387 #define CONFIG_SYS_DPAA_FMAN
 388 #define CONFIG_SYS_DPAA_PME
 389 /* Default address of microcode for the Linux Fman driver */
 390 #if defined(CONFIG_SPIFLASH)
 391 /*
 392  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 393  * env, so we got 0x110000.
 394  */
 395 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 396 #elif defined(CONFIG_SDCARD)
 397 /*
 398  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 399  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 400  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 401  */
 402 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 403 #elif defined(CONFIG_MTD_RAW_NAND)
 404 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 405 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 406 /*
 407  * Slave has no ucode locally, it can fetch this from remote. When implementing
 408  * in two corenet boards, slave's ucode could be stored in master's memory
 409  * space, the address can be mapped from slave TLB->slave LAW->
 410  * slave SRIO or PCIE outbound window->master inbound window->
 411  * master LAW->the ucode address in master's memory space.
 412  */
 413 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 414 #else
 415 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 416 #endif
 417 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 418 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 419
 420 #ifdef CONFIG_PCI
 421 #if !defined(CONFIG_DM_PCI)
 422 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 423 #define CONFIG_PCI_INDIRECT_BRIDGE
 424 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 425 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 426 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 427 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 428 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 429 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 430 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 431 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 432 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 433 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 434 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 435 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 436 #endif
 437
 438 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 439 #endif  /* CONFIG_PCI */
 440
 441 /* SATA */
 442 #define CONFIG_FSL_SATA_V2
 443
 444 #ifdef CONFIG_FSL_SATA_V2
 445 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 446 #define CONFIG_SATA1
 447 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 448 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 449 #define CONFIG_SATA2
 450 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 451 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 452
 453 #define CONFIG_LBA48
 454 #endif
 455
 456 #ifdef CONFIG_FMAN_ENET
 457 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 458 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 459 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 460 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 461 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 462
 463 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 464 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 465 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 466 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 467
 468 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 469
 470 #define CONFIG_SYS_TBIPA_VALUE  8
 471 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 472 #endif
 473
 474 /*
 475  * Environment
 476  */
 477 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 478 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 479
 480 /*
 481 * USB
 482 */
 483 #define CONFIG_HAS_FSL_DR_USB
 484 #define CONFIG_HAS_FSL_MPH_USB
 485
 486 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 487 #define CONFIG_USB_EHCI_FSL
 488 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 489 #endif
 490
 491 #ifdef CONFIG_MMC
 492 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 493 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 494 #endif
 495
 496 /*
 497  * Miscellaneous configurable options
 498  */
 499 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 500
 501 /*
 502  * For booting Linux, the board info and command line data
 503  * have to be in the first 64 MB of memory, since this is
 504  * the maximum mapped by the Linux kernel during initialization.
 505  */
 506 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 507 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 508
 509 #ifdef CONFIG_CMD_KGDB
 510 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 511 #endif
 512
 513 /*
 514  * Environment Configuration
 515  */
 516 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 517 #define CONFIG_BOOTFILE         "uImage"
 518 #define CONFIG_UBOOTPATH        u-boot.bin
 519
 520 /* default location for tftp and bootm */
 521 #define CONFIG_LOADADDR         1000000
 522
 523 #define __USB_PHY_TYPE  utmi
 524
 525 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 526         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 527         "bank_intlv=cs0_cs1\0"                                  \
 528         "netdev=eth0\0"                                         \
 529         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 530         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 531         "tftpflash=tftpboot $loadaddr $uboot && "               \
 532         "protect off $ubootaddr +$filesize && "                 \
 533         "erase $ubootaddr +$filesize && "                       \
 534         "cp.b $loadaddr $ubootaddr $filesize && "               \
 535         "protect on $ubootaddr +$filesize && "                  \
 536         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 537         "consoledev=ttyS0\0"                                    \
 538         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 539         "usb_dr_mode=host\0"                                    \
 540         "ramdiskaddr=2000000\0"                                 \
 541         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 542         "fdtaddr=1e00000\0"                                     \
 543         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 544         "bdev=sda3\0"
 545
 546 #define CONFIG_HDBOOT                                   \
 547         "setenv bootargs root=/dev/$bdev rw "           \
 548         "console=$consoledev,$baudrate $othbootargs;"   \
 549         "tftp $loadaddr $bootfile;"                     \
 550         "tftp $fdtaddr $fdtfile;"                       \
 551         "bootm $loadaddr - $fdtaddr"
 552
 553 #define CONFIG_NFSBOOTCOMMAND                   \
 554         "setenv bootargs root=/dev/nfs rw "     \
 555         "nfsroot=$serverip:$rootpath "          \
 556         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 557         "console=$consoledev,$baudrate $othbootargs;"   \
 558         "tftp $loadaddr $bootfile;"             \
 559         "tftp $fdtaddr $fdtfile;"               \
 560         "bootm $loadaddr - $fdtaddr"
 561
 562 #define CONFIG_RAMBOOTCOMMAND                           \
 563         "setenv bootargs root=/dev/ram rw "             \
 564         "console=$consoledev,$baudrate $othbootargs;"   \
 565         "tftp $ramdiskaddr $ramdiskfile;"               \
 566         "tftp $loadaddr $bootfile;"                     \
 567         "tftp $fdtaddr $fdtfile;"                       \
 568         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 569
 570 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 571
 572 #include <asm/fsl_secure_boot.h>
 573
 574 #endif  /* __CONFIG_H */