include/configs/P1023RDB.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifndef CONFIG_SYS_TEXT_BASE
  14 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  15 #endif
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  23 #endif
  24
  25 /* High Level Configuration Options */
  26 #define CONFIG_MP               /* support multiple processors */
  27
  28 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
  29 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  30 #define CONFIG_PCIE2            /* PCIE controller 2 (slot 2) */
  31 #define CONFIG_PCIE3            /* PCIE controller 3 (slot 3) */
  32 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  33 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  34 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  35
  36 #ifndef __ASSEMBLY__
  37 extern unsigned long get_clock_freq(void);
  38 #endif
  39
  40 #define CONFIG_SYS_CLK_FREQ     66666666
  41 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  42
  43 /*
  44  * These can be toggled for performance analysis, otherwise use default.
  45  */
  46 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  47 #define CONFIG_BTB                      /* toggle branch predition */
  48 #define CONFIG_HWCONFIG
  49
  50 #define CONFIG_ENABLE_36BIT_PHYS
  51
  52 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  53 #define CONFIG_SYS_MEMTEST_END          0x02000000
  54
  55 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  56
  57 /* Implement conversion of addresses in the LBC */
  58 #define CONFIG_SYS_LBC_LBCR             0x00000000
  59 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  60
  61 /* DDR Setup */
  62 #define CONFIG_VERY_BIG_RAM
  63 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  65
  66 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  67 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  68
  69 #define CONFIG_DDR_SPD
  70 #define CONFIG_FSL_DDR_INTERACTIVE
  71 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
  72 #define CONFIG_SYS_SPD_BUS_NUM          0
  73 #define SPD_EEPROM_ADDRESS              0x50
  74 #define CONFIG_SYS_DDR_RAW_TIMING
  75
  76 /*
  77  * Memory map
  78  *
  79  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
  80  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  81  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  82  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  83  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
  84  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
  85  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
  86  *
  87  * Localbus non-cacheable
  88  *
  89  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
  90  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
  91  */
  92
  93 /*
  94  * Local Bus Definitions
  95  */
  96 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
  97 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  98
  99 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 100                                 | BR_PS_16 | BR_V)
 101 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 102
 103 #define CONFIG_FLASH_CFI_DRIVER
 104 #define CONFIG_SYS_FLASH_CFI
 105 #define CONFIG_SYS_FLASH_EMPTY_INFO
 106 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 107 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 108 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 109 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 110
 111 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 112
 113 #define CONFIG_SYS_INIT_RAM_LOCK
 114 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 115 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
 116 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 117                                         GENERATED_GBL_DATA_SIZE)
 118 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 119
 120 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
 121 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 122
 123 #define CONFIG_SYS_NAND_BASE            0xffa00000
 124 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 125
 126 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 127 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 128 #define CONFIG_CMD_NAND
 129 #define CONFIG_NAND_FSL_ELBC
 130 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 131
 132 /* NAND flash config */
 133 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 134                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 135                                 | BR_PS_8               /* Port Size = 8bit */ \
 136                                 | BR_MS_FCM             /* MSEL = FCM */ \
 137                                 | BR_V)                 /* valid */
 138 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
 139                                 | OR_FCM_PGS \
 140                                 | OR_FCM_CSCT \
 141                                 | OR_FCM_CST \
 142                                 | OR_FCM_CHT \
 143                                 | OR_FCM_SCY_1 \
 144                                 | OR_FCM_TRLX \
 145                                 | OR_FCM_EHTR)
 146
 147 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 148 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 149 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 150 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 151
 152 /* Serial Port */
 153 #define CONFIG_CONS_INDEX               1
 154 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 155 #define CONFIG_SYS_NS16550_SERIAL
 156 #define CONFIG_SYS_NS16550_REG_SIZE     1
 157 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 158
 159 #define CONFIG_SYS_BAUDRATE_TABLE       \
 160         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 161
 162 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 163 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 164
 165 /* I2C */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_FSL
 168 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 169 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 170 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 171 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 172 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 173 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 174
 175 /*
 176  * I2C2 EEPROM
 177  */
 178 #define CONFIG_ID_EEPROM
 179 #ifdef CONFIG_ID_EEPROM
 180 #define CONFIG_SYS_I2C_EEPROM_NXID
 181 #endif
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 184 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 185
 186 /*
 187  * General PCI
 188  * Memory space is mapped 1-1, but I/O space must start from 0.
 189  */
 190
 191 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 192 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 193 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 194 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 195 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 196 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 197 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 198 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 199 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 200 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 201
 202 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 203 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 204 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 205 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 206 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 207 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 208 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 209 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 210 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 211 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 212
 213 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 214 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 215 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 216 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 217 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 218 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 219 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 220 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 221 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 222 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 223
 224 #if defined(CONFIG_PCI)
 225 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 226 #endif  /* CONFIG_PCI */
 227
 228 /*
 229  * Environment
 230  */
 231 #define CONFIG_ENV_OVERWRITE
 232
 233 #define CONFIG_ENV_IS_IN_FLASH
 234 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 235 #define CONFIG_ENV_SIZE         0x2000
 236 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 237
 238 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 239 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 240
 241 /*
 242  * Command line configuration.
 243  */
 244 #define CONFIG_CMD_IRQ
 245 #define CONFIG_CMD_REGINFO
 246
 247 #if defined(CONFIG_PCI)
 248 #define CONFIG_CMD_PCI
 249 #endif
 250
 251 /*
 252  * USB
 253  */
 254 #define CONFIG_HAS_FSL_DR_USB
 255 #ifdef CONFIG_HAS_FSL_DR_USB
 256 #define CONFIG_USB_EHCI
 257
 258 #ifdef CONFIG_USB_EHCI
 259 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 260 #define CONFIG_USB_EHCI_FSL
 261 #endif
 262 #endif
 263
 264 /*
 265  * Miscellaneous configurable options
 266  */
 267 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 268 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 269 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 270 #if defined(CONFIG_CMD_KGDB)
 271 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 272 #else
 273 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 274 #endif
 275 /* Print Buffer Size */
 276 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 277 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 278 /* Boot Argument Buffer Size */
 279 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 280
 281 /*
 282  * For booting Linux, the board info and command line data
 283  * have to be in the first 64 MB of memory, since this is
 284  * the maximum mapped by the Linux kernel during initialization.
 285  */
 286 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
 287 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
 288
 289 /*
 290  * Environment Configuration
 291  */
 292 #define CONFIG_BOOTFILE         "uImage"
 293 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 294
 295 /* default location for tftp and bootm */
 296 #define CONFIG_LOADADDR         1000000
 297
 298
 299 #define CONFIG_BAUDRATE 115200
 300
 301 /* Qman/Bman */
 302 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 303 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 304 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 305 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 306 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 307 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 308 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 309 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 310 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 311                                         CONFIG_SYS_QMAN_CENA_SIZE)
 312 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 313 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 314 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 315 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 316 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 317 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 318 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 319 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 320 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 321 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 322                                         CONFIG_SYS_BMAN_CENA_SIZE)
 323 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 324 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 325
 326 /* For FM */
 327 #define CONFIG_SYS_DPAA_FMAN
 328 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 329
 330 #ifdef CONFIG_SYS_DPAA_FMAN
 331 #define CONFIG_FMAN_ENET
 332 #define CONFIG_PHY_ATHEROS
 333 #endif
 334
 335 /* Default address of microcode for the Linux Fman driver */
 336 /* QE microcode/firmware address */
 337 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 338 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 339 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 340 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 341
 342 #ifdef CONFIG_FMAN_ENET
 343 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
 344 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
 345
 346 #define CONFIG_SYS_TBIPA_VALUE  8
 347 #define CONFIG_MII              /* MII PHY management */
 348 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 349 #endif
 350
 351 #define CONFIG_EXTRA_ENV_SETTINGS       \
 352         "netdev=eth0\0"                                         \
 353         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 354         "loadaddr=1000000\0"                                    \
 355         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 356         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 357                 "protect off $ubootaddr +$filesize; "           \
 358                 "erase $ubootaddr +$filesize; "                 \
 359                 "cp.b $loadaddr $ubootaddr $filesize; "         \
 360                 "protect on $ubootaddr +$filesize; "            \
 361                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 362         "consoledev=ttyS0\0"                                    \
 363         "ramdiskaddr=2000000\0"                                 \
 364         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 365         "fdtaddr=1e00000\0"                                     \
 366         "fdtfile=p1023rdb.dtb\0"                                \
 367         "othbootargs=ramdisk_size=600000\0"                     \
 368         "bdev=sda1\0"                                           \
 369         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 370
 371 #define CONFIG_HDBOOT                                   \
 372         "setenv bootargs root=/dev/$bdev rw "           \
 373         "console=$consoledev,$baudrate $othbootargs;"   \
 374         "tftp $loadaddr $bootfile;"                     \
 375         "tftp $fdtaddr $fdtfile;"                       \
 376         "bootm $loadaddr - $fdtaddr"
 377
 378 #define CONFIG_NFSBOOTCOMMAND                                           \
 379         "setenv bootargs root=/dev/nfs rw "                             \
 380         "nfsroot=$serverip:$rootpath "                                  \
 381         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 382         "console=$consoledev,$baudrate $othbootargs;"                   \
 383         "tftp $loadaddr $bootfile;"                                     \
 384         "tftp $fdtaddr $fdtfile;"                                       \
 385         "bootm $loadaddr - $fdtaddr"
 386
 387 #define CONFIG_RAMBOOTCOMMAND                                           \
 388         "setenv bootargs root=/dev/ram rw "                             \
 389         "console=$consoledev,$baudrate $othbootargs;"                   \
 390         "tftp $ramdiskaddr $ramdiskfile;"                               \
 391         "tftp $loadaddr $bootfile;"                                     \
 392         "tftp $fdtaddr $fdtfile;"                                       \
 393         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 394
 395 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 396
 397 #endif  /* __CONFIG_H */