include/configs/P1022DS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   4  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   5  *          Timur Tabi <timur@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include "../board/freescale/common/ics307_clk.h"
  12
  13 #ifdef CONFIG_SDCARD
  14 #define CONFIG_SPL_FLUSH_IMAGE
  15 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  16 #define CONFIG_SPL_PAD_TO               0x20000
  17 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  18 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  19 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  20 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  21 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  22 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  23 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  24 #ifdef CONFIG_SPL_BUILD
  25 #define CONFIG_SPL_COMMON_INIT_DDR
  26 #endif
  27 #endif
  28
  29 #ifdef CONFIG_SPIFLASH
  30 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  33 #define CONFIG_SPL_PAD_TO               0x20000
  34 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #endif
  44 #endif
  45
  46 #define CONFIG_NAND_FSL_ELBC
  47 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  48 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  49
  50 #ifdef CONFIG_NAND
  51 #ifdef CONFIG_TPL_BUILD
  52 #define CONFIG_SPL_FLUSH_IMAGE
  53 #define CONFIG_SPL_NAND_INIT
  54 #define CONFIG_SPL_COMMON_INIT_DDR
  55 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  56 #define CONFIG_TPL_TEXT_BASE            0xf8f81000
  57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  59 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  60 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  61 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  62 #elif defined(CONFIG_SPL_BUILD)
  63 #define CONFIG_SPL_INIT_MINIMAL
  64 #define CONFIG_SPL_FLUSH_IMAGE
  65 #define CONFIG_SPL_MAX_SIZE             4096
  66 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  67 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  68 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  69 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  70 #endif
  71 #define CONFIG_SPL_PAD_TO               0x20000
  72 #define CONFIG_TPL_PAD_TO               0x20000
  73 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  74 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  75 #endif
  76
  77 /* High Level Configuration Options */
  78
  79 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  80 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  81 #endif
  82
  83 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  84 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
  85 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
  86 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  87 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  88 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  89
  90 #define CONFIG_ENABLE_36BIT_PHYS
  91
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CONFIG_ADDR_MAP
  94 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  95 #endif
  96
  97 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  98 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  99 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 100
 101 /*
 102  * These can be toggled for performance analysis, otherwise use default.
 103  */
 104 #define CONFIG_L2_CACHE
 105 #define CONFIG_BTB
 106
 107 #define CONFIG_SYS_MEMTEST_START        0x00000000
 108 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 109
 110 #define CONFIG_SYS_CCSRBAR              0xffe00000
 111 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 112
 113 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 114        SPL code*/
 115 #ifdef CONFIG_SPL_BUILD
 116 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 117 #endif
 118
 119 /* DDR Setup */
 120 #define CONFIG_DDR_SPD
 121 #define CONFIG_VERY_BIG_RAM
 122
 123 #ifdef CONFIG_DDR_ECC
 124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 125 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 126 #endif
 127
 128 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 129 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 130
 131 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 132 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 133
 134 /* I2C addresses of SPD EEPROMs */
 135 #define CONFIG_SYS_SPD_BUS_NUM          1
 136 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 137
 138 /* These are used when DDR doesn't use SPD.  */
 139 #define CONFIG_SYS_SDRAM_SIZE           2048
 140 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 141 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 142 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 143 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 144 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 145 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 146 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 147 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 148 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 149 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 150 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 151 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 152 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 153 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 154 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 155 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 156 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 157 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 158 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 159 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 160
 161 /*
 162  * Memory map
 163  *
 164  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 165  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 166  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 167  *
 168  * Localbus cacheable (TBD)
 169  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 170  *
 171  * Localbus non-cacheable
 172  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 173  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 174  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 175  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 176  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 177  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 178  */
 179
 180 /*
 181  * Local Bus Definitions
 182  */
 183 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 184 #ifdef CONFIG_PHYS_64BIT
 185 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 186 #else
 187 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 188 #endif
 189
 190 #define CONFIG_FLASH_BR_PRELIM  \
 191         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 192 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 193
 194 #ifdef CONFIG_NAND
 195 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 196 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 197 #else
 198 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 199 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 200 #endif
 201
 202 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 203 #define CONFIG_SYS_FLASH_QUIET_TEST
 204 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 205
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 207 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 208
 209 #ifndef CONFIG_SYS_MONITOR_BASE
 210 #ifdef CONFIG_TPL_BUILD
 211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_TPL_TEXT_BASE
 212 #elif defined(CONFIG_SPL_BUILD)
 213 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 214 #else
 215 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 216 #endif
 217 #endif
 218
 219 #define CONFIG_SYS_FLASH_EMPTY_INFO
 220
 221 /* Nand Flash */
 222 #if defined(CONFIG_NAND_FSL_ELBC)
 223 #define CONFIG_SYS_NAND_BASE            0xff800000
 224 #ifdef CONFIG_PHYS_64BIT
 225 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 226 #else
 227 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 228 #endif
 229
 230 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 231 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 232 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 233 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 234
 235 /* NAND flash config */
 236 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 237                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 238                                | BR_PS_8               /* Port Size = 8 bit */ \
 239                                | BR_MS_FCM             /* MSEL = FCM */ \
 240                                | BR_V)                 /* valid */
 241 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 242                                | OR_FCM_PGS            /* Large Page*/ \
 243                                | OR_FCM_CSCT \
 244                                | OR_FCM_CST \
 245                                | OR_FCM_CHT \
 246                                | OR_FCM_SCY_1 \
 247                                | OR_FCM_TRLX \
 248                                | OR_FCM_EHTR)
 249 #ifdef CONFIG_NAND
 250 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 251 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 252 #else
 253 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 254 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 255 #endif
 256
 257 #endif /* CONFIG_NAND_FSL_ELBC */
 258
 259 #define CONFIG_HWCONFIG
 260
 261 #define CONFIG_FSL_NGPIXIS
 262 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 263 #ifdef CONFIG_PHYS_64BIT
 264 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 265 #else
 266 #define PIXIS_BASE_PHYS         PIXIS_BASE
 267 #endif
 268
 269 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 270 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 271
 272 #define PIXIS_LBMAP_SWITCH      7
 273 #define PIXIS_LBMAP_MASK        0xF0
 274 #define PIXIS_LBMAP_ALTBANK     0x20
 275 #define PIXIS_SPD               0x07
 276 #define PIXIS_SPD_SYSCLK_MASK   0x07
 277 #define PIXIS_ELBC_SPI_MASK     0xc0
 278 #define PIXIS_SPI               0x80
 279
 280 #define CONFIG_SYS_INIT_RAM_LOCK
 281 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 282 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 283
 284 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 285         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 286 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 289 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 290
 291 /*
 292  * Config the L2 Cache as L2 SRAM
 293 */
 294 #if defined(CONFIG_SPL_BUILD)
 295 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 296 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 297 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 298 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 299 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 300 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 301 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 302 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 303 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 304 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 305 #elif defined(CONFIG_NAND)
 306 #ifdef CONFIG_TPL_BUILD
 307 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 308 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 309 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 310 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 311 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 312 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 313 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 314 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 315 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 316 #else
 317 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 318 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 319 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 320 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 321 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 322 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 323 #endif
 324 #endif
 325 #endif
 326
 327 /*
 328  * Serial Port
 329  */
 330 #define CONFIG_SYS_NS16550_SERIAL
 331 #define CONFIG_SYS_NS16550_REG_SIZE     1
 332 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 333 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 334 #define CONFIG_NS16550_MIN_FUNCTIONS
 335 #endif
 336
 337 #define CONFIG_SYS_BAUDRATE_TABLE       \
 338         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 339
 340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 342
 343 /* Video */
 344
 345 #ifdef CONFIG_FSL_DIU_FB
 346 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 347 #define CONFIG_VIDEO_LOGO
 348 #define CONFIG_VIDEO_BMP_LOGO
 349 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 350 /*
 351  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 352  * disable empty flash sector detection, which is I/O-intensive.
 353  */
 354 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 355 #endif
 356
 357 #ifdef CONFIG_ATI
 358 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 359 #define CONFIG_BIOSEMU
 360 #define CONFIG_ATI_RADEON_FB
 361 #define CONFIG_VIDEO_LOGO
 362 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 363 #endif
 364
 365 /* I2C */
 366 #define CONFIG_SYS_I2C
 367 #define CONFIG_SYS_I2C_FSL
 368 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 369 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 370 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 371 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 372 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 373 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 374 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 375
 376 /*
 377  * I2C2 EEPROM
 378  */
 379 #define CONFIG_ID_EEPROM
 380 #define CONFIG_SYS_I2C_EEPROM_NXID
 381 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 382 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 383 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 384
 385 /*
 386  * General PCI
 387  * Memory space is mapped 1-1, but I/O space must start from 0.
 388  */
 389
 390 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 391 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 392 #ifdef CONFIG_PHYS_64BIT
 393 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 394 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 395 #else
 396 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 397 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 398 #endif
 399 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 400 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 401 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 402 #ifdef CONFIG_PHYS_64BIT
 403 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 404 #else
 405 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 406 #endif
 407 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 408
 409 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 410 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 411 #ifdef CONFIG_PHYS_64BIT
 412 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 413 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 414 #else
 415 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 416 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 417 #endif
 418 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 419 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 420 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 421 #ifdef CONFIG_PHYS_64BIT
 422 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 423 #else
 424 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 425 #endif
 426 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 427
 428 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 429 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 430 #ifdef CONFIG_PHYS_64BIT
 431 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 432 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 433 #else
 434 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 435 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 436 #endif
 437 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 438 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 439 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 440 #ifdef CONFIG_PHYS_64BIT
 441 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 442 #else
 443 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 444 #endif
 445 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 446
 447 #ifdef CONFIG_PCI
 448 #define CONFIG_PCI_INDIRECT_BRIDGE
 449 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 450 #endif
 451
 452 /* SATA */
 453 #define CONFIG_FSL_SATA_V2
 454
 455 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 456 #define CONFIG_SATA1
 457 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 458 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 459 #define CONFIG_SATA2
 460 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 461 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 462
 463 #ifdef CONFIG_FSL_SATA
 464 #define CONFIG_LBA48
 465 #endif
 466
 467 #ifdef CONFIG_MMC
 468 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 469 #endif
 470
 471 #ifdef CONFIG_TSEC_ENET
 472
 473 #define CONFIG_TSECV2
 474
 475 #define CONFIG_TSEC1            1
 476 #define CONFIG_TSEC1_NAME       "eTSEC1"
 477 #define CONFIG_TSEC2            1
 478 #define CONFIG_TSEC2_NAME       "eTSEC2"
 479
 480 #define TSEC1_PHY_ADDR          1
 481 #define TSEC2_PHY_ADDR          2
 482
 483 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 484 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 485
 486 #define TSEC1_PHYIDX            0
 487 #define TSEC2_PHYIDX            0
 488
 489 #define CONFIG_ETHPRIME         "eTSEC1"
 490 #endif
 491
 492 /*
 493  * Dynamic MTD Partition support with mtdparts
 494  */
 495
 496 /*
 497  * Environment
 498  */
 499 #ifdef CONFIG_SPIFLASH
 500 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 501 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 502 #define CONFIG_ENV_SECT_SIZE    0x10000
 503 #elif defined(CONFIG_SDCARD)
 504 #define CONFIG_FSL_FIXED_MMC_LOCATION
 505 #define CONFIG_ENV_SIZE         0x2000
 506 #define CONFIG_SYS_MMC_ENV_DEV  0
 507 #elif defined(CONFIG_NAND)
 508 #ifdef CONFIG_TPL_BUILD
 509 #define CONFIG_ENV_SIZE         0x2000
 510 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 511 #else
 512 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 513 #endif
 514 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 515 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 516 #elif defined(CONFIG_SYS_RAMBOOT)
 517 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 518 #define CONFIG_ENV_SIZE         0x2000
 519 #else
 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 521 #define CONFIG_ENV_SIZE         0x2000
 522 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 523 #endif
 524
 525 #define CONFIG_LOADS_ECHO
 526 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 527
 528 /*
 529  * USB
 530  */
 531 #define CONFIG_HAS_FSL_DR_USB
 532 #ifdef CONFIG_HAS_FSL_DR_USB
 533 #ifdef CONFIG_USB_EHCI_HCD
 534 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 535 #define CONFIG_USB_EHCI_FSL
 536 #endif
 537 #endif
 538
 539 /*
 540  * Miscellaneous configurable options
 541  */
 542 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 543
 544 /*
 545  * For booting Linux, the board info and command line data
 546  * have to be in the first 64 MB of memory, since this is
 547  * the maximum mapped by the Linux kernel during initialization.
 548  */
 549 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 550 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 551
 552 #ifdef CONFIG_CMD_KGDB
 553 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 554 #endif
 555
 556 /*
 557  * Environment Configuration
 558  */
 559
 560 #define CONFIG_HOSTNAME         "p1022ds"
 561 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 562 #define CONFIG_BOOTFILE         "uImage"
 563 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 564
 565 #define CONFIG_LOADADDR         1000000
 566
 567 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 568         "netdev=eth0\0"                                         \
 569         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 570         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 571         "tftpflash=tftpboot $loadaddr $uboot && "               \
 572                 "protect off $ubootaddr +$filesize && "         \
 573                 "erase $ubootaddr +$filesize && "               \
 574                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 575                 "protect on $ubootaddr +$filesize && "          \
 576                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 577         "consoledev=ttyS0\0"                                    \
 578         "ramdiskaddr=2000000\0"                                 \
 579         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 580         "fdtaddr=1e00000\0"                                     \
 581         "fdtfile=p1022ds.dtb\0"                                 \
 582         "bdev=sda3\0"                                           \
 583         "hwconfig=esdhc;audclk:12\0"
 584
 585 #define CONFIG_HDBOOT                                   \
 586         "setenv bootargs root=/dev/$bdev rw "           \
 587         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 588         "tftp $loadaddr $bootfile;"                     \
 589         "tftp $fdtaddr $fdtfile;"                       \
 590         "bootm $loadaddr - $fdtaddr"
 591
 592 #define CONFIG_NFSBOOTCOMMAND                                           \
 593         "setenv bootargs root=/dev/nfs rw "                             \
 594         "nfsroot=$serverip:$rootpath "                                  \
 595         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 596         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 597         "tftp $loadaddr $bootfile;"                                     \
 598         "tftp $fdtaddr $fdtfile;"                                       \
 599         "bootm $loadaddr - $fdtaddr"
 600
 601 #define CONFIG_RAMBOOTCOMMAND                                           \
 602         "setenv bootargs root=/dev/ram rw "                             \
 603         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 604         "tftp $ramdiskaddr $ramdiskfile;"                               \
 605         "tftp $loadaddr $bootfile;"                                     \
 606         "tftp $fdtaddr $fdtfile;"                                       \
 607         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 608
 609 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 610
 611 #endif